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From: Daniel Vetter <daniel@ffwll.ch>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 12/14] drm/i915: Clean up eDP PLL state asserts
Date: Fri, 30 Oct 2015 16:53:42 +0100	[thread overview]
Message-ID: <20151030155342.GG16848@phenom.ffwll.local> (raw)
In-Reply-To: <1446146763-31821-13-git-send-email-ville.syrjala@linux.intel.com>

On Thu, Oct 29, 2015 at 09:26:01PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Rewrite the eDP PLL state asserts to conform to our usual state assert
> style.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 54 +++++++++++++++++++++++++++++------------
>  1 file changed, 39 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 763b0ef..e259803 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2142,21 +2142,48 @@ static void intel_edp_backlight_power(struct intel_connector *connector,
>  		_intel_edp_backlight_off(intel_dp);
>  }
>  
> +static const char *state_string(bool enabled)
> +{
> +	return enabled ? "on" : "off";
> +}
> +
> +static void assert_dp_port(struct intel_dp *intel_dp, bool state)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> +	bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
> +
> +	I915_STATE_WARN(cur_state != state,
> +			"DP port %c state assertion failure (expected %s, current %s)\n",
> +			port_name(dig_port->port),
> +			state_string(state), state_string(cur_state));
> +}
> +#define assert_dp_port_disabled(d) assert_dp_port((d), false)
> +
> +static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
> +{
> +	bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
> +
> +	I915_STATE_WARN(cur_state != state,
> +			"eDP PLL state assertion failure (expected %s, current %s)\n",
> +			state_string(state), state_string(cur_state));
> +}
> +#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
> +#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
> +
>  static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> -	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 dpa_ctl;
>  
> -	assert_pipe_disabled(dev_priv,
> -			     to_intel_crtc(crtc)->pipe);
> +	assert_pipe_disabled(dev_priv, crtc->pipe);
> +	assert_dp_port_disabled(intel_dp);
> +	assert_edp_pll_disabled(dev_priv);
>  
>  	DRM_DEBUG_KMS("\n");
>  	dpa_ctl = I915_READ(DP_A);
> -	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
> -	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
>  
>  	/* We don't adjust intel_dp->DP while tearing down the link, to
>  	 * facilitate link retraining (e.g. after hotplug). Hence clear all
> @@ -2171,18 +2198,15 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
>  static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> -	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 dpa_ctl;
>  
> -	assert_pipe_disabled(dev_priv,
> -			     to_intel_crtc(crtc)->pipe);
> +	assert_pipe_disabled(dev_priv, crtc->pipe);
> +	assert_dp_port_disabled(intel_dp);
> +	assert_edp_pll_enabled(dev_priv);
>  
>  	dpa_ctl = I915_READ(DP_A);
> -	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
> -	     "dp pll off, should be on\n");
> -	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
>  
>  	/* We can't rely on the value tracked for the DP register in
>  	 * intel_dp->DP because link_down must not change that (otherwise link
> -- 
> 2.4.10
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2015-10-30 15:53 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-29 19:25 [PATCH 00/14] drm/i915: FIFO underrun elimination for PCH platforms ville.syrjala
2015-10-29 19:25 ` [PATCH 01/14] drm/i915: Don't use intel_pipe_to_cpu_transcoder() when there's a pipe config around ville.syrjala
2015-10-29 19:34   ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 02/14] drm/i915: Set sync polarity from adjusted mode for TRANS_DP_CTL ville.syrjala
2015-10-29 19:33   ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 03/14] drm/i915: Enable PCH FIFO underruns later on ILK/SNB/IVB ville.syrjala
2015-10-29 19:34   ` Jesse Barnes
2015-10-29 19:57   ` Paulo Zanoni
2015-10-29 21:21     ` Ville Syrjälä
2015-10-30 15:42       ` Daniel Vetter
2015-10-30 10:06   ` Jani Nikula
2015-10-30 12:08     ` Ville Syrjälä
2015-10-30 12:31       ` Jani Nikula
2015-10-30 15:41       ` Daniel Vetter
2015-10-30 17:20   ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 04/14] drm/i915: Enable PCH FIFO underruns later on HSW+ ville.syrjala
2015-10-29 19:34   ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 05/14] drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabled ville.syrjala
2015-10-29 19:36   ` Jesse Barnes
2015-10-29 21:39     ` Ville Syrjälä
2015-10-30 17:21   ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 06/14] drm/i915: Check for FIFO underruns after modeset on IVB/HSW and CPT/PPT ville.syrjala
2015-10-30 15:45   ` Daniel Vetter
2015-10-30 17:22   ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 07/14] drm/i915: Check for CPT and not !IBX in ironlake_disable_pch_transcoder() ville.syrjala
2015-10-29 19:37   ` Jesse Barnes
2015-10-29 19:25 ` [PATCH 08/14] drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaround ville.syrjala
2015-10-29 19:38   ` Jesse Barnes
2015-10-30 10:11   ` Jani Nikula
2015-10-30 12:15     ` Ville Syrjälä
2015-10-30 17:23   ` [PATCH v2 " ville.syrjala
2015-10-29 19:25 ` [PATCH 09/14] drm/i915: Hide underruns from eDP PLL and port enable on ILK ville.syrjala
2015-10-29 19:39   ` Jesse Barnes
2015-10-29 21:33     ` Ville Syrjälä
2015-10-29 19:25 ` [PATCH 10/14] drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/ ville.syrjala
2015-10-30 15:49   ` Daniel Vetter
2015-10-29 19:26 ` [PATCH 11/14] drm/i915: Remove ILK-A eDP PLL workaround notes ville.syrjala
2015-10-29 19:40   ` Jesse Barnes
2015-10-29 19:26 ` [PATCH 12/14] drm/i915: Clean up eDP PLL state asserts ville.syrjala
2015-10-30 15:53   ` Daniel Vetter [this message]
2015-10-29 19:26 ` [PATCH 13/14] drm/i915: Use intel_dp->DP in eDP PLL setup ville.syrjala
2015-10-30 16:00   ` Daniel Vetter
2015-10-30 16:36     ` Ville Syrjälä
2015-11-10 14:37       ` Jani Nikula
2015-11-10 14:16   ` [PATCH v2 " ville.syrjala
2015-11-10 14:43     ` Jani Nikula
2015-10-29 19:26 ` [PATCH 14/14] drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on() ville.syrjala
2015-10-30 16:01   ` Daniel Vetter
2015-10-30 13:30 ` [PATCH 00/14] drm/i915: FIFO underrun elimination for PCH platforms Jani Nikula
2015-11-10 15:04 ` Ville Syrjälä

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