From: Zhiyuan Lv <zhiyuan.lv@intel.com>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org, Eddie Dong <eddie.dong@intel.com>
Subject: Re: [PATCH 25/29] drm/i915: Pull the vgpu uncore funcs apart from the rest of gen6+
Date: Thu, 5 Nov 2015 15:33:57 +0800 [thread overview]
Message-ID: <20151105073357.GA14247@zlv-hp-dev> (raw)
In-Reply-To: <1446672017-24497-26-git-send-email-ville.syrjala@linux.intel.com>
On Wed, Nov 04, 2015 at 11:20:13PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I need to add a new variable into GEN6_{READ,WRITE}_HEADER, but the vgpu
> won't need it, so let's avoid an unused variable warning by splitting
> the vgpu stuff to use its own macros.
>
> Cc: Eddie Dong <eddie.dong@intel.com>
> Cc: Jike Song <jike.song@intel.com>
> Cc: Kevin Tian <kevin.tian@intel.com>
> Cc: Yu Zhang <yu.c.zhang@linux.intel.com>
> Cc: Zhi Wang <zhi.a.wang@intel.com>
> Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
It looks good to me. Thanks!
Reviewed-by: Zhiyuan Lv <zhiyuan.lv@intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 80 +++++++++++++++++++++++++------------
> 1 file changed, 54 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index ced494a..52ba23d 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -701,14 +701,6 @@ static inline void __force_wake_get(struct drm_i915_private *dev_priv,
> dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
> }
>
> -#define __vgpu_read(x) \
> -static u##x \
> -vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> - GEN6_READ_HEADER(x); \
> - val = __raw_i915_read##x(dev_priv, reg); \
> - GEN6_READ_FOOTER; \
> -}
> -
> #define __gen6_read(x) \
> static u##x \
> gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> @@ -783,10 +775,6 @@ gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> GEN6_READ_FOOTER; \
> }
>
> -__vgpu_read(8)
> -__vgpu_read(16)
> -__vgpu_read(32)
> -__vgpu_read(64)
> __gen9_read(8)
> __gen9_read(16)
> __gen9_read(32)
> @@ -808,10 +796,37 @@ __gen6_read(64)
> #undef __chv_read
> #undef __vlv_read
> #undef __gen6_read
> -#undef __vgpu_read
> #undef GEN6_READ_FOOTER
> #undef GEN6_READ_HEADER
>
> +#define VGPU_READ_HEADER(x) \
> + unsigned long irqflags; \
> + u##x val = 0; \
> + assert_device_not_suspended(dev_priv); \
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
> +
> +#define VGPU_READ_FOOTER \
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
> + trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
> + return val
> +
> +#define __vgpu_read(x) \
> +static u##x \
> +vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> + VGPU_READ_HEADER(x); \
> + val = __raw_i915_read##x(dev_priv, reg); \
> + VGPU_READ_FOOTER; \
> +}
> +
> +__vgpu_read(8)
> +__vgpu_read(16)
> +__vgpu_read(32)
> +__vgpu_read(64)
> +
> +#undef __vgpu_read
> +#undef VGPU_READ_FOOTER
> +#undef VGPU_READ_HEADER
> +
> #define GEN2_WRITE_HEADER \
> trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
> assert_device_not_suspended(dev_priv); \
> @@ -892,14 +907,6 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
> GEN6_WRITE_FOOTER; \
> }
>
> -#define __vgpu_write(x) \
> -static void vgpu_write##x(struct drm_i915_private *dev_priv, \
> - off_t reg, u##x val, bool trace) { \
> - GEN6_WRITE_HEADER; \
> - __raw_i915_write##x(dev_priv, reg, val); \
> - GEN6_WRITE_FOOTER; \
> -}
> -
> static const u32 gen8_shadowed_regs[] = {
> FORCEWAKE_MT,
> GEN6_RPNSWREQ,
> @@ -1023,20 +1030,41 @@ __gen6_write(8)
> __gen6_write(16)
> __gen6_write(32)
> __gen6_write(64)
> -__vgpu_write(8)
> -__vgpu_write(16)
> -__vgpu_write(32)
> -__vgpu_write(64)
>
> #undef __gen9_write
> #undef __chv_write
> #undef __gen8_write
> #undef __hsw_write
> #undef __gen6_write
> -#undef __vgpu_write
> #undef GEN6_WRITE_FOOTER
> #undef GEN6_WRITE_HEADER
>
> +#define VGPU_WRITE_HEADER \
> + unsigned long irqflags; \
> + trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
> + assert_device_not_suspended(dev_priv); \
> + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
> +
> +#define VGPU_WRITE_FOOTER \
> + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
> +
> +#define __vgpu_write(x) \
> +static void vgpu_write##x(struct drm_i915_private *dev_priv, \
> + off_t reg, u##x val, bool trace) { \
> + VGPU_WRITE_HEADER; \
> + __raw_i915_write##x(dev_priv, reg, val); \
> + VGPU_WRITE_FOOTER; \
> +}
> +
> +__vgpu_write(8)
> +__vgpu_write(16)
> +__vgpu_write(32)
> +__vgpu_write(64)
> +
> +#undef __vgpu_write
> +#undef VGPU_WRITE_FOOTER
> +#undef VGPU_WRITE_HEADER
> +
> #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
> do { \
> dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
> --
> 2.4.10
>
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next prev parent reply other threads:[~2015-11-05 7:42 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-04 21:19 [PATCH v2 00/29] drm/i915: Type safe register read/write (v2) and more prep work ville.syrjala
2015-11-04 21:19 ` [PATCH 01/29] pci: Decouple quirks.c from i915_reg.h ville.syrjala
2015-11-05 13:37 ` Chris Wilson
2015-11-24 17:09 ` Bjorn Helgaas
2015-11-04 21:19 ` [PATCH 02/29] drm/i915: Remove the magic AUX_CTL is at DP + foo tricks ville.syrjala
2015-11-06 13:21 ` Chris Wilson
2015-11-04 21:19 ` [PATCH 03/29] drm/i915: Replace the aux ddc name switch statement with a table ville.syrjala
2015-11-05 14:10 ` Chris Wilson
2015-11-05 14:22 ` Ville Syrjälä
2015-11-05 14:33 ` Chris Wilson
2015-11-04 21:19 ` [PATCH v3 04/29] drm/i915: Parametrize AUX registers ville.syrjala
2015-11-06 13:25 ` Chris Wilson
2015-11-06 13:41 ` Ville Syrjälä
2015-11-04 21:19 ` [PATCH v2 05/29] drm/i915: Add dev_priv->psr_mmio_base ville.syrjala
2015-11-05 14:40 ` Chris Wilson
2015-11-05 14:51 ` Ville Syrjälä
2015-11-04 21:19 ` [PATCH v3 06/29] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[] ville.syrjala
2015-11-06 13:23 ` Chris Wilson
2015-11-04 21:19 ` [PATCH v2 07/29] drm/i915: Model PSR AUX register selection more like the normal AUX code ville.syrjala
2015-11-05 21:34 ` Chris Wilson
2015-11-04 21:19 ` [PATCH 08/29] drm/i915: s/PCH_DP_/PORT_/ in intel_trans_dp_port_sel() and move it next to its only user ville.syrjala
2015-11-05 13:54 ` Chris Wilson
2015-11-04 21:19 ` [PATCH 09/29] drm/i915: Replace aux_ch_ctl_reg check with port check ville.syrjala
2015-11-05 13:55 ` Chris Wilson
2015-11-04 21:19 ` [PATCH 10/29] drm/i915: s/is_sdvob/enum port/ ville.syrjala
2015-11-05 14:05 ` Chris Wilson
2015-11-06 19:29 ` [PATCH v2 " ville.syrjala
2015-11-04 21:19 ` [PATCH 11/29] drm/i915: Store DVO SRCDIM register offset under intel_dvo_device ville.syrjala
2015-11-05 11:10 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 12/29] drm/i915: Streamline gpio_mmio_base deduction ville.syrjala
2015-11-18 9:46 ` Daniel Vetter
2015-11-04 21:20 ` [PATCH 13/29] drm/i915: Prefix raw register defines with underscore ville.syrjala
2015-11-05 13:50 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 14/29] drm/i915: Parametrize L3 error registers ville.syrjala
2015-11-05 11:22 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 15/29] drm/i915: Parametrize MOCS registers ville.syrjala
2015-11-05 11:15 ` Chris Wilson
2015-11-05 12:13 ` [PATCH v2 " ville.syrjala
2015-11-05 13:24 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 16/29] drm/i915: s/0x50/RING_PSMI_CTL/ ville.syrjala
2015-11-05 11:16 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 17/29] drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctl ville.syrjala
2015-11-05 10:59 ` Chris Wilson
2015-11-05 11:41 ` Ville Syrjälä
2015-11-05 13:33 ` Chris Wilson
2015-11-06 19:43 ` [PATCH v2 " ville.syrjala
2015-11-18 12:30 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 18/29] drm/i915: Make the cmd parser 64bit regs explicit ville.syrjala
2015-11-05 11:02 ` Chris Wilson
2015-11-06 19:44 ` [PATCH v2 " ville.syrjala
2015-11-04 21:20 ` [PATCH v2 19/29] drm/i915: Add functions to emit register offsets to the ring ville.syrjala
2015-11-05 11:03 ` Chris Wilson
2015-11-05 11:44 ` Ville Syrjälä
2015-11-05 12:01 ` Chris Wilson
2015-11-05 12:05 ` Ville Syrjälä
2015-11-04 21:20 ` [PATCH 20/29] drm/i915: Add wa_ctx_emit_reg() ville.syrjala
2015-11-05 11:04 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 21/29] drm/i915: Wrap ASSIGN_CTX_{PDP, PM4L} in do {} while(0) ville.syrjala
2015-11-05 13:38 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 22/29] drm/i915: Give names to more ring registers ville.syrjala
2015-11-05 13:46 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 23/29] drm/i915: Wrap context LRI init in a macro ville.syrjala
2015-11-05 13:49 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 24/29] drm/i915: Turn vgpu pdps into an array ville.syrjala
2015-11-05 6:56 ` Zhiyuan Lv
2015-11-04 21:20 ` [PATCH 25/29] drm/i915: Pull the vgpu uncore funcs apart from the rest of gen6+ ville.syrjala
2015-11-05 7:33 ` Zhiyuan Lv [this message]
2015-11-04 21:20 ` [PATCH 26/29] drm/i915: Add 'offset' to uncore funcs ville.syrjala
2015-11-05 10:16 ` Chris Wilson
2015-11-05 11:38 ` Ville Syrjälä
2015-11-06 19:47 ` [PATCH v2 " ville.syrjala
2015-11-06 20:33 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 27/29] drm/i915: Add save/restore of SWF for ILK+ ville.syrjala
2015-11-06 13:14 ` Chris Wilson
2015-11-06 13:38 ` Ville Syrjälä
2015-11-04 21:20 ` [PATCH 28/29] drm/i915: Add missing ')' to SKL_PS_ECC_STAT define ville.syrjala
2015-11-05 14:33 ` Chris Wilson
2015-11-04 21:20 ` [PATCH v3 29/29] drm/i915: Type safe register read/write ville.syrjala
2015-11-05 9:55 ` Chris Wilson
2015-11-18 13:33 ` [PATCH v4 " ville.syrjala
2015-11-18 13:45 ` [PATCH v2 00/29] drm/i915: Type safe register read/write (v2) and more prep work Ville Syrjälä
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