From: Daniel Vetter <daniel@ffwll.ch>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 12/29] drm/i915: Streamline gpio_mmio_base deduction
Date: Wed, 18 Nov 2015 10:46:09 +0100 [thread overview]
Message-ID: <20151118094609.GF20799@phenom.ffwll.local> (raw)
In-Reply-To: <1446672017-24497-13-git-send-email-ville.syrjala@linux.intel.com>
On Wed, Nov 04, 2015 at 11:20:00PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> If we ignore the BXT situation, we can observe that the only variables
> affecting gpio_mmio_base is IS_VALLEVIEW and HAS_GMCH_DISPLAY. The BXT
> situation we can fit into the same pattern if we change gmbus_pins_bxt[]
> to house the GMCH GPIO register offsets (like we do for all other
> platfotms). So let's do that.
>
> We could even simplify the VLV situation more by including the
> display_mmio_offset in the GPIO register defines, but let's leave it be
> for now.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_i2c.c | 15 +++++++--------
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index bd58da0..9d35589 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -63,9 +63,9 @@ static const struct gmbus_pin gmbus_pins_skl[] = {
> };
>
> static const struct gmbus_pin gmbus_pins_bxt[] = {
> - [GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB },
> - [GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC },
> - [GMBUS_PIN_3_BXT] = { "misc", PCH_GPIOD },
> + [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
> + [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
> };
>
> /* pin is expected to be valid */
> @@ -626,12 +626,11 @@ int intel_setup_gmbus(struct drm_device *dev)
>
> if (HAS_PCH_NOP(dev))
> return 0;
> - else if (HAS_PCH_SPLIT(dev))
> - dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
> - else if (IS_VALLEYVIEW(dev))
> +
> + if (IS_VALLEYVIEW(dev))
> dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
> - else
> - dev_priv->gpio_mmio_base = 0;
> + else if (!HAS_GMCH_DISPLAY(dev))
> + dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
>
> mutex_init(&dev_priv->gmbus_mutex);
> init_waitqueue_head(&dev_priv->gmbus_wait_queue);
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-11-18 9:46 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-04 21:19 [PATCH v2 00/29] drm/i915: Type safe register read/write (v2) and more prep work ville.syrjala
2015-11-04 21:19 ` [PATCH 01/29] pci: Decouple quirks.c from i915_reg.h ville.syrjala
2015-11-05 13:37 ` Chris Wilson
2015-11-24 17:09 ` Bjorn Helgaas
2015-11-04 21:19 ` [PATCH 02/29] drm/i915: Remove the magic AUX_CTL is at DP + foo tricks ville.syrjala
2015-11-06 13:21 ` Chris Wilson
2015-11-04 21:19 ` [PATCH 03/29] drm/i915: Replace the aux ddc name switch statement with a table ville.syrjala
2015-11-05 14:10 ` Chris Wilson
2015-11-05 14:22 ` Ville Syrjälä
2015-11-05 14:33 ` Chris Wilson
2015-11-04 21:19 ` [PATCH v3 04/29] drm/i915: Parametrize AUX registers ville.syrjala
2015-11-06 13:25 ` Chris Wilson
2015-11-06 13:41 ` Ville Syrjälä
2015-11-04 21:19 ` [PATCH v2 05/29] drm/i915: Add dev_priv->psr_mmio_base ville.syrjala
2015-11-05 14:40 ` Chris Wilson
2015-11-05 14:51 ` Ville Syrjälä
2015-11-04 21:19 ` [PATCH v3 06/29] drm/i915: Store aux data reg offsets in intel_dp->aux_ch_data_reg[] ville.syrjala
2015-11-06 13:23 ` Chris Wilson
2015-11-04 21:19 ` [PATCH v2 07/29] drm/i915: Model PSR AUX register selection more like the normal AUX code ville.syrjala
2015-11-05 21:34 ` Chris Wilson
2015-11-04 21:19 ` [PATCH 08/29] drm/i915: s/PCH_DP_/PORT_/ in intel_trans_dp_port_sel() and move it next to its only user ville.syrjala
2015-11-05 13:54 ` Chris Wilson
2015-11-04 21:19 ` [PATCH 09/29] drm/i915: Replace aux_ch_ctl_reg check with port check ville.syrjala
2015-11-05 13:55 ` Chris Wilson
2015-11-04 21:19 ` [PATCH 10/29] drm/i915: s/is_sdvob/enum port/ ville.syrjala
2015-11-05 14:05 ` Chris Wilson
2015-11-06 19:29 ` [PATCH v2 " ville.syrjala
2015-11-04 21:19 ` [PATCH 11/29] drm/i915: Store DVO SRCDIM register offset under intel_dvo_device ville.syrjala
2015-11-05 11:10 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 12/29] drm/i915: Streamline gpio_mmio_base deduction ville.syrjala
2015-11-18 9:46 ` Daniel Vetter [this message]
2015-11-04 21:20 ` [PATCH 13/29] drm/i915: Prefix raw register defines with underscore ville.syrjala
2015-11-05 13:50 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 14/29] drm/i915: Parametrize L3 error registers ville.syrjala
2015-11-05 11:22 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 15/29] drm/i915: Parametrize MOCS registers ville.syrjala
2015-11-05 11:15 ` Chris Wilson
2015-11-05 12:13 ` [PATCH v2 " ville.syrjala
2015-11-05 13:24 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 16/29] drm/i915: s/0x50/RING_PSMI_CTL/ ville.syrjala
2015-11-05 11:16 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 17/29] drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctl ville.syrjala
2015-11-05 10:59 ` Chris Wilson
2015-11-05 11:41 ` Ville Syrjälä
2015-11-05 13:33 ` Chris Wilson
2015-11-06 19:43 ` [PATCH v2 " ville.syrjala
2015-11-18 12:30 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 18/29] drm/i915: Make the cmd parser 64bit regs explicit ville.syrjala
2015-11-05 11:02 ` Chris Wilson
2015-11-06 19:44 ` [PATCH v2 " ville.syrjala
2015-11-04 21:20 ` [PATCH v2 19/29] drm/i915: Add functions to emit register offsets to the ring ville.syrjala
2015-11-05 11:03 ` Chris Wilson
2015-11-05 11:44 ` Ville Syrjälä
2015-11-05 12:01 ` Chris Wilson
2015-11-05 12:05 ` Ville Syrjälä
2015-11-04 21:20 ` [PATCH 20/29] drm/i915: Add wa_ctx_emit_reg() ville.syrjala
2015-11-05 11:04 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 21/29] drm/i915: Wrap ASSIGN_CTX_{PDP, PM4L} in do {} while(0) ville.syrjala
2015-11-05 13:38 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 22/29] drm/i915: Give names to more ring registers ville.syrjala
2015-11-05 13:46 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 23/29] drm/i915: Wrap context LRI init in a macro ville.syrjala
2015-11-05 13:49 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 24/29] drm/i915: Turn vgpu pdps into an array ville.syrjala
2015-11-05 6:56 ` Zhiyuan Lv
2015-11-04 21:20 ` [PATCH 25/29] drm/i915: Pull the vgpu uncore funcs apart from the rest of gen6+ ville.syrjala
2015-11-05 7:33 ` Zhiyuan Lv
2015-11-04 21:20 ` [PATCH 26/29] drm/i915: Add 'offset' to uncore funcs ville.syrjala
2015-11-05 10:16 ` Chris Wilson
2015-11-05 11:38 ` Ville Syrjälä
2015-11-06 19:47 ` [PATCH v2 " ville.syrjala
2015-11-06 20:33 ` Chris Wilson
2015-11-04 21:20 ` [PATCH 27/29] drm/i915: Add save/restore of SWF for ILK+ ville.syrjala
2015-11-06 13:14 ` Chris Wilson
2015-11-06 13:38 ` Ville Syrjälä
2015-11-04 21:20 ` [PATCH 28/29] drm/i915: Add missing ')' to SKL_PS_ECC_STAT define ville.syrjala
2015-11-05 14:33 ` Chris Wilson
2015-11-04 21:20 ` [PATCH v3 29/29] drm/i915: Type safe register read/write ville.syrjala
2015-11-05 9:55 ` Chris Wilson
2015-11-18 13:33 ` [PATCH v4 " ville.syrjala
2015-11-18 13:45 ` [PATCH v2 00/29] drm/i915: Type safe register read/write (v2) and more prep work Ville Syrjälä
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