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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/7] drm/i915: sseu: convert slice count field to mask
Date: Fri, 20 Nov 2015 15:00:27 +0200	[thread overview]
Message-ID: <20151120130027.GH4437@intel.com> (raw)
In-Reply-To: <20151119234045.GC13508@intel.com>

On Thu, Nov 19, 2015 at 03:40:45PM -0800, Ben Widawsky wrote:
> On Wed, Oct 21, 2015 at 06:40:34PM +0300, Imre Deak wrote:
> > In an upcoming patch we'll need the actual mask of slices in addition to
> > their count, so replace the count field with a mask.
> > 
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++++-------
> >  drivers/gpu/drm/i915/i915_dma.c     | 37 +++++++++++++++++++------------------
> >  drivers/gpu/drm/i915/i915_drv.h     |  2 +-
> >  drivers/gpu/drm/i915/intel_lrc.c    |  2 +-
> >  4 files changed, 28 insertions(+), 27 deletions(-)
>>  
<snip>
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index 8a55f8a..4130ff1 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -2202,7 +2202,7 @@ make_rpcs(struct drm_device *dev)
> >  	*/
> >  	if (INTEL_INFO(dev)->sseu.has_slice_pg) {
> >  		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
> > -		rpcs |= INTEL_INFO(dev)->sseu.slice_total <<
> > +		rpcs |= hweight32(INTEL_INFO(dev)->sseu.slice_mask) <<
> 			^ hweight8?
> 
> >  			GEN8_RPCS_S_CNT_SHIFT;
> >  		rpcs |= GEN8_RPCS_ENABLE;
> >  	}
> 
> I'm not positive if hweight32 is actually okay on an 8bit type. I remember Ville
> correcting me once on this, but I can't remember it's correct. Assuming
> hweight32 is fine to use, with or without my recommendations, this is:
> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

I think my hweight8() comment (w.r.t. some patches IIRC) was just an
idea for a micro-optimizition. C promotes small stuff to ints anyway
so I assume hweight32() is just fine functionally.

-- 
Ville Syrjälä
Intel OTC
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  reply	other threads:[~2015-11-20 13:00 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-21 15:40 [PATCH 0/7] drm/i915: read out slice/subslice masks Imre Deak
2015-10-21 15:40 ` [PATCH 1/7] drm/i915: sseu: move sseu_dev_status to i915_drv.h Imre Deak
2015-11-19 23:10   ` Ben Widawsky
2015-11-20  0:29     ` Jeff McGee
2015-10-21 15:40 ` [PATCH 2/7] drm/i915: sseu: use sseu_dev_info in device info Imre Deak
2015-11-19 23:18   ` Ben Widawsky
2015-10-21 15:40 ` [PATCH 3/7] drm/i915: sseu: simplify debugfs status/info printing Imre Deak
2015-11-19 23:24   ` Ben Widawsky
2015-10-21 15:40 ` [PATCH 4/7] drm/i915: sseu: convert slice count field to mask Imre Deak
2015-11-19 23:40   ` Ben Widawsky
2015-11-20 13:00     ` Ville Syrjälä [this message]
2015-10-21 15:40 ` [PATCH 5/7] drm/i915: sseu: convert subslice count fields to subslice mask Imre Deak
2015-11-20  0:07   ` Ben Widawsky
2015-10-21 15:40 ` [PATCH 6/7] drm/i915: sseu: add debug printf for slice/subslice masks Imre Deak
2015-10-21 15:40 ` [PATCH 7/7] drm/i915/bdw: sseu: fix sseu status parsing Imre Deak
2015-11-20  0:08   ` Ben Widawsky
2015-10-27 11:45 ` [PATCH 0/7] drm/i915: read out slice/subslice masks Robert Bragg

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