From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Stone <daniel@fooishbar.org>
Cc: Shobhit Kumar <shobhit.kumar@intel.com>,
intel-gfx <Intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915/skl: CDCLK change during modeset based on VCO in use.
Date: Fri, 20 Nov 2015 21:07:00 +0200 [thread overview]
Message-ID: <20151120190700.GW4437@intel.com> (raw)
In-Reply-To: <CAPj87rNXFtHibBZao=rF5M-96FgviQnqY_wRP=DgiE4KhNWDXQ@mail.gmail.com>
On Fri, Nov 20, 2015 at 07:03:28PM +0000, Daniel Stone wrote:
> On 20 November 2015 at 13:55, Ville Syrjälä
> <ville.syrjala@linux.intel.com> wrote:
> > On Thu, Nov 19, 2015 at 09:20:16AM -0800, clinton.a.taylor@intel.com wrote:
> >> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> >> +{
> >> + struct drm_i915_private *dev_priv = to_i915(state->dev);
> >> + int max_pixclk = ilk_max_pixel_rate(state);
> >> + int cdclk;
> >> + uint32_t linkrate;
> >> +
> >> + linkrate = (I915_READ(DPLL_CTRL1) &
> >> + DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
> >
> > I don't think we should read this from the hardware here. Instead
> > we should stash the proper vco somewhere under dev_priv.
>
> In state rather than dev_priv, surely?
No, it's going to be a fixed value, so doesn't need to be recomputed
ever.
--
Ville Syrjälä
Intel OTC
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prev parent reply other threads:[~2015-11-20 19:07 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-19 17:20 [PATCH] drm/i915/skl: CDCLK change during modeset based on VCO in use clinton.a.taylor
2015-11-20 13:55 ` Ville Syrjälä
2015-11-20 18:10 ` Clint Taylor
2015-11-20 18:47 ` Ville Syrjälä
2015-11-20 19:03 ` Daniel Stone
2015-11-20 19:07 ` Ville Syrjälä [this message]
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