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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915: Use intel_pipe_will_have_type() in ironlake_crtc_compute_clock()
Date: Tue, 1 Dec 2015 16:10:34 +0200	[thread overview]
Message-ID: <20151201141034.GA4437@intel.com> (raw)
In-Reply-To: <20151126084026.GB17050@phenom.ffwll.local>

On Thu, Nov 26, 2015 at 09:40:26AM +0100, Daniel Vetter wrote:
> On Wed, Nov 25, 2015 at 04:35:30PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > ironlake_crtc_compute_clock() gets called during atomic compute phase,
> > so we must check the future pipe type instead of the current type.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Pushed this patch to dinq. Thanks for the review.

> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index a5669a6613e8..26cafeea2845 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -8988,7 +8988,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
> >  	memset(&crtc_state->dpll_hw_state, 0,
> >  	       sizeof(crtc_state->dpll_hw_state));
> >  
> > -	is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
> > +	is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
> >  
> >  	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
> >  	     "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
> > -- 
> > 2.4.10
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

      reply	other threads:[~2015-12-01 14:11 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-25 14:35 [PATCH 1/2] drm/i915: Use intel_pipe_will_have_type() in ironlake_crtc_compute_clock() ville.syrjala
2015-11-25 14:35 ` [PATCH 2/2] drm/i915: Allow PCH DPLL sharing regardles of DPLL_SDVO_HIGH_SPEED ville.syrjala
2015-11-26  8:41   ` Daniel Vetter
2015-11-26 11:42     ` Ville Syrjälä
2015-12-01 14:16       ` Ville Syrjälä
2015-12-03  8:02   ` Daniel Vetter
2015-12-03 10:37     ` Ville Syrjälä
2015-12-03 11:21       ` Ville Syrjälä
2015-11-26  8:40 ` [PATCH 1/2] drm/i915: Use intel_pipe_will_have_type() in ironlake_crtc_compute_clock() Daniel Vetter
2015-12-01 14:10   ` Ville Syrjälä [this message]

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