From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/3] drm/i915/bxt: backlight clock gating workaround
Date: Tue, 1 Dec 2015 19:09:30 +0200 [thread overview]
Message-ID: <20151201170930.GH4437@intel.com> (raw)
In-Reply-To: <1448958232-26520-3-git-send-email-jani.nikula@intel.com>
On Tue, Dec 01, 2015 at 10:23:52AM +0200, Jani Nikula wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> Per bspec, "Backlight PWM may stop in the asserted state, causing
> backlight to stay fully on. WA: Before disabling PWM, set CLKGATE_DIS_0
> 0x46530 bit 13 PWM1 Gating Dis (for PWM1) or bit 14 PWM2 Gating Dis (for
> PWM2). The bits can remain set without harm." (There's no workaround
> name for this.)
>
> This fixes some Broxton backlight issues.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> [Jani: cleanup & commit message]
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Nice and easy due to the "without harm" part.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 487224572022..d87d545e0369 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2973,6 +2973,13 @@ enum skl_disp_power_wells {
> #define OGAMC0 _MMIO(0x30024)
>
> /*
> + * GEN9 clock gating regs
> + */
> +#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
> +#define PWM2_GATING_DIS (1 << 14)
> +#define PWM1_GATING_DIS (1 << 13)
> +
> +/*
> * Display engine regs
> */
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 96f45d7b3e4b..612a8b462294 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -66,6 +66,14 @@ static void bxt_init_clock_gating(struct drm_device *dev)
> */
> I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
> +
> + /*
> + * Wa: Backlight PWM may stop in the asserted state, causing backlight
> + * to stay fully on.
> + */
> + if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
> + I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
> + PWM1_GATING_DIS | PWM2_GATING_DIS);
> }
>
> static void i915_pineview_get_mem_freq(struct drm_device *dev)
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-12-01 17:09 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-01 8:23 [PATCH 1/3] drm/i915/bxt: add support for setting backlight freq from vbt Jani Nikula
2015-12-01 8:23 ` [PATCH 2/3] drm/i915: use default 200 Hz backlight frequency Jani Nikula
2015-12-01 8:23 ` [PATCH 3/3] drm/i915/bxt: backlight clock gating workaround Jani Nikula
2015-12-01 17:09 ` Ville Syrjälä [this message]
2015-12-01 16:58 ` [PATCH 1/3] drm/i915/bxt: add support for setting backlight freq from vbt Imre Deak
2015-12-02 8:28 ` Jani Nikula
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