From: Daniel Vetter <daniel@ffwll.ch>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 02/11] drm/i915: Fix vbt PWM max setup for CTG
Date: Fri, 4 Dec 2015 10:37:25 +0100 [thread overview]
Message-ID: <20151204093725.GH10243@phenom.ffwll.local> (raw)
In-Reply-To: <87zixu4ah5.fsf@intel.com>
On Tue, Dec 01, 2015 at 02:30:46PM +0200, Jani Nikula wrote:
> On Tue, 01 Dec 2015, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Mon, 30 Nov 2015, ville.syrjala@linux.intel.com wrote:
> >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>
> >> CTG uses hrawclk for backlight, so calculate the max based on that
> >> instead of cdclk.
> >
> > If you say so.
> >
> > Acked-by: Jani Nikula <jani.nikula@intel.com>
>
> Okay, found it, promote that to
Should probably contain a Bspec reference then, hunting in that beast
isn't much fun.
-Daniel
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
>
> >
> >> Fixes: aa17cdb4f836 ("drm/i915: initialize backlight max from VBT")
> >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_panel.c | 10 ++++++++--
> >> 1 file changed, 8 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> >> index ea528ca854e8..737e12349e81 100644
> >> --- a/drivers/gpu/drm/i915/intel_panel.c
> >> +++ b/drivers/gpu/drm/i915/intel_panel.c
> >> @@ -1344,13 +1344,19 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
> >>
> >> /*
> >> * Gen4: This value represents the period of the PWM stream in display core
> >> - * clocks multiplied by 128.
> >> + * clocks ([DevCTG] HRAW clocks) multiplied by 128.
> >> + *
> >> */
> >> static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
> >> {
> >> struct drm_device *dev = connector->base.dev;
> >> struct drm_i915_private *dev_priv = dev->dev_private;
> >> - int clock = 1000 * dev_priv->display.get_display_clock_speed(dev);
> >> + int clock;
> >> +
> >> + if (IS_G4X(dev_priv))
> >> + clock = MHz(intel_hrawclk(dev));
> >> + else
> >> + clock = 1000 * dev_priv->display.get_display_clock_speed(dev);
> >>
> >> return clock / (pwm_freq_hz * 128);
> >> }
>
> --
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-12-04 9:37 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-30 14:23 [PATCH 00/11] drm/i915: rawclk/cdclk stuff ville.syrjala
2015-11-30 14:23 ` [PATCH 01/11] drm/i915: Fix VBT backlight Hz to PWM conversion for PNV ville.syrjala
2015-12-01 12:19 ` Jani Nikula
2015-11-30 14:23 ` [PATCH 02/11] drm/i915: Fix vbt PWM max setup for CTG ville.syrjala
2015-12-01 12:21 ` Jani Nikula
2015-12-01 12:28 ` Ville Syrjälä
2015-12-01 12:30 ` Jani Nikula
2015-12-04 9:37 ` Daniel Vetter [this message]
2015-11-30 14:23 ` [PATCH 03/11] drm/i915: Add HAS_PCH_LPT_H() ville.syrjala
2015-12-01 12:23 ` Jani Nikula
2015-11-30 14:23 ` [PATCH 04/11] drm/i915: Kill duplicated PNV .get_display_clock_speed() assignment ville.syrjala
2015-12-01 8:48 ` Daniel Vetter
2015-12-01 12:23 ` Jani Nikula
2015-11-30 14:23 ` [PATCH 05/11] drm/i915: Round the AUX clock divider to closest on all platforms ville.syrjala
2015-12-01 12:34 ` Jani Nikula
2015-11-30 14:23 ` [PATCH 06/11] drm/i915: Use cached cdclk_freq for PWM calculations ville.syrjala
2015-12-01 12:37 ` Jani Nikula
2015-12-02 9:29 ` Ville Syrjälä
2015-11-30 14:23 ` [PATCH 07/11] drm/i915: Store rawclk_freq in dev_priv ville.syrjala
2015-12-01 12:47 ` Jani Nikula
2015-12-01 13:25 ` Ville Syrjälä
2015-12-01 15:43 ` Jani Nikula
2016-01-12 17:47 ` Ville Syrjälä
2015-11-30 14:23 ` [PATCH 08/11] drm/i915: Rename s/i9xx/g4x/ in DP code ville.syrjala
2015-12-01 12:39 ` Jani Nikula
2015-11-30 14:23 ` [PATCH 09/11] drm/i915: Use g4x_get_aux_clock_divider() for VLV/CHV ville.syrjala
2015-12-01 12:49 ` Jani Nikula
2015-11-30 14:23 ` [PATCH 10/11] drm/i915: Read out hrawclk from CCK on vlv/chv ville.syrjala
2015-11-30 14:23 ` [PATCH 11/11] drm/i915: Clean up .get_aux_clock_divider() functions ville.syrjala
2015-12-01 12:56 ` Jani Nikula
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