* [PATCH 1/7] drm/i915: Pass modifier instead of tiling_mode to gen4_compute_page_offset()
2016-01-12 19:08 [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches ville.syrjala
@ 2016-01-12 19:08 ` ville.syrjala
2016-01-12 19:08 ` [PATCH v3 2/7] drm/i915: Factor out intel_tile_width() ville.syrjala
` (7 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: ville.syrjala @ 2016-01-12 19:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In preparation for handling more than X tiling, pass the fb modifier to
gen4_compute_page_offset() instead of the obj->tiling_mode.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_sprite.c | 21 ++++++++++-----------
3 files changed, 18 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index abfb5ba054db..0f8174051d5c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2449,11 +2449,11 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
* is assumed to be a power-of-two. */
unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
int *x, int *y,
- unsigned int tiling_mode,
+ uint64_t fb_modifier,
unsigned int cpp,
unsigned int pitch)
{
- if (tiling_mode != I915_TILING_NONE) {
+ if (fb_modifier != DRM_FORMAT_MOD_NONE) {
unsigned int tile_rows, tiles;
tile_rows = *y / 8;
@@ -2769,8 +2769,8 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
if (INTEL_INFO(dev)->gen >= 4) {
intel_crtc->dspaddr_offset =
- intel_gen4_compute_page_offset(dev_priv,
- &x, &y, obj->tiling_mode,
+ intel_gen4_compute_page_offset(dev_priv, &x, &y,
+ fb->modifier[0],
pixel_size,
fb->pitches[0]);
linear_offset -= intel_crtc->dspaddr_offset;
@@ -2877,8 +2877,8 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
linear_offset = y * fb->pitches[0] + x * pixel_size;
intel_crtc->dspaddr_offset =
- intel_gen4_compute_page_offset(dev_priv,
- &x, &y, obj->tiling_mode,
+ intel_gen4_compute_page_offset(dev_priv, &x, &y,
+ fb->modifier[0],
pixel_size,
fb->pitches[0]);
linear_offset -= intel_crtc->dspaddr_offset;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e27954d2edad..015538287171 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1198,8 +1198,8 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
int *x, int *y,
- unsigned int tiling_mode,
- unsigned int bpp,
+ uint64_t fb_modifier,
+ unsigned int cpp,
unsigned int pitch);
void intel_prepare_reset(struct drm_device *dev);
void intel_finish_reset(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 4d448b990c50..fc5789e65a93 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -422,9 +422,8 @@ vlv_update_plane(struct drm_plane *dplane,
crtc_h--;
linear_offset = y * fb->pitches[0] + x * pixel_size;
- sprsurf_offset = intel_gen4_compute_page_offset(dev_priv,
- &x, &y,
- obj->tiling_mode,
+ sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
+ fb->modifier[0],
pixel_size,
fb->pitches[0]);
linear_offset -= sprsurf_offset;
@@ -557,10 +556,10 @@ ivb_update_plane(struct drm_plane *plane,
sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
linear_offset = y * fb->pitches[0] + x * pixel_size;
- sprsurf_offset =
- intel_gen4_compute_page_offset(dev_priv,
- &x, &y, obj->tiling_mode,
- pixel_size, fb->pitches[0]);
+ sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
+ fb->modifier[0],
+ pixel_size,
+ fb->pitches[0]);
linear_offset -= sprsurf_offset;
if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
@@ -696,10 +695,10 @@ ilk_update_plane(struct drm_plane *plane,
dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
linear_offset = y * fb->pitches[0] + x * pixel_size;
- dvssurf_offset =
- intel_gen4_compute_page_offset(dev_priv,
- &x, &y, obj->tiling_mode,
- pixel_size, fb->pitches[0]);
+ dvssurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
+ fb->modifier[0],
+ pixel_size,
+ fb->pitches[0]);
linear_offset -= dvssurf_offset;
if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
--
2.4.10
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 2/7] drm/i915: Factor out intel_tile_width()
2016-01-12 19:08 [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches ville.syrjala
2016-01-12 19:08 ` [PATCH 1/7] drm/i915: Pass modifier instead of tiling_mode to gen4_compute_page_offset() ville.syrjala
@ 2016-01-12 19:08 ` ville.syrjala
2016-01-12 19:08 ` [PATCH v2 3/7] drm/i915: Redo intel_tile_height() as intel_tile_size() / intel_tile_width() ville.syrjala
` (6 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: ville.syrjala @ 2016-01-12 19:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pull the tile width calculations from intel_fb_stride_alignment() into a
new function intel_tile_width().
Also take the opportunity to pass aroun dev_priv instead of dev to
intel_fb_stride_alignment().
v2: Reorder argumnents to be more consistent with other functions
Change intel_fb_stride_alignment() to accept dev_priv instead of dev
v3: Deal with Y tilling (Daniel)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 85 +++++++++++++++++++++---------------
drivers/gpu/drm/i915/intel_drv.h | 4 +-
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
3 files changed, 54 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0f8174051d5c..3a6387092f63 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2223,6 +2223,43 @@ static bool need_vtd_wa(struct drm_device *dev)
return false;
}
+static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv,
+ uint64_t fb_modifier, unsigned int cpp)
+{
+ switch (fb_modifier) {
+ case DRM_FORMAT_MOD_NONE:
+ return cpp;
+ case I915_FORMAT_MOD_X_TILED:
+ if (IS_GEN2(dev_priv))
+ return 128;
+ else
+ return 512;
+ case I915_FORMAT_MOD_Y_TILED:
+ if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
+ return 128;
+ else
+ return 512;
+ case I915_FORMAT_MOD_Yf_TILED:
+ switch (cpp) {
+ case 1:
+ return 64;
+ case 2:
+ case 4:
+ return 128;
+ case 8:
+ case 16:
+ return 256;
+ default:
+ MISSING_CASE(cpp);
+ return cpp;
+ }
+ break;
+ default:
+ MISSING_CASE(fb_modifier);
+ return cpp;
+ }
+}
+
unsigned int
intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
uint64_t fb_format_modifier, unsigned int plane)
@@ -2914,37 +2951,15 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
POSTING_READ(reg);
}
-u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
- uint32_t pixel_format)
+u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
+ uint64_t fb_modifier, uint32_t pixel_format)
{
- u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
-
- /*
- * The stride is either expressed as a multiple of 64 bytes
- * chunks for linear buffers or in number of tiles for tiled
- * buffers.
- */
- switch (fb_modifier) {
- case DRM_FORMAT_MOD_NONE:
- return 64;
- case I915_FORMAT_MOD_X_TILED:
- if (INTEL_INFO(dev)->gen == 2)
- return 128;
- return 512;
- case I915_FORMAT_MOD_Y_TILED:
- /* No need to check for old gens and Y tiling since this is
- * about the display engine and those will be blocked before
- * we get here.
- */
- return 128;
- case I915_FORMAT_MOD_Yf_TILED:
- if (bits_per_pixel == 8)
- return 64;
- else
- return 128;
- default:
- MISSING_CASE(fb_modifier);
+ if (fb_modifier == DRM_FORMAT_MOD_NONE) {
return 64;
+ } else {
+ int cpp = drm_format_plane_cpp(pixel_format, 0);
+
+ return intel_tile_width(dev_priv, fb_modifier, cpp);
}
}
@@ -3118,7 +3133,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
plane_ctl |= skl_plane_ctl_rotation(rotation);
- stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
+ stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
fb->pixel_format);
surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
@@ -9303,7 +9318,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
fb->width = ((val >> 0) & 0x1fff) + 1;
val = I915_READ(PLANE_STRIDE(pipe, 0));
- stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
+ stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
fb->pixel_format);
fb->pitches[0] = (val & 0x3ff) * stride_mult;
@@ -11389,8 +11404,8 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
stride = DIV_ROUND_UP(fb->height, tile_height);
} else {
stride = fb->pitches[0] /
- intel_fb_stride_alignment(dev, fb->modifier[0],
- fb->pixel_format);
+ intel_fb_stride_alignment(dev_priv, fb->modifier[0],
+ fb->pixel_format);
}
/*
@@ -14774,6 +14789,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
struct drm_mode_fb_cmd2 *mode_cmd,
struct drm_i915_gem_object *obj)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
unsigned int aligned_height;
int ret;
u32 pitch_limit, stride_alignment;
@@ -14815,7 +14831,8 @@ static int intel_framebuffer_init(struct drm_device *dev,
return -EINVAL;
}
- stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
+ stride_alignment = intel_fb_stride_alignment(dev_priv,
+ mode_cmd->modifier[0],
mode_cmd->pixel_format);
if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 015538287171..9a8075b785ac 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1070,8 +1070,8 @@ unsigned int intel_fb_align_height(struct drm_device *dev,
uint64_t fb_format_modifier);
void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
enum fb_op_origin origin);
-u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
- uint32_t pixel_format);
+u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
+ uint64_t fb_modifier, uint32_t pixel_format);
/* intel_audio.c */
void intel_init_audio(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index fc5789e65a93..6e7ac0ea0a41 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -216,7 +216,7 @@ skl_update_plane(struct drm_plane *drm_plane,
rotation = plane_state->base.rotation;
plane_ctl |= skl_plane_ctl_rotation(rotation);
- stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
+ stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
fb->pixel_format);
/* Sizes are 0 based */
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 3/7] drm/i915: Redo intel_tile_height() as intel_tile_size() / intel_tile_width()
2016-01-12 19:08 [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches ville.syrjala
2016-01-12 19:08 ` [PATCH 1/7] drm/i915: Pass modifier instead of tiling_mode to gen4_compute_page_offset() ville.syrjala
2016-01-12 19:08 ` [PATCH v3 2/7] drm/i915: Factor out intel_tile_width() ville.syrjala
@ 2016-01-12 19:08 ` ville.syrjala
2016-01-12 19:08 ` [PATCH v2 4/7] drm/i915: change intel_fill_fb_ggtt_view() to use the real tile size ville.syrjala
` (5 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: ville.syrjala @ 2016-01-12 19:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
I find more usual to think about tile widths than heights, so changing
the intel_tile_height() to calculate the tile height as
tile_size/tile_width is easier than the opposite to the poor brain.
v2: Reorder arguments for consistency
Constify dev_priv arguments
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 89 ++++++++++++------------------------
drivers/gpu/drm/i915/intel_drv.h | 5 +-
drivers/gpu/drm/i915/intel_sprite.c | 5 +-
3 files changed, 34 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3a6387092f63..e2c7ae90b39d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2223,6 +2223,11 @@ static bool need_vtd_wa(struct drm_device *dev)
return false;
}
+static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
+{
+ return IS_GEN2(dev_priv) ? 2048 : 4096;
+}
+
static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv,
uint64_t fb_modifier, unsigned int cpp)
{
@@ -2260,67 +2265,34 @@ static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv,
}
}
-unsigned int
-intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
- uint64_t fb_format_modifier, unsigned int plane)
+unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
+ uint64_t fb_modifier, unsigned int cpp)
{
- unsigned int tile_height;
- uint32_t pixel_bytes;
-
- switch (fb_format_modifier) {
- case DRM_FORMAT_MOD_NONE:
- tile_height = 1;
- break;
- case I915_FORMAT_MOD_X_TILED:
- tile_height = IS_GEN2(dev) ? 16 : 8;
- break;
- case I915_FORMAT_MOD_Y_TILED:
- tile_height = 32;
- break;
- case I915_FORMAT_MOD_Yf_TILED:
- pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
- switch (pixel_bytes) {
- default:
- case 1:
- tile_height = 64;
- break;
- case 2:
- case 4:
- tile_height = 32;
- break;
- case 8:
- tile_height = 16;
- break;
- case 16:
- WARN_ONCE(1,
- "128-bit pixels are not supported for display!");
- tile_height = 16;
- break;
- }
- break;
- default:
- MISSING_CASE(fb_format_modifier);
- tile_height = 1;
- break;
- }
-
- return tile_height;
+ if (fb_modifier == DRM_FORMAT_MOD_NONE)
+ return 1;
+ else
+ return intel_tile_size(dev_priv) /
+ intel_tile_width(dev_priv, fb_modifier, cpp);
}
unsigned int
intel_fb_align_height(struct drm_device *dev, unsigned int height,
- uint32_t pixel_format, uint64_t fb_format_modifier)
+ uint32_t pixel_format, uint64_t fb_modifier)
{
- return ALIGN(height, intel_tile_height(dev, pixel_format,
- fb_format_modifier, 0));
+ unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
+ unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
+
+ return ALIGN(height, tile_height);
}
static void
intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
const struct drm_plane_state *plane_state)
{
+ struct drm_i915_private *dev_priv = to_i915(fb->dev);
struct intel_rotation_info *info = &view->params.rotation_info;
unsigned int tile_height, tile_pitch;
+ unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
*view = i915_ggtt_view_normal;
@@ -2338,22 +2310,19 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
info->uv_offset = fb->offsets[1];
info->fb_modifier = fb->modifier[0];
- tile_height = intel_tile_height(fb->dev, fb->pixel_format,
- fb->modifier[0], 0);
+ tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
tile_pitch = PAGE_SIZE / tile_height;
info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
info->size = info->width_pages * info->height_pages * PAGE_SIZE;
if (info->pixel_format == DRM_FORMAT_NV12) {
- tile_height = intel_tile_height(fb->dev, fb->pixel_format,
- fb->modifier[0], 1);
+ cpp = drm_format_plane_cpp(fb->pixel_format, 1);
+ tile_height = intel_tile_height(dev_priv, fb->modifier[1], cpp);
tile_pitch = PAGE_SIZE / tile_height;
- info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
- info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
- tile_height);
- info->size_uv = info->width_pages_uv * info->height_pages_uv *
- PAGE_SIZE;
+ info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_pitch);
+ info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
+ info->size_uv = info->width_pages_uv * info->height_pages_uv * PAGE_SIZE;
}
}
@@ -3140,9 +3109,10 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
WARN_ON(drm_rect_width(&plane_state->src) == 0);
if (intel_rotation_90_or_270(rotation)) {
+ int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
+
/* stride = Surface height in tiles */
- tile_height = intel_tile_height(dev, fb->pixel_format,
- fb->modifier[0], 0);
+ tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
stride = DIV_ROUND_UP(fb->height, tile_height);
x_offset = stride * tile_height - src_y - src_h;
y_offset = src_x;
@@ -11399,8 +11369,7 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
*/
if (intel_rotation_90_or_270(rotation)) {
/* stride = Surface height in tiles */
- tile_height = intel_tile_height(dev, fb->pixel_format,
- fb->modifier[0], 0);
+ tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
stride = DIV_ROUND_UP(fb->height, tile_height);
} else {
stride = fb->pitches[0] /
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9a8075b785ac..6aaaa8d3b81a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1155,9 +1155,8 @@ int intel_plane_atomic_set_property(struct drm_plane *plane,
int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
struct drm_plane_state *plane_state);
-unsigned int
-intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
- uint64_t fb_format_modifier, unsigned int plane);
+unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
+ uint64_t fb_modifier, unsigned int cpp);
static inline bool
intel_rotation_90_or_270(unsigned int rotation)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 6e7ac0ea0a41..39a7be02c181 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -239,9 +239,10 @@ skl_update_plane(struct drm_plane *drm_plane,
surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
if (intel_rotation_90_or_270(rotation)) {
+ int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
+
/* stride: Surface height in tiles */
- tile_height = intel_tile_height(dev, fb->pixel_format,
- fb->modifier[0], 0);
+ tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
stride = DIV_ROUND_UP(fb->height, tile_height);
plane_size = (src_w << 16) | src_h;
x_offset = stride * tile_height - y - (src_h + 1);
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 4/7] drm/i915: change intel_fill_fb_ggtt_view() to use the real tile size
2016-01-12 19:08 [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches ville.syrjala
` (2 preceding siblings ...)
2016-01-12 19:08 ` [PATCH v2 3/7] drm/i915: Redo intel_tile_height() as intel_tile_size() / intel_tile_width() ville.syrjala
@ 2016-01-12 19:08 ` ville.syrjala
2016-01-12 19:08 ` [PATCH 5/7] drm/i915: Use intel_tile_{size, width, height}() in intel_gen4_compute_page_offset() ville.syrjala
` (4 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: ville.syrjala @ 2016-01-12 19:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use the actual tile size as to compute stuff in
intel_fill_fb_ggtt_view() instead of assuming it's PAGE_SIZE. I suppose
it doesn't matter since we don't use the results on gen2 platforms
where the tile size is 2k.
v2: Update due to CbCr plane
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e2c7ae90b39d..e75f61a56174 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2291,8 +2291,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
struct intel_rotation_info *info = &view->params.rotation_info;
- unsigned int tile_height, tile_pitch;
- unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
+ unsigned int tile_size, tile_width, tile_height, cpp;
*view = i915_ggtt_view_normal;
@@ -2310,19 +2309,24 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
info->uv_offset = fb->offsets[1];
info->fb_modifier = fb->modifier[0];
- tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
- tile_pitch = PAGE_SIZE / tile_height;
- info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
+ tile_size = intel_tile_size(dev_priv);
+
+ cpp = drm_format_plane_cpp(fb->pixel_format, 0);
+ tile_width = intel_tile_width(dev_priv, cpp, fb->modifier[0]);
+ tile_height = tile_size / tile_width;
+
+ info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
- info->size = info->width_pages * info->height_pages * PAGE_SIZE;
+ info->size = info->width_pages * info->height_pages * tile_size;
if (info->pixel_format == DRM_FORMAT_NV12) {
cpp = drm_format_plane_cpp(fb->pixel_format, 1);
- tile_height = intel_tile_height(dev_priv, fb->modifier[1], cpp);
- tile_pitch = PAGE_SIZE / tile_height;
- info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_pitch);
+ tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp);
+ tile_height = tile_size / tile_width;
+
+ info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width);
info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
- info->size_uv = info->width_pages_uv * info->height_pages_uv * PAGE_SIZE;
+ info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
}
}
--
2.4.10
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 5/7] drm/i915: Use intel_tile_{size, width, height}() in intel_gen4_compute_page_offset()
2016-01-12 19:08 [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches ville.syrjala
` (3 preceding siblings ...)
2016-01-12 19:08 ` [PATCH v2 4/7] drm/i915: change intel_fill_fb_ggtt_view() to use the real tile size ville.syrjala
@ 2016-01-12 19:08 ` ville.syrjala
2016-01-12 19:08 ` [PATCH v2 6/7] drm/i915: s/intel_gen4_compute_page_offset/intel_compute_tile_offset/ ville.syrjala
` (3 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: ville.syrjala @ 2016-01-12 19:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make intel_gen4_compute_page_offset() ready for other tiling formats
besied X-tile by getting the tile dimensions through
intel_tile_{size,width,height}().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e75f61a56174..2ce166d71d3a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2464,15 +2464,20 @@ unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
unsigned int pitch)
{
if (fb_modifier != DRM_FORMAT_MOD_NONE) {
+ unsigned int tile_size, tile_width, tile_height;
unsigned int tile_rows, tiles;
- tile_rows = *y / 8;
- *y %= 8;
+ tile_size = intel_tile_size(dev_priv);
+ tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
+ tile_height = tile_size / tile_width;
+
+ tile_rows = *y / tile_height;
+ *y %= tile_height;
- tiles = *x / (512/cpp);
- *x %= 512/cpp;
+ tiles = *x / (tile_width/cpp);
+ *x %= tile_width/cpp;
- return tile_rows * pitch * 8 + tiles * 4096;
+ return tile_rows * pitch * tile_height + tiles * tile_size;
} else {
unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
unsigned int offset;
--
2.4.10
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 6/7] drm/i915: s/intel_gen4_compute_page_offset/intel_compute_tile_offset/
2016-01-12 19:08 [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches ville.syrjala
` (4 preceding siblings ...)
2016-01-12 19:08 ` [PATCH 5/7] drm/i915: Use intel_tile_{size, width, height}() in intel_gen4_compute_page_offset() ville.syrjala
@ 2016-01-12 19:08 ` ville.syrjala
2016-01-12 19:08 ` [PATCH 7/7] drm/i915: Refactor intel_surf_alignment() ville.syrjala
` (2 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: ville.syrjala @ 2016-01-12 19:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Since intel_gen4_compute_page_offset() can now handle tiling formats
all the way down to gen2, rename it to intel_compute_tile_offset().
Not that we actually use it on gen2/3 since there's no DSPSURF etc.
registers which would take a page aligned address.
v2: s/page/tile/ (Daniel)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 26 +++++++++++++-------------
drivers/gpu/drm/i915/intel_drv.h | 10 +++++-----
drivers/gpu/drm/i915/intel_sprite.c | 24 ++++++++++++------------
3 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2ce166d71d3a..2e5b9f34fecd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2457,11 +2457,11 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
* is assumed to be a power-of-two. */
-unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
- int *x, int *y,
- uint64_t fb_modifier,
- unsigned int cpp,
- unsigned int pitch)
+unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
+ int *x, int *y,
+ uint64_t fb_modifier,
+ unsigned int cpp,
+ unsigned int pitch)
{
if (fb_modifier != DRM_FORMAT_MOD_NONE) {
unsigned int tile_size, tile_width, tile_height;
@@ -2784,10 +2784,10 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
if (INTEL_INFO(dev)->gen >= 4) {
intel_crtc->dspaddr_offset =
- intel_gen4_compute_page_offset(dev_priv, &x, &y,
- fb->modifier[0],
- pixel_size,
- fb->pitches[0]);
+ intel_compute_tile_offset(dev_priv, &x, &y,
+ fb->modifier[0],
+ pixel_size,
+ fb->pitches[0]);
linear_offset -= intel_crtc->dspaddr_offset;
} else {
intel_crtc->dspaddr_offset = linear_offset;
@@ -2892,10 +2892,10 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
linear_offset = y * fb->pitches[0] + x * pixel_size;
intel_crtc->dspaddr_offset =
- intel_gen4_compute_page_offset(dev_priv, &x, &y,
- fb->modifier[0],
- pixel_size,
- fb->pitches[0]);
+ intel_compute_tile_offset(dev_priv, &x, &y,
+ fb->modifier[0],
+ pixel_size,
+ fb->pitches[0]);
linear_offset -= intel_crtc->dspaddr_offset;
if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
dspcntr |= DISPPLANE_ROTATE_180;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6aaaa8d3b81a..059b46e22c31 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1195,11 +1195,11 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
-unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
- int *x, int *y,
- uint64_t fb_modifier,
- unsigned int cpp,
- unsigned int pitch);
+unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
+ int *x, int *y,
+ uint64_t fb_modifier,
+ unsigned int cpp,
+ unsigned int pitch);
void intel_prepare_reset(struct drm_device *dev);
void intel_finish_reset(struct drm_device *dev);
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 39a7be02c181..0875c8e0ec0a 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -423,10 +423,10 @@ vlv_update_plane(struct drm_plane *dplane,
crtc_h--;
linear_offset = y * fb->pitches[0] + x * pixel_size;
- sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
- fb->modifier[0],
- pixel_size,
- fb->pitches[0]);
+ sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
+ fb->modifier[0],
+ pixel_size,
+ fb->pitches[0]);
linear_offset -= sprsurf_offset;
if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
@@ -557,10 +557,10 @@ ivb_update_plane(struct drm_plane *plane,
sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
linear_offset = y * fb->pitches[0] + x * pixel_size;
- sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
- fb->modifier[0],
- pixel_size,
- fb->pitches[0]);
+ sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
+ fb->modifier[0],
+ pixel_size,
+ fb->pitches[0]);
linear_offset -= sprsurf_offset;
if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
@@ -696,10 +696,10 @@ ilk_update_plane(struct drm_plane *plane,
dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
linear_offset = y * fb->pitches[0] + x * pixel_size;
- dvssurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
- fb->modifier[0],
- pixel_size,
- fb->pitches[0]);
+ dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
+ fb->modifier[0],
+ pixel_size,
+ fb->pitches[0]);
linear_offset -= dvssurf_offset;
if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
--
2.4.10
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^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 7/7] drm/i915: Refactor intel_surf_alignment()
2016-01-12 19:08 [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches ville.syrjala
` (5 preceding siblings ...)
2016-01-12 19:08 ` [PATCH v2 6/7] drm/i915: s/intel_gen4_compute_page_offset/intel_compute_tile_offset/ ville.syrjala
@ 2016-01-12 19:08 ` ville.syrjala
2016-01-13 8:24 ` ✗ warning: Fi.CI.BAT Patchwork
2016-01-13 17:10 ` [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches Ville Syrjälä
8 siblings, 0 replies; 11+ messages in thread
From: ville.syrjala @ 2016-01-12 19:08 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pull the code to determine the surface alignment for both linear and
tiled surfaces into a separate function intel_surf_alignment(). This
will be used not only for the vma alignment but actually aligning
the plane SURF once SKL+ starts using intel_compute_page_offset()
(since SKL+ needs >4K alignment for tiled surfaces too).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 45 +++++++++++++++++-------------------
1 file changed, 21 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2e5b9f34fecd..0c3a398473ef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2330,7 +2330,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
}
}
-static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
+static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
{
if (INTEL_INFO(dev_priv)->gen >= 9)
return 256 * 1024;
@@ -2343,6 +2343,25 @@ static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
return 0;
}
+static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
+ uint64_t fb_modifier)
+{
+ switch (fb_modifier) {
+ case DRM_FORMAT_MOD_NONE:
+ return intel_linear_alignment(dev_priv);
+ case I915_FORMAT_MOD_X_TILED:
+ if (INTEL_INFO(dev_priv)->gen >= 9)
+ return 256 * 1024;
+ return 0;
+ case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_Yf_TILED:
+ return 1 * 1024 * 1024;
+ default:
+ MISSING_CASE(fb_modifier);
+ return 0;
+ }
+}
+
int
intel_pin_and_fence_fb_obj(struct drm_plane *plane,
struct drm_framebuffer *fb,
@@ -2357,29 +2376,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
- switch (fb->modifier[0]) {
- case DRM_FORMAT_MOD_NONE:
- alignment = intel_linear_alignment(dev_priv);
- break;
- case I915_FORMAT_MOD_X_TILED:
- if (INTEL_INFO(dev)->gen >= 9)
- alignment = 256 * 1024;
- else {
- /* pin() will align the object as required by fence */
- alignment = 0;
- }
- break;
- case I915_FORMAT_MOD_Y_TILED:
- case I915_FORMAT_MOD_Yf_TILED:
- if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
- "Y tiling bo slipped through, driver bug!\n"))
- return -EINVAL;
- alignment = 1 * 1024 * 1024;
- break;
- default:
- MISSING_CASE(fb->modifier[0]);
- return -EINVAL;
- }
+ alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
intel_fill_fb_ggtt_view(&view, fb, plane_state);
--
2.4.10
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^ permalink raw reply related [flat|nested] 11+ messages in thread* ✗ warning: Fi.CI.BAT
2016-01-12 19:08 [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches ville.syrjala
` (6 preceding siblings ...)
2016-01-12 19:08 ` [PATCH 7/7] drm/i915: Refactor intel_surf_alignment() ville.syrjala
@ 2016-01-13 8:24 ` Patchwork
2016-01-13 15:52 ` Ville Syrjälä
2016-01-13 17:10 ` [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches Ville Syrjälä
8 siblings, 1 reply; 11+ messages in thread
From: Patchwork @ 2016-01-13 8:24 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Summary ==
Built on 06d0112e293dfdea7f796d4085f755898850947b drm-intel-nightly: 2016y-01m-12d-21h-16m-40s UTC integration manifest
Test gem_storedw_loop:
Subgroup basic-render:
pass -> DMESG-WARN (bdw-nuci7)
dmesg-warn -> PASS (bdw-ultra)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (skl-i7k-2)
dmesg-warn -> PASS (ilk-hp8440p)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a:
pass -> DMESG-WARN (byt-nuc)
Subgroup read-crc-pipe-a-frame-sequence:
fail -> PASS (snb-x220t)
bdw-nuci7 total:138 pass:128 dwarn:1 dfail:0 fail:0 skip:9
bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
byt-nuc total:141 pass:122 dwarn:4 dfail:0 fail:0 skip:15
hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
hsw-xps12 total:138 pass:133 dwarn:1 dfail:0 fail:0 skip:4
ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1157/
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^ permalink raw reply [flat|nested] 11+ messages in thread* Re: ✗ warning: Fi.CI.BAT
2016-01-13 8:24 ` ✗ warning: Fi.CI.BAT Patchwork
@ 2016-01-13 15:52 ` Ville Syrjälä
0 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2016-01-13 15:52 UTC (permalink / raw)
To: Patchwork; +Cc: intel-gfx
On Wed, Jan 13, 2016 at 08:24:52AM -0000, Patchwork wrote:
> == Summary ==
>
> Built on 06d0112e293dfdea7f796d4085f755898850947b drm-intel-nightly: 2016y-01m-12d-21h-16m-40s UTC integration manifest
>
> Test gem_storedw_loop:
> Subgroup basic-render:
> pass -> DMESG-WARN (bdw-nuci7)
That I take it is this:
https://bugs.freedesktop.org/show_bug.cgi?id=93693
> dmesg-warn -> PASS (bdw-ultra)
> Test kms_flip:
> Subgroup basic-flip-vs-dpms:
> dmesg-warn -> PASS (skl-i7k-2)
> dmesg-warn -> PASS (ilk-hp8440p)
> Test kms_pipe_crc_basic:
> Subgroup read-crc-pipe-a:
> pass -> DMESG-WARN (byt-nuc)
This is the age old
[drm:vlv_check_no_gt_access [i915]] *ERROR* GT register access while GT waking disabled
https://bugs.freedesktop.org/show_bug.cgi?id=93121
So these have nothing to do with these patches it seems.
> Subgroup read-crc-pipe-a-frame-sequence:
> fail -> PASS (snb-x220t)
>
> bdw-nuci7 total:138 pass:128 dwarn:1 dfail:0 fail:0 skip:9
> bdw-ultra total:138 pass:132 dwarn:0 dfail:0 fail:0 skip:6
> bsw-nuc-2 total:141 pass:115 dwarn:2 dfail:0 fail:0 skip:24
> byt-nuc total:141 pass:122 dwarn:4 dfail:0 fail:0 skip:15
> hsw-brixbox total:141 pass:134 dwarn:0 dfail:0 fail:0 skip:7
> hsw-gt2 total:141 pass:137 dwarn:0 dfail:0 fail:0 skip:4
> hsw-xps12 total:138 pass:133 dwarn:1 dfail:0 fail:0 skip:4
> ilk-hp8440p total:141 pass:101 dwarn:3 dfail:0 fail:0 skip:37
> skl-i7k-2 total:141 pass:131 dwarn:2 dfail:0 fail:0 skip:8
> snb-dellxps total:141 pass:122 dwarn:5 dfail:0 fail:0 skip:14
> snb-x220t total:141 pass:122 dwarn:5 dfail:0 fail:1 skip:13
>
> Results at /archive/results/CI_IGT_test/Patchwork_1157/
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches
2016-01-12 19:08 [PATCH 0/7] drm/i915: Reviewed fb offsets[] prep patches ville.syrjala
` (7 preceding siblings ...)
2016-01-13 8:24 ` ✗ warning: Fi.CI.BAT Patchwork
@ 2016-01-13 17:10 ` Ville Syrjälä
8 siblings, 0 replies; 11+ messages in thread
From: Ville Syrjälä @ 2016-01-13 17:10 UTC (permalink / raw)
To: intel-gfx
On Tue, Jan 12, 2016 at 09:08:30PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Here's a repost of some already reviewed patches from my larger fb
> offsets[] series [1] from last year, for the sake of the CI system.
>
> [1] http://lists.freedesktop.org/archives/intel-gfx/2015-October/078050.html
>
> Ville Syrjälä (7):
> drm/i915: Pass modifier instead of tiling_mode to
> gen4_compute_page_offset()
> drm/i915: Factor out intel_tile_width()
> drm/i915: Redo intel_tile_height() as intel_tile_size() /
> intel_tile_width()
> drm/i915: change intel_fill_fb_ggtt_view() to use the real tile size
> drm/i915: Use intel_tile_{size,width,height}() in
> intel_gen4_compute_page_offset()
> drm/i915: s/intel_gen4_compute_page_offset/intel_compute_tile_offset/
> drm/i915: Refactor intel_surf_alignment()
Series pushed to dinq. Thanks for the reviews.
>
> drivers/gpu/drm/i915/intel_display.c | 248 +++++++++++++++++------------------
> drivers/gpu/drm/i915/intel_drv.h | 19 ++-
> drivers/gpu/drm/i915/intel_sprite.c | 32 ++---
> 3 files changed, 145 insertions(+), 154 deletions(-)
>
> --
> 2.4.10
--
Ville Syrjälä
Intel OTC
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