[PATCH] drm/i915: Codify our assumption that the Global GTT is <= 4GiB

[PATCH] drm/i915: Codify our assumption that the Global GTT is <= 4GiB

[Chris Wilson]

Throughout the code base, we use u32 for offsets into the global GTT. If
we ever see any hardware with a larger GGTT, then we run the real risk
of silent corruption. So test for our assumption up front so that we
have a nice reminder should the time come when it fails.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2e460b369e82..0d910638972c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3143,6 +3143,13 @@ int i915_gem_gtt_init(struct drm_device *dev)
 	if (ret)
 		return ret;
 
+	if ((gtt->base.total - 1) >> 32) {
+		DRM_ERROR("We never expected a Global GTT with more than 32bits of address space! Found %lldM!\n",
+			  gtt->base.total >> 20);
+		gtt->base.total = 1ull << 32;
+		gtt->mappable_end = min(gtt->mappable_end, gtt->base.total);
+	}
+
 	/* GMADR is the PCI mmio aperture into the global GTT. */
 	DRM_INFO("Memory usable by graphics device = %lluM\n",
 		 gtt->base.total >> 20);
-- 
2.7.0.rc3

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✗ Fi.CI.BAT: warning for drm/i915: Codify our assumption that the Global GTT is <= 4GiB

[Patchwork]

== Summary ==

Built on 615fbad7f4cea73b1a8eccdcc942c8ca1a708dab drm-intel-nightly: 2016y-01m-15d-09h-46m-32s UTC integration manifest

Test gem_storedw_loop:
        Subgroup basic-render:
                dmesg-warn -> PASS       (bdw-nuci7)
                pass       -> DMESG-WARN (bdw-ultra)
Test kms_flip:
        Subgroup basic-flip-vs-modeset:
                dmesg-warn -> PASS       (skl-i5k-2)

bdw-nuci7        total:138  pass:129  dwarn:0   dfail:0   fail:0   skip:9  
bdw-ultra        total:138  pass:131  dwarn:1   dfail:0   fail:0   skip:6  
bsw-nuc-2        total:141  pass:115  dwarn:2   dfail:0   fail:0   skip:24 
byt-nuc          total:141  pass:123  dwarn:3   dfail:0   fail:0   skip:15 
hsw-brixbox      total:141  pass:134  dwarn:0   dfail:0   fail:0   skip:7  
hsw-gt2          total:141  pass:137  dwarn:0   dfail:0   fail:0   skip:4  
ilk-hp8440p      total:141  pass:101  dwarn:3   dfail:0   fail:0   skip:37 
ivb-t430s        total:135  pass:122  dwarn:3   dfail:4   fail:0   skip:6  
skl-i5k-2        total:141  pass:132  dwarn:1   dfail:0   fail:0   skip:8  
skl-i7k-2        total:141  pass:132  dwarn:1   dfail:0   fail:0   skip:8  
snb-dellxps      total:141  pass:122  dwarn:5   dfail:0   fail:0   skip:14 
snb-x220t        total:141  pass:122  dwarn:5   dfail:0   fail:1   skip:13 

Results at /archive/results/CI_IGT_test/Patchwork_1194/

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Re: [PATCH] drm/i915: Codify our assumption that the Global GTT is <= 4GiB

[Dave Gordon]

On 15/01/16 10:20, Chris Wilson wrote:
> Throughout the code base, we use u32 for offsets into the global GTT. If
> we ever see any hardware with a larger GGTT, then we run the real risk
> of silent corruption. So test for our assumption up front so that we
> have a nice reminder should the time come when it fails.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
> ---
>   drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++++++
>   1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 2e460b369e82..0d910638972c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3143,6 +3143,13 @@ int i915_gem_gtt_init(struct drm_device *dev)
>   	if (ret)
>   		return ret;
>
> +	if ((gtt->base.total - 1) >> 32) {
> +		DRM_ERROR("We never expected a Global GTT with more than 32bits of address space! Found %lldM!\n",
> +			  gtt->base.total >> 20);
> +		gtt->base.total = 1ull << 32;
> +		gtt->mappable_end = min(gtt->mappable_end, gtt->base.total);

Assuming Mika's comment on 'struct i915_address_space' is correct:
...
	u64 start;              /* Start offset always 0 for dri2 */
...
otherwise this calculation would need to be adjusted.

> +
>   	/* GMADR is the PCI mmio aperture into the global GTT. */
>   	DRM_INFO("Memory usable by graphics device = %lluM\n",
>   		 gtt->base.total >> 20);

LGTM.

Reviewed-by: Dave Gordon <david.s.gordon@intel.com>

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Re: [PATCH] drm/i915: Codify our assumption that the Global GTT is <= 4GiB

[Chris Wilson]

On Fri, Jan 15, 2016 at 11:25:38AM +0000, Dave Gordon wrote:
> On 15/01/16 10:20, Chris Wilson wrote:
> >Throughout the code base, we use u32 for offsets into the global GTT. If
> >we ever see any hardware with a larger GGTT, then we run the real risk
> >of silent corruption. So test for our assumption up front so that we
> >have a nice reminder should the time come when it fails.
> >
> >Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >Cc: Daniel Vetter <daniel@ffwll.ch>
> >---
> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >index 2e460b369e82..0d910638972c 100644
> >--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> >+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >@@ -3143,6 +3143,13 @@ int i915_gem_gtt_init(struct drm_device *dev)
> >  	if (ret)
> >  		return ret;
> >
> >+	if ((gtt->base.total - 1) >> 32) {
> >+		DRM_ERROR("We never expected a Global GTT with more than 32bits of address space! Found %lldM!\n",
> >+			  gtt->base.total >> 20);
> >+		gtt->base.total = 1ull << 32;
> >+		gtt->mappable_end = min(gtt->mappable_end, gtt->base.total);
> 
> Assuming Mika's comment on 'struct i915_address_space' is correct:
> ...
> 	u64 start;              /* Start offset always 0 for dri2 */
> ...
> otherwise this calculation would need to be adjusted.

The address_space start was for the obsolete UMS call where the xserver
would tell the kernel the range of the (then only global) GTT to use for
itself.

The vgpu plugin comes later? Though if I remember correctly, it reserves
ranges of the GGTT for itself rather than alter the drm_mm.

So I don't think it has been revitalised since. Removing the start value
from the struct i915_address_space confirms it is obsolete.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [PATCH] drm/i915: Codify our assumption that the Global GTT is <= 4GiB

[Chris Wilson]

On Fri, Jan 15, 2016 at 10:20:11AM +0000, Chris Wilson wrote:
> Throughout the code base, we use u32 for offsets into the global GTT. If
> we ever see any hardware with a larger GGTT, then we run the real risk
> of silent corruption. So test for our assumption up front so that we
> have a nice reminder should the time come when it fails.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>

From the earlier cut-n-paste,

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

(so I hope it still holds with the minor correction applied :)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [PATCH] drm/i915: Codify our assumption that the Global GTT is <= 4GiB

[Ville Syrjälä]

On Fri, Jan 15, 2016 at 11:28:16AM +0000, Chris Wilson wrote:
> On Fri, Jan 15, 2016 at 10:20:11AM +0000, Chris Wilson wrote:
> > Throughout the code base, we use u32 for offsets into the global GTT. If
> > we ever see any hardware with a larger GGTT, then we run the real risk
> > of silent corruption. So test for our assumption up front so that we
> > have a nice reminder should the time come when it fails.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Daniel Vetter <daniel@ffwll.ch>
> 
> >From the earlier cut-n-paste,
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> (so I hope it still holds with the minor correction applied :)

Yes. Please excuse the sucky review I gave to the original.

-- 
Ville Syrjälä
Intel OTC
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