* [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2)
@ 2016-01-20 19:05 ville.syrjala
2016-01-20 19:05 ` [PATCH 01/18] drm/i915: Rename the rotated gtt view member to 'rotated' ville.syrjala
` (21 more replies)
0 siblings, 22 replies; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
This is the new version of [1]. I already sent a bunch of the earlir
patches as separate prep series [2] and [3]. [2] was already pushed
fully, but most of the patches from [3] didn't get reviewed yet, so
I've included them in this series so that the CI machinery might
actually apply the patches and test the thing. So you can consider
the last prep series superceced by this one.
What's changed from the original:
* The big patch got split up a bit
* I tried to avoid some of the bytes vs. pixels confusion
* Reordered the patches a bit
* Tried to account various other review comments
The series (+ a bit of extra) available here:
git://github.com/vsyrjala/linux.git fb_offsets_7
[1] http://lists.freedesktop.org/archives/intel-gfx/2015-October/078050.html
[2] http://lists.freedesktop.org/archives/intel-gfx/2016-January/085064.html
[3] http://lists.freedesktop.org/archives/intel-gfx/2016-January/085327.html
Ville Syrjälä (18):
drm/i915: Rename the rotated gtt view member to 'rotated'
drm/i915: Pass stride to rotate_pages()
drm/i915: Pass rotation_info to intel_rotate_fb_obj_pages()
drm/i915: Make display gtt offsets u32
drm/i915: Standardize on 'cpp' for bytes per pixel
drm: Add drm_format_plane_width() and drm_format_plane_height()
drm/i915: Fix intel_tile_width() parameters
drm/i915: Pass 90/270 vs. 0/180 rotation info for
intel_gen4_compute_page_offset()
drm/i915: Support for extra alignment for tiled surfaces
drm/i915: Don't pass plane+plane_state to intel_pin_and_fence_fb_obj()
drm/i915: Pass drm_frambuffer to intel_compute_page_offset()
drm/i915: Reorganize intel_rotation_info
drm/i915: Move the NULL sg handling out from rotate_pages()
drm/i915: Embed rotation_info under intel_framebuffer
drm/i915: Rewrite fb rotation GTT handling
drm/i915: Don't pass pitch to intel_compute_page_offset()
drm/i915: Pass around plane_state instead of fb+rotation
drm/i915: Make sure fb offset is (macro)pixel aligned
drivers/gpu/drm/i915/i915_gem_gtt.c | 70 ++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 16 +-
drivers/gpu/drm/i915/intel_display.c | 587 ++++++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_drv.h | 35 ++-
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 128 ++++----
drivers/gpu/drm/i915/intel_sprite.c | 136 ++++----
include/drm/drm_crtc.h | 30 ++
8 files changed, 613 insertions(+), 391 deletions(-)
--
2.4.10
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH 01/18] drm/i915: Rename the rotated gtt view member to 'rotated'
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-25 16:50 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH 02/18] drm/i915: Pass stride to rotate_pages() ville.syrjala
` (20 subsequent siblings)
21 siblings, 1 reply; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Also rename 'rotation_info' to 'rotated' to match the view type exactly,
this should avoid confusion which union members is valid for each view
type.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7377b6725c33..a3ea6b15c762 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3366,7 +3366,7 @@ static struct sg_table *
intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
struct drm_i915_gem_object *obj)
{
- struct intel_rotation_info *rot_info = &ggtt_view->params.rotation_info;
+ struct intel_rotation_info *rot_info = &ggtt_view->params.rotated;
unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
unsigned int size_pages_uv;
struct sg_page_iter sg_iter;
@@ -3598,7 +3598,7 @@ i915_ggtt_view_size(struct drm_i915_gem_object *obj,
if (view->type == I915_GGTT_VIEW_NORMAL) {
return obj->base.size;
} else if (view->type == I915_GGTT_VIEW_ROTATED) {
- return view->params.rotation_info.size;
+ return view->params.rotated.size;
} else if (view->type == I915_GGTT_VIEW_PARTIAL) {
return view->params.partial.size << PAGE_SHIFT;
} else {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index e5737963ab79..f520c90e5377 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -155,7 +155,7 @@ struct i915_ggtt_view {
u64 offset;
unsigned int size;
} partial;
- struct intel_rotation_info rotation_info;
+ struct intel_rotation_info rotated;
} params;
struct sg_table *pages;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 06ab6df8ad48..5f8e3f7abca1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2284,7 +2284,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
const struct drm_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
- struct intel_rotation_info *info = &view->params.rotation_info;
+ struct intel_rotation_info *info = &view->params.rotated;
unsigned int tile_size, tile_width, tile_height, cpp;
*view = i915_ggtt_view_normal;
@@ -2951,7 +2951,7 @@ u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
offset = vma->node.start;
if (plane == 1) {
- offset += vma->ggtt_view.params.rotation_info.uv_start_page *
+ offset += vma->ggtt_view.params.rotated.uv_start_page *
PAGE_SIZE;
}
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH 02/18] drm/i915: Pass stride to rotate_pages()
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
2016-01-20 19:05 ` [PATCH 01/18] drm/i915: Rename the rotated gtt view member to 'rotated' ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-25 16:52 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH 03/18] drm/i915: Pass rotation_info to intel_rotate_fb_obj_pages() ville.syrjala
` (19 subsequent siblings)
21 siblings, 1 reply; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pass stride in addition to width and height to rotate_pages(). For now
width and stride are the same, but once framebuffer offsets enter the
scene that may no longer be the case.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a3ea6b15c762..d547eecac242 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3333,6 +3333,7 @@ i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
static struct scatterlist *
rotate_pages(const dma_addr_t *in, unsigned int offset,
unsigned int width, unsigned int height,
+ unsigned int stride,
struct sg_table *st, struct scatterlist *sg)
{
unsigned int column, row;
@@ -3344,7 +3345,7 @@ rotate_pages(const dma_addr_t *in, unsigned int offset,
}
for (column = 0; column < width; column++) {
- src_idx = width * (height - 1) + column;
+ src_idx = stride * (height - 1) + column;
for (row = 0; row < height; row++) {
st->nents++;
/* We don't need the pages, but need to initialize
@@ -3355,7 +3356,7 @@ rotate_pages(const dma_addr_t *in, unsigned int offset,
sg_dma_address(sg) = in[offset + src_idx];
sg_dma_len(sg) = PAGE_SIZE;
sg = sg_next(sg);
- src_idx -= width;
+ src_idx -= stride;
}
}
@@ -3408,6 +3409,7 @@ intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
/* Rotate the pages. */
sg = rotate_pages(page_addr_list, 0,
rot_info->width_pages, rot_info->height_pages,
+ rot_info->width_pages,
st, NULL);
/* Append the UV plane if NV12. */
@@ -3423,6 +3425,7 @@ intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
rotate_pages(page_addr_list, uv_start_page,
rot_info->width_pages_uv,
rot_info->height_pages_uv,
+ rot_info->width_pages_uv,
st, sg);
}
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH 03/18] drm/i915: Pass rotation_info to intel_rotate_fb_obj_pages()
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
2016-01-20 19:05 ` [PATCH 01/18] drm/i915: Rename the rotated gtt view member to 'rotated' ville.syrjala
2016-01-20 19:05 ` [PATCH 02/18] drm/i915: Pass stride to rotate_pages() ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-25 16:53 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH 04/18] drm/i915: Make display gtt offsets u32 ville.syrjala
` (18 subsequent siblings)
21 siblings, 1 reply; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_rotate_fb_obj_pages() doens't need the entire gtt view, just the
rotation info suffices.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d547eecac242..b3d8e2b0948c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3364,10 +3364,9 @@ rotate_pages(const dma_addr_t *in, unsigned int offset,
}
static struct sg_table *
-intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
+intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
struct drm_i915_gem_object *obj)
{
- struct intel_rotation_info *rot_info = &ggtt_view->params.rotated;
unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
unsigned int size_pages_uv;
struct sg_page_iter sg_iter;
@@ -3507,7 +3506,7 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma)
vma->ggtt_view.pages = vma->obj->pages;
else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
vma->ggtt_view.pages =
- intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
+ intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj);
else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
vma->ggtt_view.pages =
intel_partial_pages(&vma->ggtt_view, vma->obj);
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH 04/18] drm/i915: Make display gtt offsets u32
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (2 preceding siblings ...)
2016-01-20 19:05 ` [PATCH 03/18] drm/i915: Pass rotation_info to intel_rotate_fb_obj_pages() ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-25 17:00 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH 05/18] drm/i915: Standardize on 'cpp' for bytes per pixel ville.syrjala
` (17 subsequent siblings)
21 siblings, 1 reply; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Using 'unsigned long' for ggtt offsets doesn't make much sense. Use
'u32' instead since we've not yet seen a >4GiB ggtt.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++------------
drivers/gpu/drm/i915/intel_drv.h | 12 ++++++------
drivers/gpu/drm/i915/intel_sprite.c | 6 +++---
3 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5f8e3f7abca1..0f5df7a66cc4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2448,11 +2448,11 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
* is assumed to be a power-of-two. */
-unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
- int *x, int *y,
- uint64_t fb_modifier,
- unsigned int cpp,
- unsigned int pitch)
+u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
+ int *x, int *y,
+ uint64_t fb_modifier,
+ unsigned int cpp,
+ unsigned int pitch)
{
if (fb_modifier != DRM_FORMAT_MOD_NONE) {
unsigned int tile_size, tile_width, tile_height;
@@ -2706,14 +2706,12 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
struct drm_framebuffer *fb = plane_state->base.fb;
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int plane = intel_crtc->plane;
- unsigned long linear_offset;
- int x = plane_state->src.x1 >> 16;
- int y = plane_state->src.y1 >> 16;
+ u32 linear_offset;
u32 dspcntr;
i915_reg_t reg = DSPCNTR(plane);
- int pixel_size;
-
- pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+ int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+ int x = plane_state->src.x1 >> 16;
+ int y = plane_state->src.y1 >> 16;
dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -2839,7 +2837,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
struct drm_framebuffer *fb = plane_state->base.fb;
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int plane = intel_crtc->plane;
- unsigned long linear_offset;
+ u32 linear_offset;
u32 dspcntr;
i915_reg_t reg = DSPCNTR(plane);
int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bc970125ec76..f620023ed134 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -575,7 +575,7 @@ struct intel_crtc {
/* Display surface base address adjustement for pageflips. Note that on
* gen4+ this only adjusts up to a tile, offsets within a tile are
* handled in the hw itself (with the TILEOFF register). */
- unsigned long dspaddr_offset;
+ u32 dspaddr_offset;
int adjusted_x;
int adjusted_y;
@@ -1172,11 +1172,11 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
-unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
- int *x, int *y,
- uint64_t fb_modifier,
- unsigned int cpp,
- unsigned int pitch);
+u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
+ int *x, int *y,
+ uint64_t fb_modifier,
+ unsigned int cpp,
+ unsigned int pitch);
void intel_prepare_reset(struct drm_device *dev);
void intel_finish_reset(struct drm_device *dev);
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0875c8e0ec0a..f1ee7db0811a 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -350,7 +350,7 @@ vlv_update_plane(struct drm_plane *dplane,
int pipe = intel_plane->pipe;
int plane = intel_plane->plane;
u32 sprctl;
- unsigned long sprsurf_offset, linear_offset;
+ u32 sprsurf_offset, linear_offset;
int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->dst.x1;
@@ -493,7 +493,7 @@ ivb_update_plane(struct drm_plane *plane,
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
enum pipe pipe = intel_plane->pipe;
u32 sprctl, sprscale = 0;
- unsigned long sprsurf_offset, linear_offset;
+ u32 sprsurf_offset, linear_offset;
int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->dst.x1;
@@ -635,8 +635,8 @@ ilk_update_plane(struct drm_plane *plane,
struct drm_framebuffer *fb = plane_state->base.fb;
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int pipe = intel_plane->pipe;
- unsigned long dvssurf_offset, linear_offset;
u32 dvscntr, dvsscale;
+ u32 dvssurf_offset, linear_offset;
int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->dst.x1;
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH 05/18] drm/i915: Standardize on 'cpp' for bytes per pixel
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (3 preceding siblings ...)
2016-01-20 19:05 ` [PATCH 04/18] drm/i915: Make display gtt offsets u32 ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-25 17:05 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH v2 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height() ville.syrjala
` (16 subsequent siblings)
21 siblings, 1 reply; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We more or less randomly call the "bytes per pixel" value
'cpp', 'bytes_per_pixel', 'pixel_size', or even 'bpp'. Let's just pick
one and stick to it. I've chosen 'cpp'.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 22 +++---
drivers/gpu/drm/i915/intel_pm.c | 128 +++++++++++++++++------------------
drivers/gpu/drm/i915/intel_sprite.c | 34 ++++------
3 files changed, 87 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0f5df7a66cc4..f94ddad704b2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2709,7 +2709,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
u32 linear_offset;
u32 dspcntr;
i915_reg_t reg = DSPCNTR(plane);
- int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+ int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
int x = plane_state->src.x1 >> 16;
int y = plane_state->src.y1 >> 16;
@@ -2769,13 +2769,12 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
if (IS_G4X(dev))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
- linear_offset = y * fb->pitches[0] + x * pixel_size;
+ linear_offset = y * fb->pitches[0] + x * cpp;
if (INTEL_INFO(dev)->gen >= 4) {
intel_crtc->dspaddr_offset =
intel_compute_tile_offset(dev_priv, &x, &y,
- fb->modifier[0],
- pixel_size,
+ fb->modifier[0], cpp,
fb->pitches[0]);
linear_offset -= intel_crtc->dspaddr_offset;
} else {
@@ -2792,7 +2791,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
data and adding to linear_offset*/
linear_offset +=
(crtc_state->pipe_src_h - 1) * fb->pitches[0] +
- (crtc_state->pipe_src_w - 1) * pixel_size;
+ (crtc_state->pipe_src_w - 1) * cpp;
}
intel_crtc->adjusted_x = x;
@@ -2840,7 +2839,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
u32 linear_offset;
u32 dspcntr;
i915_reg_t reg = DSPCNTR(plane);
- int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+ int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
int x = plane_state->src.x1 >> 16;
int y = plane_state->src.y1 >> 16;
@@ -2879,11 +2878,10 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
- linear_offset = y * fb->pitches[0] + x * pixel_size;
+ linear_offset = y * fb->pitches[0] + x * cpp;
intel_crtc->dspaddr_offset =
intel_compute_tile_offset(dev_priv, &x, &y,
- fb->modifier[0],
- pixel_size,
+ fb->modifier[0], cpp,
fb->pitches[0]);
linear_offset -= intel_crtc->dspaddr_offset;
if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
@@ -2897,7 +2895,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
data and adding to linear_offset*/
linear_offset +=
(crtc_state->pipe_src_h - 1) * fb->pitches[0] +
- (crtc_state->pipe_src_w - 1) * pixel_size;
+ (crtc_state->pipe_src_w - 1) * cpp;
}
}
@@ -14680,10 +14678,12 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
u32 gen = INTEL_INFO(dev)->gen;
if (gen >= 9) {
+ int cpp = drm_format_plane_cpp(pixel_format, 0);
+
/* "The stride in bytes must not exceed the of the size of 8K
* pixels and 32K bytes."
*/
- return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
+ return min(8192 * cpp, 32768);
} else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
return 32*1024;
} else if (gen >= 4) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 20bf854eae8c..31bc4ea395ac 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -548,7 +548,7 @@ static const struct intel_watermark_params i845_wm_info = {
* intel_calculate_wm - calculate watermark level
* @clock_in_khz: pixel clock
* @wm: chip FIFO params
- * @pixel_size: display pixel size
+ * @cpp: bytes per pixel
* @latency_ns: memory latency for the platform
*
* Calculate the watermark level (the level at which the display plane will
@@ -564,8 +564,7 @@ static const struct intel_watermark_params i845_wm_info = {
*/
static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
const struct intel_watermark_params *wm,
- int fifo_size,
- int pixel_size,
+ int fifo_size, int cpp,
unsigned long latency_ns)
{
long entries_required, wm_size;
@@ -576,7 +575,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
* clocks go from a few thousand to several hundred thousand.
* latency is usually a few thousand
*/
- entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
+ entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
1000;
entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
@@ -640,13 +639,13 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
crtc = single_enabled_crtc(dev);
if (crtc) {
const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
- int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
+ int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
int clock = adjusted_mode->crtc_clock;
/* Display SR */
wm = intel_calculate_wm(clock, &pineview_display_wm,
pineview_display_wm.fifo_size,
- pixel_size, latency->display_sr);
+ cpp, latency->display_sr);
reg = I915_READ(DSPFW1);
reg &= ~DSPFW_SR_MASK;
reg |= FW_WM(wm, SR);
@@ -656,7 +655,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
/* cursor SR */
wm = intel_calculate_wm(clock, &pineview_cursor_wm,
pineview_display_wm.fifo_size,
- pixel_size, latency->cursor_sr);
+ cpp, latency->cursor_sr);
reg = I915_READ(DSPFW3);
reg &= ~DSPFW_CURSOR_SR_MASK;
reg |= FW_WM(wm, CURSOR_SR);
@@ -665,7 +664,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
/* Display HPLL off SR */
wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
pineview_display_hplloff_wm.fifo_size,
- pixel_size, latency->display_hpll_disable);
+ cpp, latency->display_hpll_disable);
reg = I915_READ(DSPFW3);
reg &= ~DSPFW_HPLL_SR_MASK;
reg |= FW_WM(wm, HPLL_SR);
@@ -674,7 +673,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
/* cursor HPLL off SR */
wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
pineview_display_hplloff_wm.fifo_size,
- pixel_size, latency->cursor_hpll_disable);
+ cpp, latency->cursor_hpll_disable);
reg = I915_READ(DSPFW3);
reg &= ~DSPFW_HPLL_CURSOR_MASK;
reg |= FW_WM(wm, HPLL_CURSOR);
@@ -698,7 +697,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
{
struct drm_crtc *crtc;
const struct drm_display_mode *adjusted_mode;
- int htotal, hdisplay, clock, pixel_size;
+ int htotal, hdisplay, clock, cpp;
int line_time_us, line_count;
int entries, tlb_miss;
@@ -713,10 +712,10 @@ static bool g4x_compute_wm0(struct drm_device *dev,
clock = adjusted_mode->crtc_clock;
htotal = adjusted_mode->crtc_htotal;
hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
- pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
+ cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
/* Use the small buffer method to calculate plane watermark */
- entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
+ entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
if (tlb_miss > 0)
entries += tlb_miss;
@@ -728,7 +727,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
/* Use the large buffer method to calculate cursor watermark */
line_time_us = max(htotal * 1000 / clock, 1);
line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
- entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
+ entries = line_count * crtc->cursor->state->crtc_w * cpp;
tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
if (tlb_miss > 0)
entries += tlb_miss;
@@ -784,7 +783,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
{
struct drm_crtc *crtc;
const struct drm_display_mode *adjusted_mode;
- int hdisplay, htotal, pixel_size, clock;
+ int hdisplay, htotal, cpp, clock;
unsigned long line_time_us;
int line_count, line_size;
int small, large;
@@ -800,21 +799,21 @@ static bool g4x_compute_srwm(struct drm_device *dev,
clock = adjusted_mode->crtc_clock;
htotal = adjusted_mode->crtc_htotal;
hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
- pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
+ cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
line_time_us = max(htotal * 1000 / clock, 1);
line_count = (latency_ns / line_time_us + 1000) / 1000;
- line_size = hdisplay * pixel_size;
+ line_size = hdisplay * cpp;
/* Use the minimum of the small and large buffer method for primary */
- small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
+ small = ((clock * cpp / 1000) * latency_ns) / 1000;
large = line_count * line_size;
entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
*display_wm = entries + display->guard_size;
/* calculate the self-refresh watermark for display cursor */
- entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
+ entries = line_count * cpp * crtc->cursor->state->crtc_w;
entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
*cursor_wm = entries + cursor->guard_size;
@@ -906,13 +905,13 @@ enum vlv_wm_level {
static unsigned int vlv_wm_method2(unsigned int pixel_rate,
unsigned int pipe_htotal,
unsigned int horiz_pixels,
- unsigned int bytes_per_pixel,
+ unsigned int cpp,
unsigned int latency)
{
unsigned int ret;
ret = (latency * pixel_rate) / (pipe_htotal * 10000);
- ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
+ ret = (ret + 1) * horiz_pixels * cpp;
ret = DIV_ROUND_UP(ret, 64);
return ret;
@@ -941,7 +940,7 @@ static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
int level)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- int clock, htotal, pixel_size, width, wm;
+ int clock, htotal, cpp, width, wm;
if (dev_priv->wm.pri_latency[level] == 0)
return USHRT_MAX;
@@ -949,7 +948,7 @@ static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
if (!state->visible)
return 0;
- pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
+ cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
clock = crtc->config->base.adjusted_mode.crtc_clock;
htotal = crtc->config->base.adjusted_mode.crtc_htotal;
width = crtc->config->pipe_src_w;
@@ -965,7 +964,7 @@ static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
*/
wm = 63;
} else {
- wm = vlv_wm_method2(clock, htotal, width, pixel_size,
+ wm = vlv_wm_method2(clock, htotal, width, cpp,
dev_priv->wm.pri_latency[level] * 10);
}
@@ -1439,7 +1438,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
int clock = adjusted_mode->crtc_clock;
int htotal = adjusted_mode->crtc_htotal;
int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
- int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
+ int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
unsigned long line_time_us;
int entries;
@@ -1447,7 +1446,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
/* Use ns/us then divide to preserve precision */
entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
- pixel_size * hdisplay;
+ cpp * hdisplay;
entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
srwm = I965_FIFO_SIZE - entries;
if (srwm < 0)
@@ -1457,7 +1456,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
entries, srwm);
entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
- pixel_size * crtc->cursor->state->crtc_w;
+ cpp * crtc->cursor->state->crtc_w;
entries = DIV_ROUND_UP(entries,
i965_cursor_wm_info.cacheline_size);
cursor_sr = i965_cursor_wm_info.fifo_size -
@@ -1518,7 +1517,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
crtc = intel_get_crtc_for_plane(dev, 0);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode;
- int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
+ int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
if (IS_GEN2(dev))
cpp = 4;
@@ -1540,7 +1539,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
crtc = intel_get_crtc_for_plane(dev, 1);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode;
- int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
+ int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
if (IS_GEN2(dev))
cpp = 4;
@@ -1586,7 +1585,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
int clock = adjusted_mode->crtc_clock;
int htotal = adjusted_mode->crtc_htotal;
int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
- int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
+ int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
unsigned long line_time_us;
int entries;
@@ -1594,7 +1593,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
/* Use ns/us then divide to preserve precision */
entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
- pixel_size * hdisplay;
+ cpp * hdisplay;
entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
srwm = wm_info->fifo_size - entries;
@@ -1685,15 +1684,14 @@ uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
}
/* latency must be in 0.1us units. */
-static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
- uint32_t latency)
+static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
{
uint64_t ret;
if (WARN(latency == 0, "Latency value missing\n"))
return UINT_MAX;
- ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
+ ret = (uint64_t) pixel_rate * cpp * latency;
ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
return ret;
@@ -1701,7 +1699,7 @@ static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
/* latency must be in 0.1us units. */
static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
- uint32_t horiz_pixels, uint8_t bytes_per_pixel,
+ uint32_t horiz_pixels, uint8_t cpp,
uint32_t latency)
{
uint32_t ret;
@@ -1712,13 +1710,13 @@ static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
return UINT_MAX;
ret = (latency * pixel_rate) / (pipe_htotal * 10000);
- ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
+ ret = (ret + 1) * horiz_pixels * cpp;
ret = DIV_ROUND_UP(ret, 64) + 2;
return ret;
}
static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
- uint8_t bytes_per_pixel)
+ uint8_t cpp)
{
/*
* Neither of these should be possible since this function shouldn't be
@@ -1726,12 +1724,12 @@ static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
* extra paranoid to avoid a potential divide-by-zero if we screw up
* elsewhere in the driver.
*/
- if (WARN_ON(!bytes_per_pixel))
+ if (WARN_ON(!cpp))
return 0;
if (WARN_ON(!horiz_pixels))
return 0;
- return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
+ return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
}
struct ilk_wm_maximums {
@@ -1750,13 +1748,14 @@ static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
uint32_t mem_value,
bool is_lp)
{
- int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
+ int cpp = pstate->base.fb ?
+ drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
uint32_t method1, method2;
if (!cstate->base.active || !pstate->visible)
return 0;
- method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
+ method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
if (!is_lp)
return method1;
@@ -1764,8 +1763,7 @@ static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
cstate->base.adjusted_mode.crtc_htotal,
drm_rect_width(&pstate->dst),
- bpp,
- mem_value);
+ cpp, mem_value);
return min(method1, method2);
}
@@ -1778,18 +1776,18 @@ static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
const struct intel_plane_state *pstate,
uint32_t mem_value)
{
- int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
+ int cpp = pstate->base.fb ?
+ drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
uint32_t method1, method2;
if (!cstate->base.active || !pstate->visible)
return 0;
- method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
+ method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
cstate->base.adjusted_mode.crtc_htotal,
drm_rect_width(&pstate->dst),
- bpp,
- mem_value);
+ cpp, mem_value);
return min(method1, method2);
}
@@ -1801,7 +1799,8 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
const struct intel_plane_state *pstate,
uint32_t mem_value)
{
- int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
+ int cpp = pstate->base.fb ?
+ drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
if (!cstate->base.active || !pstate->visible)
return 0;
@@ -1809,8 +1808,7 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
cstate->base.adjusted_mode.crtc_htotal,
drm_rect_width(&pstate->dst),
- bpp,
- mem_value);
+ cpp, mem_value);
}
/* Only for WM_LP. */
@@ -1818,12 +1816,13 @@ static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
const struct intel_plane_state *pstate,
uint32_t pri_val)
{
- int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
+ int cpp = pstate->base.fb ?
+ drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
if (!cstate->base.active || !pstate->visible)
return 0;
- return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
+ return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
}
static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
@@ -3042,26 +3041,25 @@ static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
/*
* The max latency should be 257 (max the punit can code is 255 and we add 2us
- * for the read latency) and bytes_per_pixel should always be <= 8, so that
+ * for the read latency) and cpp should always be <= 8, so that
* should allow pixel_rate up to ~2 GHz which seems sufficient since max
* 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
*/
-static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
- uint32_t latency)
+static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
{
uint32_t wm_intermediate_val, ret;
if (latency == 0)
return UINT_MAX;
- wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
+ wm_intermediate_val = latency * pixel_rate * cpp / 512;
ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
return ret;
}
static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
- uint32_t horiz_pixels, uint8_t bytes_per_pixel,
+ uint32_t horiz_pixels, uint8_t cpp,
uint64_t tiling, uint32_t latency)
{
uint32_t ret;
@@ -3071,7 +3069,7 @@ static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
if (latency == 0)
return UINT_MAX;
- plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
+ plane_bytes_per_line = horiz_pixels * cpp;
if (tiling == I915_FORMAT_MOD_Y_TILED ||
tiling == I915_FORMAT_MOD_Yf_TILED) {
@@ -3121,23 +3119,21 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
uint32_t plane_bytes_per_line, plane_blocks_per_line;
uint32_t res_blocks, res_lines;
uint32_t selected_result;
- uint8_t bytes_per_pixel;
+ uint8_t cpp;
if (latency == 0 || !cstate->base.active || !fb)
return false;
- bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
+ cpp = drm_format_plane_cpp(fb->pixel_format, 0);
method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
- bytes_per_pixel,
- latency);
+ cpp, latency);
method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
cstate->base.adjusted_mode.crtc_htotal,
cstate->pipe_src_w,
- bytes_per_pixel,
- fb->modifier[0],
+ cpp, fb->modifier[0],
latency);
- plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
+ plane_bytes_per_line = cstate->pipe_src_w * cpp;
plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
@@ -3145,11 +3141,11 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
uint32_t min_scanlines = 4;
uint32_t y_tile_minimum;
if (intel_rotation_90_or_270(plane->state->rotation)) {
- int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
+ int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
drm_format_plane_cpp(fb->pixel_format, 1) :
drm_format_plane_cpp(fb->pixel_format, 0);
- switch (bpp) {
+ switch (cpp) {
case 1:
min_scanlines = 16;
break;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index f1ee7db0811a..a2582c455b36 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -351,7 +351,7 @@ vlv_update_plane(struct drm_plane *dplane,
int plane = intel_plane->plane;
u32 sprctl;
u32 sprsurf_offset, linear_offset;
- int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+ int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->dst.x1;
int crtc_y = plane_state->dst.y1;
@@ -422,10 +422,9 @@ vlv_update_plane(struct drm_plane *dplane,
crtc_w--;
crtc_h--;
- linear_offset = y * fb->pitches[0] + x * pixel_size;
+ linear_offset = y * fb->pitches[0] + x * cpp;
sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
- fb->modifier[0],
- pixel_size,
+ fb->modifier[0], cpp,
fb->pitches[0]);
linear_offset -= sprsurf_offset;
@@ -434,7 +433,7 @@ vlv_update_plane(struct drm_plane *dplane,
x += src_w;
y += src_h;
- linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
+ linear_offset += src_h * fb->pitches[0] + src_w * cpp;
}
if (key->flags) {
@@ -494,7 +493,7 @@ ivb_update_plane(struct drm_plane *plane,
enum pipe pipe = intel_plane->pipe;
u32 sprctl, sprscale = 0;
u32 sprsurf_offset, linear_offset;
- int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+ int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->dst.x1;
int crtc_y = plane_state->dst.y1;
@@ -556,10 +555,9 @@ ivb_update_plane(struct drm_plane *plane,
if (crtc_w != src_w || crtc_h != src_h)
sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
- linear_offset = y * fb->pitches[0] + x * pixel_size;
+ linear_offset = y * fb->pitches[0] + x * cpp;
sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
- fb->modifier[0],
- pixel_size,
+ fb->modifier[0], cpp,
fb->pitches[0]);
linear_offset -= sprsurf_offset;
@@ -570,8 +568,7 @@ ivb_update_plane(struct drm_plane *plane,
if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
x += src_w;
y += src_h;
- linear_offset += src_h * fb->pitches[0] +
- src_w * pixel_size;
+ linear_offset += src_h * fb->pitches[0] + src_w * cpp;
}
}
@@ -637,7 +634,7 @@ ilk_update_plane(struct drm_plane *plane,
int pipe = intel_plane->pipe;
u32 dvscntr, dvsscale;
u32 dvssurf_offset, linear_offset;
- int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+ int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->dst.x1;
int crtc_y = plane_state->dst.y1;
@@ -695,10 +692,9 @@ ilk_update_plane(struct drm_plane *plane,
if (crtc_w != src_w || crtc_h != src_h)
dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
- linear_offset = y * fb->pitches[0] + x * pixel_size;
+ linear_offset = y * fb->pitches[0] + x * cpp;
dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
- fb->modifier[0],
- pixel_size,
+ fb->modifier[0], cpp,
fb->pitches[0]);
linear_offset -= dvssurf_offset;
@@ -707,7 +703,7 @@ ilk_update_plane(struct drm_plane *plane,
x += src_w;
y += src_h;
- linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
+ linear_offset += src_h * fb->pitches[0] + src_w * cpp;
}
if (key->flags) {
@@ -772,7 +768,6 @@ intel_check_sprite_plane(struct drm_plane *plane,
int hscale, vscale;
int max_scale, min_scale;
bool can_scale;
- int pixel_size;
if (!fb) {
state->visible = false;
@@ -894,6 +889,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
/* Check size restrictions when scaling */
if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
unsigned int width_bytes;
+ int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
WARN_ON(!can_scale);
@@ -905,9 +901,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
if (src_w < 3 || src_h < 3)
state->visible = false;
- pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
- width_bytes = ((src_x * pixel_size) & 63) +
- src_w * pixel_size;
+ width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
width_bytes > 4096 || fb->pitches[0] > 4096)) {
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height()
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (4 preceding siblings ...)
2016-01-20 19:05 ` [PATCH 05/18] drm/i915: Standardize on 'cpp' for bytes per pixel ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-25 17:08 ` Daniel Vetter
` (2 more replies)
2016-01-20 19:05 ` [PATCH 07/18] drm/i915: Fix intel_tile_width() parameters ville.syrjala
` (15 subsequent siblings)
21 siblings, 3 replies; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a few helpers to get the dimensions of the chroma plane(s).
v2: Add kernel-doc (Daniel)
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
include/drm/drm_crtc.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index c65a212db77e..91195c403422 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -2482,6 +2482,36 @@ extern int drm_format_num_planes(uint32_t format);
extern int drm_format_plane_cpp(uint32_t format, int plane);
extern int drm_format_horz_chroma_subsampling(uint32_t format);
extern int drm_format_vert_chroma_subsampling(uint32_t format);
+/**
+ * drm_format_plane_width - width of the plane given the first plane
+ * @width: width of the first plane
+ * @format: pixel format
+ * @plane: plane index
+ *
+ * Returns the width of @plane, given that the width of the first plane
+ * is @width.
+ */
+static inline int drm_format_plane_width(int width, uint32_t format, int plane)
+{
+ if (plane == 0)
+ return width;
+ return width / drm_format_horz_chroma_subsampling(format);
+}
+/**
+ * drm_format_plane_height - height of the plane given the first plane
+ * @height: height of the first plane
+ * @format: pixel format
+ * @plane: plane index
+ *
+ * Returns the height of @plane, given that the height of the first plane
+ * is @height.
+ */
+static inline int drm_format_plane_height(int height, uint32_t format, int plane)
+{
+ if (plane == 0)
+ return height;
+ return height / drm_format_vert_chroma_subsampling(format);
+}
extern const char *drm_get_format_name(uint32_t format);
extern struct drm_property *drm_mode_create_rotation_property(struct drm_device *dev,
unsigned int supported_rotations);
--
2.4.10
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dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH 07/18] drm/i915: Fix intel_tile_width() parameters
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (5 preceding siblings ...)
2016-01-20 19:05 ` [PATCH v2 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height() ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-25 17:12 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH v3 08/18] drm/i915: Pass 90/270 vs. 0/180 rotation info for intel_gen4_compute_page_offset() ville.syrjala
` (14 subsequent siblings)
21 siblings, 1 reply; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The fb_modifiers and cpp arguments passed to intel_tile_width() in
intel_fill_fb_ggtt_view() got accidentally swapped around. I'm pretty
sure I fixed this already, but could be I lost the fix accidentally
during some rebases or something. Anyway, fix it up for real.
Fixes: d9b3288ecf2f ("drm/i915: change intel_fill_fb_ggtt_view() to use the real tile size")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f94ddad704b2..cfd52ea68e34 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2306,7 +2306,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
tile_size = intel_tile_size(dev_priv);
cpp = drm_format_plane_cpp(fb->pixel_format, 0);
- tile_width = intel_tile_width(dev_priv, cpp, fb->modifier[0]);
+ tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp);
tile_height = tile_size / tile_width;
info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
--
2.4.10
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v3 08/18] drm/i915: Pass 90/270 vs. 0/180 rotation info for intel_gen4_compute_page_offset()
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (6 preceding siblings ...)
2016-01-20 19:05 ` [PATCH 07/18] drm/i915: Fix intel_tile_width() parameters ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-25 17:30 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH v2 09/18] drm/i915: Support for extra alignment for tiled surfaces ville.syrjala
` (13 subsequent siblings)
21 siblings, 1 reply; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The page aligned surface address calculation needs to know which way
things are rotated. The contract now says that the caller must pass the
rotate x/y coordinates, as well as the tile_height aligned stride in
the tile_height direction. This will make it fairly simple to deal with
90/270 degree rotation on SKL+ where we have to deal with the rotated
view into the GTT.
v2: Pass rotation instead of bool even thoughwe only care about 0/180 vs. 90/270
v3: Introduce intel_tile_dims(), and don't mix up different units so much
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2)
---
drivers/gpu/drm/i915/intel_display.c | 66 +++++++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_sprite.c | 18 +++++-----
3 files changed, 59 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cfd52ea68e34..bda3224021b2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2269,6 +2269,18 @@ unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
intel_tile_width(dev_priv, fb_modifier, cpp);
}
+/* Return the tile dimensions in pixel units */
+static void intel_tile_dims(const struct drm_i915_private *dev_priv,
+ unsigned int *tile_width,
+ unsigned int *tile_height,
+ uint64_t fb_modifier,
+ unsigned int cpp)
+{
+ *tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
+ *tile_height = intel_tile_size(dev_priv) / *tile_width;
+ *tile_width /= cpp;
+}
+
unsigned int
intel_fb_align_height(struct drm_device *dev, unsigned int height,
uint32_t pixel_format, uint64_t fb_modifier)
@@ -2306,19 +2318,19 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
tile_size = intel_tile_size(dev_priv);
cpp = drm_format_plane_cpp(fb->pixel_format, 0);
- tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp);
- tile_height = tile_size / tile_width;
+ intel_tile_dims(dev_priv, &tile_width, &tile_height,
+ fb->modifier[0], cpp);
- info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
+ info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
info->size = info->width_pages * info->height_pages * tile_size;
if (info->pixel_format == DRM_FORMAT_NV12) {
cpp = drm_format_plane_cpp(fb->pixel_format, 1);
- tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp);
- tile_height = tile_size / tile_width;
+ intel_tile_dims(dev_priv, &tile_width, &tile_height,
+ fb->modifier[1], cpp);
- info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width);
+ info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
}
@@ -2446,29 +2458,43 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
i915_gem_object_unpin_from_display_plane(obj, &view);
}
-/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
- * is assumed to be a power-of-two. */
+/*
+ * Computes the linear offset to the base tile and adjusts
+ * x, y. bytes per pixel is assumed to be a power-of-two.
+ *
+ * In the 90/270 rotated case, x and y are assumed
+ * to be already rotated to match the rotated GTT view, and
+ * pitch is the tile_height aligned framebuffer height.
+ */
u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
int *x, int *y,
uint64_t fb_modifier,
unsigned int cpp,
- unsigned int pitch)
+ unsigned int pitch,
+ unsigned int rotation)
{
if (fb_modifier != DRM_FORMAT_MOD_NONE) {
unsigned int tile_size, tile_width, tile_height;
- unsigned int tile_rows, tiles;
+ unsigned int tile_rows, tiles, pitch_tiles;
tile_size = intel_tile_size(dev_priv);
- tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
- tile_height = tile_size / tile_width;
+ intel_tile_dims(dev_priv, &tile_width, &tile_height,
+ fb_modifier, cpp);
+
+ if (intel_rotation_90_or_270(rotation)) {
+ pitch_tiles = pitch / tile_height;
+ swap(tile_width, tile_height);
+ } else {
+ pitch_tiles = pitch / (tile_width * cpp);
+ }
tile_rows = *y / tile_height;
*y %= tile_height;
- tiles = *x / (tile_width/cpp);
- *x %= tile_width/cpp;
+ tiles = *x / tile_width;
+ *x %= tile_width;
- return tile_rows * pitch * tile_height + tiles * tile_size;
+ return (tile_rows * pitch_tiles + tiles) * tile_size;
} else {
unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
unsigned int offset;
@@ -2709,6 +2735,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
u32 linear_offset;
u32 dspcntr;
i915_reg_t reg = DSPCNTR(plane);
+ unsigned int rotation = plane_state->base.rotation;
int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
int x = plane_state->src.x1 >> 16;
int y = plane_state->src.y1 >> 16;
@@ -2775,13 +2802,13 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
intel_crtc->dspaddr_offset =
intel_compute_tile_offset(dev_priv, &x, &y,
fb->modifier[0], cpp,
- fb->pitches[0]);
+ fb->pitches[0], rotation);
linear_offset -= intel_crtc->dspaddr_offset;
} else {
intel_crtc->dspaddr_offset = linear_offset;
}
- if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
+ if (rotation == BIT(DRM_ROTATE_180)) {
dspcntr |= DISPPLANE_ROTATE_180;
x += (crtc_state->pipe_src_w - 1);
@@ -2839,6 +2866,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
u32 linear_offset;
u32 dspcntr;
i915_reg_t reg = DSPCNTR(plane);
+ unsigned int rotation = plane_state->base.rotation;
int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
int x = plane_state->src.x1 >> 16;
int y = plane_state->src.y1 >> 16;
@@ -2882,9 +2910,9 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
intel_crtc->dspaddr_offset =
intel_compute_tile_offset(dev_priv, &x, &y,
fb->modifier[0], cpp,
- fb->pitches[0]);
+ fb->pitches[0], rotation);
linear_offset -= intel_crtc->dspaddr_offset;
- if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
+ if (rotation == BIT(DRM_ROTATE_180)) {
dspcntr |= DISPPLANE_ROTATE_180;
if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f620023ed134..223693dbfe7c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1176,7 +1176,8 @@ u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
int *x, int *y,
uint64_t fb_modifier,
unsigned int cpp,
- unsigned int pitch);
+ unsigned int pitch,
+ unsigned int rotation);
void intel_prepare_reset(struct drm_device *dev);
void intel_finish_reset(struct drm_device *dev);
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index a2582c455b36..7dc2b8b2a4ac 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -193,7 +193,7 @@ skl_update_plane(struct drm_plane *drm_plane,
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 surf_addr;
u32 tile_height, plane_offset, plane_size;
- unsigned int rotation;
+ unsigned int rotation = plane_state->base.rotation;
int x_offset, y_offset;
int crtc_x = plane_state->dst.x1;
int crtc_y = plane_state->dst.y1;
@@ -213,7 +213,6 @@ skl_update_plane(struct drm_plane *drm_plane,
plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
- rotation = plane_state->base.rotation;
plane_ctl |= skl_plane_ctl_rotation(rotation);
stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
@@ -351,6 +350,7 @@ vlv_update_plane(struct drm_plane *dplane,
int plane = intel_plane->plane;
u32 sprctl;
u32 sprsurf_offset, linear_offset;
+ unsigned int rotation = dplane->state->rotation;
int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->dst.x1;
@@ -425,10 +425,10 @@ vlv_update_plane(struct drm_plane *dplane,
linear_offset = y * fb->pitches[0] + x * cpp;
sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
fb->modifier[0], cpp,
- fb->pitches[0]);
+ fb->pitches[0], rotation);
linear_offset -= sprsurf_offset;
- if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
+ if (rotation == BIT(DRM_ROTATE_180)) {
sprctl |= SP_ROTATE_180;
x += src_w;
@@ -493,6 +493,7 @@ ivb_update_plane(struct drm_plane *plane,
enum pipe pipe = intel_plane->pipe;
u32 sprctl, sprscale = 0;
u32 sprsurf_offset, linear_offset;
+ unsigned int rotation = plane_state->base.rotation;
int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->dst.x1;
@@ -558,10 +559,10 @@ ivb_update_plane(struct drm_plane *plane,
linear_offset = y * fb->pitches[0] + x * cpp;
sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
fb->modifier[0], cpp,
- fb->pitches[0]);
+ fb->pitches[0], rotation);
linear_offset -= sprsurf_offset;
- if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
+ if (rotation == BIT(DRM_ROTATE_180)) {
sprctl |= SPRITE_ROTATE_180;
/* HSW and BDW does this automagically in hardware */
@@ -634,6 +635,7 @@ ilk_update_plane(struct drm_plane *plane,
int pipe = intel_plane->pipe;
u32 dvscntr, dvsscale;
u32 dvssurf_offset, linear_offset;
+ unsigned int rotation = plane_state->base.rotation;
int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->dst.x1;
@@ -695,10 +697,10 @@ ilk_update_plane(struct drm_plane *plane,
linear_offset = y * fb->pitches[0] + x * cpp;
dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
fb->modifier[0], cpp,
- fb->pitches[0]);
+ fb->pitches[0], rotation);
linear_offset -= dvssurf_offset;
- if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
+ if (rotation == BIT(DRM_ROTATE_180)) {
dvscntr |= DVS_ROTATE_180;
x += src_w;
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 09/18] drm/i915: Support for extra alignment for tiled surfaces
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (7 preceding siblings ...)
2016-01-20 19:05 ` [PATCH v3 08/18] drm/i915: Pass 90/270 vs. 0/180 rotation info for intel_gen4_compute_page_offset() ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-25 17:24 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH v2 10/18] drm/i915: Don't pass plane+plane_state to intel_pin_and_fence_fb_obj() ville.syrjala
` (12 subsequent siblings)
21 siblings, 1 reply; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
SKL+ needs >4K alignment for tiled surfaces, so make
intel_compute_page_offset() handle it.
The way we do it is first we compute the closest tile boundary
as before, and then figure out how many tiles we need to go
to reach the desired alignment. The difference in the offset
is then added into the x/y offsets.
v2: Be less confusing wrt. units (pixels vs. bytes) (Daniel)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++++++++++++++++----
1 file changed, 42 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bda3224021b2..a102fabce5b4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2459,6 +2459,35 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
}
/*
+ * Adjust the tile offset by moving the difference into
+ * the x/y offsets.
+ *
+ * Input tile dimensions and pitch must already be
+ * rotated to match x and y, and in pixel units.
+ */
+static void intel_adjust_tile_offset(int *x, int *y,
+ unsigned int tile_width,
+ unsigned int tile_height,
+ unsigned int tile_size,
+ unsigned int pitch_tiles,
+ unsigned int old_offset,
+ unsigned int new_offset)
+{
+ unsigned int tiles;
+
+ WARN_ON(old_offset & (tile_size - 1));
+ WARN_ON(new_offset & (tile_size - 1));
+ WARN_ON(new_offset > old_offset);
+
+ tiles = (old_offset - new_offset) / tile_size;
+ if (tiles == 0)
+ return;
+
+ *y += tiles / pitch_tiles * tile_height;
+ *x += tiles % pitch_tiles * tile_width;
+}
+
+/*
* Computes the linear offset to the base tile and adjusts
* x, y. bytes per pixel is assumed to be a power-of-two.
*
@@ -2473,6 +2502,12 @@ u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
unsigned int pitch,
unsigned int rotation)
{
+ unsigned int offset, alignment;
+
+ alignment = intel_surf_alignment(dev_priv, fb_modifier);
+ if (alignment)
+ alignment--;
+
if (fb_modifier != DRM_FORMAT_MOD_NONE) {
unsigned int tile_size, tile_width, tile_height;
unsigned int tile_rows, tiles, pitch_tiles;
@@ -2494,16 +2529,18 @@ u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
tiles = *x / tile_width;
*x %= tile_width;
- return (tile_rows * pitch_tiles + tiles) * tile_size;
- } else {
- unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
- unsigned int offset;
+ offset = (tile_rows * pitch_tiles + tiles) * tile_size;
+ intel_adjust_tile_offset(x, y, tile_width, tile_height,
+ tile_size, pitch_tiles,
+ offset, offset & ~alignment);
+ } else {
offset = *y * pitch + *x * cpp;
*y = (offset & alignment) / pitch;
*x = ((offset & alignment) - *y * pitch) / cpp;
- return offset & ~alignment;
}
+
+ return offset & ~alignment;
}
static int i9xx_format_to_fourcc(int format)
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 10/18] drm/i915: Don't pass plane+plane_state to intel_pin_and_fence_fb_obj()
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (8 preceding siblings ...)
2016-01-20 19:05 ` [PATCH v2 09/18] drm/i915: Support for extra alignment for tiled surfaces ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-20 19:05 ` [PATCH 11/18] drm/i915: Pass drm_frambuffer to intel_compute_page_offset() ville.syrjala
` (11 subsequent siblings)
21 siblings, 0 replies; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_pin_and_fence_fb_obj() only needs the framebuffer, and the desird
rotation (to find the right GTT view for it), so no need to pass all
kinds of plane stuff.
The main motivation is to get rid of the uggy NULL plane_state handling
due to fbdev.
v2: Add a note why I really want this
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Grumpily-Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 41 +++++++++++++++---------------------
drivers/gpu/drm/i915/intel_drv.h | 5 ++---
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
3 files changed, 20 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a102fabce5b4..29787ee888d3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2292,8 +2292,9 @@ intel_fb_align_height(struct drm_device *dev, unsigned int height,
}
static void
-intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
- const struct drm_plane_state *plane_state)
+intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
+ const struct drm_framebuffer *fb,
+ unsigned int rotation)
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
struct intel_rotation_info *info = &view->params.rotated;
@@ -2301,10 +2302,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
*view = i915_ggtt_view_normal;
- if (!plane_state)
- return;
-
- if (!intel_rotation_90_or_270(plane_state->rotation))
+ if (!intel_rotation_90_or_270(rotation))
return;
*view = i915_ggtt_view_rotated;
@@ -2369,9 +2367,8 @@ static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv
}
int
-intel_pin_and_fence_fb_obj(struct drm_plane *plane,
- struct drm_framebuffer *fb,
- const struct drm_plane_state *plane_state)
+intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
+ unsigned int rotation)
{
struct drm_device *dev = fb->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2384,7 +2381,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
- intel_fill_fb_ggtt_view(&view, fb, plane_state);
+ intel_fill_fb_ggtt_view(&view, fb, rotation);
/* Note that the w/a also requires 64 PTE of padding following the
* bo. We currently fill all unused PTE with the shadow page and so
@@ -2442,15 +2439,14 @@ err_pm:
return ret;
}
-static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
- const struct drm_plane_state *plane_state)
+static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
{
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
struct i915_ggtt_view view;
WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
- intel_fill_fb_ggtt_view(&view, fb, plane_state);
+ intel_fill_fb_ggtt_view(&view, fb, rotation);
if (view.type == I915_GGTT_VIEW_NORMAL)
i915_gem_object_unpin_fence(obj);
@@ -3002,7 +2998,7 @@ u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
u64 offset;
intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
- intel_plane->base.state);
+ intel_plane->base.state->rotation);
vma = i915_gem_obj_to_ggtt_view(obj, &view);
if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
@@ -10969,7 +10965,7 @@ static void intel_unpin_work_fn(struct work_struct *__work)
struct drm_plane *primary = crtc->base.primary;
mutex_lock(&dev->struct_mutex);
- intel_unpin_fb_obj(work->old_fb, primary->state);
+ intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
drm_gem_object_unreference(&work->pending_flip_obj->base);
if (work->flip_queued_req)
@@ -11733,8 +11729,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
goto cleanup_pending;
}
- ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
- crtc->primary->state);
+ ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
if (ret)
goto cleanup_pending;
@@ -11783,7 +11778,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
return 0;
cleanup_unpin:
- intel_unpin_fb_obj(fb, crtc->primary->state);
+ intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
cleanup_pending:
if (request)
i915_gem_request_cancel(request);
@@ -13924,7 +13919,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
if (ret)
DRM_DEBUG_KMS("failed to attach phys object\n");
} else {
- ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
+ ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
}
if (ret == 0) {
@@ -13968,7 +13963,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
!INTEL_INFO(dev)->cursor_needs_physical))
- intel_unpin_fb_obj(old_state->fb, old_state);
+ intel_unpin_fb_obj(old_state->fb, old_state->rotation);
/* prepare_fb aborted? */
if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
@@ -13976,7 +13971,6 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
i915_gem_request_assign(&old_intel_state->wait_req, NULL);
-
}
int
@@ -16073,9 +16067,8 @@ void intel_modeset_gem_init(struct drm_device *dev)
continue;
mutex_lock(&dev->struct_mutex);
- ret = intel_pin_and_fence_fb_obj(c->primary,
- c->primary->fb,
- c->primary->state);
+ ret = intel_pin_and_fence_fb_obj(c->primary->fb,
+ c->primary->state->rotation);
mutex_unlock(&dev->struct_mutex);
if (ret) {
DRM_ERROR("failed to pin boot fb on pipe %d\n",
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 223693dbfe7c..2d3ecb592a91 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1106,9 +1106,8 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
void intel_release_load_detect_pipe(struct drm_connector *connector,
struct intel_load_detect_pipe *old,
struct drm_modeset_acquire_ctx *ctx);
-int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
- struct drm_framebuffer *fb,
- const struct drm_plane_state *plane_state);
+int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
+ unsigned int rotation);
struct drm_framebuffer *
__intel_framebuffer_create(struct drm_device *dev,
struct drm_mode_fb_cmd2 *mode_cmd,
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 09840f4380f9..082deb31c900 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -220,7 +220,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
* This also validates that any existing fb inherited from the
* BIOS is suitable for own access.
*/
- ret = intel_pin_and_fence_fb_obj(NULL, &ifbdev->fb->base, NULL);
+ ret = intel_pin_and_fence_fb_obj(&ifbdev->fb->base, BIT(DRM_ROTATE_0));
if (ret)
goto out_unlock;
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH 11/18] drm/i915: Pass drm_frambuffer to intel_compute_page_offset()
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (9 preceding siblings ...)
2016-01-20 19:05 ` [PATCH v2 10/18] drm/i915: Don't pass plane+plane_state to intel_pin_and_fence_fb_obj() ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-20 19:05 ` [PATCH 12/18] drm/i915: Reorganize intel_rotation_info ville.syrjala
` (10 subsequent siblings)
21 siblings, 0 replies; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_compute_page_offsets() gets passed a bunch of the framebuffer
metadate sepearately. Just pass the framebuffer itself to make life
simpler for the caller, and make it less likely they would make a
mistake in the order of the arguments (as most as just unsigned ints and
such).
We still pass the pitch explicitly since for 90/270 degree rotation
the caller has to pass in the right thing.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/i915/intel_display.c | 15 +++++++--------
drivers/gpu/drm/i915/intel_drv.h | 6 ++----
drivers/gpu/drm/i915/intel_sprite.c | 9 +++------
3 files changed, 12 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 29787ee888d3..084c8ae3668f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2491,13 +2491,14 @@ static void intel_adjust_tile_offset(int *x, int *y,
* to be already rotated to match the rotated GTT view, and
* pitch is the tile_height aligned framebuffer height.
*/
-u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
- int *x, int *y,
- uint64_t fb_modifier,
- unsigned int cpp,
+u32 intel_compute_tile_offset(int *x, int *y,
+ const struct drm_framebuffer *fb, int plane,
unsigned int pitch,
unsigned int rotation)
{
+ const struct drm_i915_private *dev_priv = to_i915(fb->dev);
+ uint64_t fb_modifier = fb->modifier[plane];
+ unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
unsigned int offset, alignment;
alignment = intel_surf_alignment(dev_priv, fb_modifier);
@@ -2833,8 +2834,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
if (INTEL_INFO(dev)->gen >= 4) {
intel_crtc->dspaddr_offset =
- intel_compute_tile_offset(dev_priv, &x, &y,
- fb->modifier[0], cpp,
+ intel_compute_tile_offset(&x, &y, fb, 0,
fb->pitches[0], rotation);
linear_offset -= intel_crtc->dspaddr_offset;
} else {
@@ -2941,8 +2941,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
linear_offset = y * fb->pitches[0] + x * cpp;
intel_crtc->dspaddr_offset =
- intel_compute_tile_offset(dev_priv, &x, &y,
- fb->modifier[0], cpp,
+ intel_compute_tile_offset(&x, &y, fb, 0,
fb->pitches[0], rotation);
linear_offset -= intel_crtc->dspaddr_offset;
if (rotation == BIT(DRM_ROTATE_180)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2d3ecb592a91..b9ef9d5f1041 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1171,10 +1171,8 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
-u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
- int *x, int *y,
- uint64_t fb_modifier,
- unsigned int cpp,
+u32 intel_compute_tile_offset(int *x, int *y,
+ const struct drm_framebuffer *fb, int plane,
unsigned int pitch,
unsigned int rotation);
void intel_prepare_reset(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 7dc2b8b2a4ac..8821533561b1 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -423,8 +423,7 @@ vlv_update_plane(struct drm_plane *dplane,
crtc_h--;
linear_offset = y * fb->pitches[0] + x * cpp;
- sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
- fb->modifier[0], cpp,
+ sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
fb->pitches[0], rotation);
linear_offset -= sprsurf_offset;
@@ -557,8 +556,7 @@ ivb_update_plane(struct drm_plane *plane,
sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
linear_offset = y * fb->pitches[0] + x * cpp;
- sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
- fb->modifier[0], cpp,
+ sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
fb->pitches[0], rotation);
linear_offset -= sprsurf_offset;
@@ -695,8 +693,7 @@ ilk_update_plane(struct drm_plane *plane,
dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
linear_offset = y * fb->pitches[0] + x * cpp;
- dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
- fb->modifier[0], cpp,
+ dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
fb->pitches[0], rotation);
linear_offset -= dvssurf_offset;
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH 12/18] drm/i915: Reorganize intel_rotation_info
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (10 preceding siblings ...)
2016-01-20 19:05 ` [PATCH 11/18] drm/i915: Pass drm_frambuffer to intel_compute_page_offset() ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-25 17:38 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH 13/18] drm/i915: Move the NULL sg handling out from rotate_pages() ville.syrjala
` (9 subsequent siblings)
21 siblings, 1 reply; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Throw out a bunch of unnecessary stuff from struct intel_rotation_info,
and pull most of the remaining stuff to live under an array of
per-color plane sub-structures.
What still remains outside the sub-structure will be reorgranized later
as well, but that requires more work elsewhere so leave it be for now.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 35 +++++++++++++++--------------------
drivers/gpu/drm/i915/i915_gem_gtt.h | 11 ++++-------
drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++----------
drivers/gpu/drm/i915/intel_drv.h | 1 +
4 files changed, 35 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b3d8e2b0948c..f95468cd0470 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3367,7 +3367,7 @@ static struct sg_table *
intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
struct drm_i915_gem_object *obj)
{
- unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
+ unsigned int size_pages = rot_info->plane[0].width * rot_info->plane[0].height;
unsigned int size_pages_uv;
struct sg_page_iter sg_iter;
unsigned long i;
@@ -3385,7 +3385,7 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
/* Account for UV plane with NV12. */
if (rot_info->pixel_format == DRM_FORMAT_NV12)
- size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
+ size_pages_uv = rot_info->plane[1].width * rot_info->plane[1].height;
else
size_pages_uv = 0;
@@ -3407,9 +3407,9 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
/* Rotate the pages. */
sg = rotate_pages(page_addr_list, 0,
- rot_info->width_pages, rot_info->height_pages,
- rot_info->width_pages,
- st, NULL);
+ rot_info->plane[0].width, rot_info->plane[0].height,
+ rot_info->plane[0].width,
+ st, NULL);
/* Append the UV plane if NV12. */
if (rot_info->pixel_format == DRM_FORMAT_NV12) {
@@ -3421,18 +3421,15 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
rot_info->uv_start_page = uv_start_page;
- rotate_pages(page_addr_list, uv_start_page,
- rot_info->width_pages_uv,
- rot_info->height_pages_uv,
- rot_info->width_pages_uv,
+ rotate_pages(page_addr_list, rot_info->uv_start_page,
+ rot_info->plane[1].width, rot_info->plane[1].height,
+ rot_info->plane[1].width,
st, sg);
}
- DRM_DEBUG_KMS(
- "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
- obj->base.size, rot_info->pitch, rot_info->height,
- rot_info->pixel_format, rot_info->width_pages,
- rot_info->height_pages, size_pages + size_pages_uv,
+ DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
+ obj->base.size, rot_info->plane[0].width,
+ rot_info->plane[0].height, size_pages + size_pages_uv,
size_pages);
drm_free_large(page_addr_list);
@@ -3444,11 +3441,9 @@ err_sg_alloc:
err_st_alloc:
drm_free_large(page_addr_list);
- DRM_DEBUG_KMS(
- "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
- obj->base.size, ret, rot_info->pitch, rot_info->height,
- rot_info->pixel_format, rot_info->width_pages,
- rot_info->height_pages, size_pages + size_pages_uv,
+ DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n",
+ obj->base.size, ret, rot_info->plane[0].width,
+ rot_info->plane[0].height, size_pages + size_pages_uv,
size_pages);
return ERR_PTR(ret);
}
@@ -3600,7 +3595,7 @@ i915_ggtt_view_size(struct drm_i915_gem_object *obj,
if (view->type == I915_GGTT_VIEW_NORMAL) {
return obj->base.size;
} else if (view->type == I915_GGTT_VIEW_ROTATED) {
- return view->params.rotated.size;
+ return intel_rotation_info_size(&view->params.rotated) << PAGE_SHIFT;
} else if (view->type == I915_GGTT_VIEW_PARTIAL) {
return view->params.partial.size << PAGE_SHIFT;
} else {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index f520c90e5377..4b8a378b9d3f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -135,16 +135,13 @@ enum i915_ggtt_view_type {
};
struct intel_rotation_info {
- unsigned int height;
- unsigned int pitch;
unsigned int uv_offset;
uint32_t pixel_format;
- uint64_t fb_modifier;
- unsigned int width_pages, height_pages;
- uint64_t size;
- unsigned int width_pages_uv, height_pages_uv;
- uint64_t size_uv;
unsigned int uv_start_page;
+ struct {
+ /* tiles */
+ unsigned int width, height;
+ } plane[2];
};
struct i915_ggtt_view {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 084c8ae3668f..899ffb1a9b10 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2291,6 +2291,17 @@ intel_fb_align_height(struct drm_device *dev, unsigned int height,
return ALIGN(height, tile_height);
}
+unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
+{
+ unsigned int size = 0;
+ int i;
+
+ for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
+ size += rot_info->plane[i].width * rot_info->plane[i].height;
+
+ return size;
+}
+
static void
intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
const struct drm_framebuffer *fb,
@@ -2307,11 +2318,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
*view = i915_ggtt_view_rotated;
- info->height = fb->height;
- info->pixel_format = fb->pixel_format;
- info->pitch = fb->pitches[0];
info->uv_offset = fb->offsets[1];
- info->fb_modifier = fb->modifier[0];
tile_size = intel_tile_size(dev_priv);
@@ -2319,18 +2326,16 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
intel_tile_dims(dev_priv, &tile_width, &tile_height,
fb->modifier[0], cpp);
- info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
- info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
- info->size = info->width_pages * info->height_pages * tile_size;
+ info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
+ info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
if (info->pixel_format == DRM_FORMAT_NV12) {
cpp = drm_format_plane_cpp(fb->pixel_format, 1);
intel_tile_dims(dev_priv, &tile_width, &tile_height,
fb->modifier[1], cpp);
- info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
- info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
- info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
+ info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
+ info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
}
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b9ef9d5f1041..f251f253cc99 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1059,6 +1059,7 @@ void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
/* intel_display.c */
extern const struct drm_plane_funcs intel_plane_funcs;
+unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
bool intel_has_pending_fb_unpin(struct drm_device *dev);
int intel_pch_rawclk(struct drm_device *dev);
int intel_hrawclk(struct drm_device *dev);
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH 13/18] drm/i915: Move the NULL sg handling out from rotate_pages()
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (11 preceding siblings ...)
2016-01-20 19:05 ` [PATCH 12/18] drm/i915: Reorganize intel_rotation_info ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-25 17:40 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH 14/18] drm/i915: Embed rotation_info under intel_framebuffer ville.syrjala
` (8 subsequent siblings)
21 siblings, 1 reply; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
rotate_pages() checks to see if it got called with a NULL sg, and then
goes to extract it from sg->sgl. It always gets called with a NULL sg
for the first plane, so moving the initial 'sg=st->sgl' assignment out
into intel_rotate_fb_obj_pages() seems less special-casey.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f95468cd0470..db80ec08cca4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3339,11 +3339,6 @@ rotate_pages(const dma_addr_t *in, unsigned int offset,
unsigned int column, row;
unsigned int src_idx;
- if (!sg) {
- st->nents = 0;
- sg = st->sgl;
- }
-
for (column = 0; column < width; column++) {
src_idx = stride * (height - 1) + column;
for (row = 0; row < height; row++) {
@@ -3405,11 +3400,14 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
i++;
}
+ st->nents = 0;
+ sg = st->sgl;
+
/* Rotate the pages. */
sg = rotate_pages(page_addr_list, 0,
rot_info->plane[0].width, rot_info->plane[0].height,
rot_info->plane[0].width,
- st, NULL);
+ st, sg);
/* Append the UV plane if NV12. */
if (rot_info->pixel_format == DRM_FORMAT_NV12) {
@@ -3421,10 +3419,10 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
rot_info->uv_start_page = uv_start_page;
- rotate_pages(page_addr_list, rot_info->uv_start_page,
- rot_info->plane[1].width, rot_info->plane[1].height,
- rot_info->plane[1].width,
- st, sg);
+ sg = rotate_pages(page_addr_list, rot_info->uv_start_page,
+ rot_info->plane[1].width, rot_info->plane[1].height,
+ rot_info->plane[1].width,
+ st, sg);
}
DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH 14/18] drm/i915: Embed rotation_info under intel_framebuffer
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (12 preceding siblings ...)
2016-01-20 19:05 ` [PATCH 13/18] drm/i915: Move the NULL sg handling out from rotate_pages() ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-20 21:08 ` Chris Wilson
2016-01-25 17:42 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH v3 15/18] drm/i915: Rewrite fb rotation GTT handling ville.syrjala
` (7 subsequent siblings)
21 siblings, 2 replies; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Instead of repopulatin the rotation_info struct for the fb every time
we try to use the fb, we can just populate it once when creating the fb,
and later we can just copy the pre-populate struct into the gtt_view.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++-----------
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 899ffb1a9b10..7ed33b5eb443 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2307,18 +2307,20 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
const struct drm_framebuffer *fb,
unsigned int rotation)
{
- struct drm_i915_private *dev_priv = to_i915(fb->dev);
- struct intel_rotation_info *info = &view->params.rotated;
- unsigned int tile_size, tile_width, tile_height, cpp;
-
- *view = i915_ggtt_view_normal;
-
- if (!intel_rotation_90_or_270(rotation))
- return;
-
- *view = i915_ggtt_view_rotated;
+ if (intel_rotation_90_or_270(rotation)) {
+ *view = i915_ggtt_view_rotated;
+ view->params.rotated = to_intel_framebuffer(fb)->rot_info;
+ } else {
+ *view = i915_ggtt_view_normal;
+ }
+}
- info->uv_offset = fb->offsets[1];
+static void
+intel_fill_fb_info(struct drm_i915_private *dev_priv,
+ struct drm_framebuffer *fb)
+{
+ struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
+ unsigned int tile_size, tile_width, tile_height, cpp;
tile_size = intel_tile_size(dev_priv);
@@ -2334,6 +2336,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
intel_tile_dims(dev_priv, &tile_width, &tile_height,
fb->modifier[1], cpp);
+ info->uv_offset = fb->offsets[1];
info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
}
@@ -14906,6 +14909,8 @@ static int intel_framebuffer_init(struct drm_device *dev,
drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
intel_fb->obj = obj;
+ intel_fill_fb_info(dev_priv, &intel_fb->base);
+
ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
if (ret) {
DRM_ERROR("framebuffer init failed %d\n", ret);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f251f253cc99..8a0f4dfd04a6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -118,6 +118,7 @@ enum intel_output_type {
struct intel_framebuffer {
struct drm_framebuffer base;
struct drm_i915_gem_object *obj;
+ struct intel_rotation_info rot_info;
};
struct intel_fbdev {
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v3 15/18] drm/i915: Rewrite fb rotation GTT handling
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (13 preceding siblings ...)
2016-01-20 19:05 ` [PATCH 14/18] drm/i915: Embed rotation_info under intel_framebuffer ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-20 19:05 ` [PATCH v2 16/18] drm/i915: Don't pass pitch to intel_compute_page_offset() ville.syrjala
` (6 subsequent siblings)
21 siblings, 0 replies; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Redo the fb rotation handling in order to:
- eliminate the NV12 special casing
- handle fb->offsets[] properly
- make the rotation handling reasier for the plane code
To achieve these goals we reduce intel_rotation_info to only contain
(for each plane) the rotated view width,height,stride in tile units,
and the page offset into the object where the plane starts. Each plane
is handled exactly the same way, no special casing for NV12 or other
formats. We then store the computed rotation_info under
intel_framebuffer so that we don't have to recompute it again.
To handle fb->offsets[] we treat them as a linear offsets and convert
them to x/y offsets from the start of the relevant GTT mapping (either
normal or rotated). We store the x/y offsets under intel_framebuffer,
and for some extra convenience we also store the rotated pitch (ie.
tile aligned plane height). So for each plane we have the normal
x/y offsets, rotated x/y offsets, and the rotated pitch. The normal
pitch is available already in fb->pitches[].
While we're gathering up all that extra information, we can also easily
compute the storage requirements for the framebuffer, so that we can
check that the object is big enough to hold it.
When it comes time to deal with the plane source coordinates, we first
rotate the clipped src coordinates to match the relevant GTT view
orientation, then add to them the fb x/y offsets. Next we compute
the aligned surface page offset, and as a result we're left with some
residual x/y offsets. Finally, if required by the hardware, we convert
the remaining x/y offsets into a linear offset.
For gen2/3 we simply skip computing the final page offset, and just
convert the src+fb x/y offsets directly into a linear offset since
that's what the hardware wants.
After this all platforms, incluing SKL+, compute these things in exactly
the same way (excluding alignemnt differences).
v2: Use BIT(DRM_ROTATE_270) instead of ROTATE_270 when rotating
plane src coordinates
Drop some spurious changes that got left behind during
development
v3: Split out more changes to prep patches (Daniel)
s/intel_fb->plane[].foo.bar/intel_fb->foo[].bar/ for brevity
Rename intel_surf_gtt_offset to intel_fb_gtt_offset
Kill the pointless 'plane' parameter from intel_fb_gtt_offset()
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 51 ++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +-
drivers/gpu/drm/i915/intel_display.c | 376 +++++++++++++++++++++++------------
drivers/gpu/drm/i915/intel_drv.h | 19 +-
drivers/gpu/drm/i915/intel_sprite.c | 97 ++++-----
5 files changed, 331 insertions(+), 217 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index db80ec08cca4..56eda5d5ae0f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3359,16 +3359,14 @@ rotate_pages(const dma_addr_t *in, unsigned int offset,
}
static struct sg_table *
-intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
+intel_rotate_fb_obj_pages(const struct intel_rotation_info *rot_info,
struct drm_i915_gem_object *obj)
{
- unsigned int size_pages = rot_info->plane[0].width * rot_info->plane[0].height;
- unsigned int size_pages_uv;
+ unsigned int size = intel_rotation_info_size(rot_info);
struct sg_page_iter sg_iter;
unsigned long i;
dma_addr_t *page_addr_list;
struct sg_table *st;
- unsigned int uv_start_page;
struct scatterlist *sg;
int ret = -ENOMEM;
@@ -3378,18 +3376,12 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
if (!page_addr_list)
return ERR_PTR(ret);
- /* Account for UV plane with NV12. */
- if (rot_info->pixel_format == DRM_FORMAT_NV12)
- size_pages_uv = rot_info->plane[1].width * rot_info->plane[1].height;
- else
- size_pages_uv = 0;
-
/* Allocate target SG list. */
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (!st)
goto err_st_alloc;
- ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
+ ret = sg_alloc_table(st, size, GFP_KERNEL);
if (ret)
goto err_sg_alloc;
@@ -3403,32 +3395,14 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
st->nents = 0;
sg = st->sgl;
- /* Rotate the pages. */
- sg = rotate_pages(page_addr_list, 0,
- rot_info->plane[0].width, rot_info->plane[0].height,
- rot_info->plane[0].width,
- st, sg);
-
- /* Append the UV plane if NV12. */
- if (rot_info->pixel_format == DRM_FORMAT_NV12) {
- uv_start_page = size_pages;
-
- /* Check for tile-row un-alignment. */
- if (offset_in_page(rot_info->uv_offset))
- uv_start_page--;
-
- rot_info->uv_start_page = uv_start_page;
-
- sg = rotate_pages(page_addr_list, rot_info->uv_start_page,
- rot_info->plane[1].width, rot_info->plane[1].height,
- rot_info->plane[1].width,
- st, sg);
+ for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) {
+ sg = rotate_pages(page_addr_list, rot_info->plane[i].offset,
+ rot_info->plane[i].width, rot_info->plane[i].height,
+ rot_info->plane[i].stride, st, sg);
}
- DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
- obj->base.size, rot_info->plane[0].width,
- rot_info->plane[0].height, size_pages + size_pages_uv,
- size_pages);
+ DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n",
+ obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size);
drm_free_large(page_addr_list);
@@ -3439,10 +3413,9 @@ err_sg_alloc:
err_st_alloc:
drm_free_large(page_addr_list);
- DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n",
- obj->base.size, ret, rot_info->plane[0].width,
- rot_info->plane[0].height, size_pages + size_pages_uv,
- size_pages);
+ DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
+ obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size);
+
return ERR_PTR(ret);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 4b8a378b9d3f..39db46637395 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -135,12 +135,9 @@ enum i915_ggtt_view_type {
};
struct intel_rotation_info {
- unsigned int uv_offset;
- uint32_t pixel_format;
- unsigned int uv_start_page;
struct {
/* tiles */
- unsigned int width, height;
+ unsigned int width, height, stride, offset;
} plane[2];
};
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7ed33b5eb443..ef68892f4e0a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2315,33 +2315,6 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
}
}
-static void
-intel_fill_fb_info(struct drm_i915_private *dev_priv,
- struct drm_framebuffer *fb)
-{
- struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
- unsigned int tile_size, tile_width, tile_height, cpp;
-
- tile_size = intel_tile_size(dev_priv);
-
- cpp = drm_format_plane_cpp(fb->pixel_format, 0);
- intel_tile_dims(dev_priv, &tile_width, &tile_height,
- fb->modifier[0], cpp);
-
- info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
- info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
-
- if (info->pixel_format == DRM_FORMAT_NV12) {
- cpp = drm_format_plane_cpp(fb->pixel_format, 1);
- intel_tile_dims(dev_priv, &tile_width, &tile_height,
- fb->modifier[1], cpp);
-
- info->uv_offset = fb->offsets[1];
- info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
- info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
- }
-}
-
static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
{
if (INTEL_INFO(dev_priv)->gen >= 9)
@@ -2463,6 +2436,42 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation
}
/*
+ * Convert the x/y offsets into a linear offset.
+ * Only valid with 0/180 degree rotation, which is fine since linear
+ * offset is only used with linear buffers on pre-hsw and tiled buffers
+ * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
+ */
+unsigned int intel_fb_xy_to_linear(int x, int y,
+ const struct drm_framebuffer *fb, int plane)
+{
+ unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
+ unsigned int pitch = fb->pitches[plane];
+
+ return y * pitch + x * cpp;
+}
+
+/*
+ * Add the x/y offsets derived from fb->offsets[] to the user
+ * specified plane src x/y offsets. The resulting x/y offsets
+ * specify the start of scanout from the beginning of the gtt mapping.
+ */
+void intel_add_fb_offsets(int *x, int *y,
+ const struct drm_framebuffer *fb, int plane,
+ unsigned int rotation)
+
+{
+ const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+
+ if (intel_rotation_90_or_270(rotation)) {
+ *x += intel_fb->rotated[plane].x;
+ *y += intel_fb->rotated[plane].y;
+ } else {
+ *x += intel_fb->normal[plane].x;
+ *y += intel_fb->normal[plane].y;
+ }
+}
+
+/*
* Adjust the tile offset by moving the difference into
* the x/y offsets.
*
@@ -2498,20 +2507,23 @@ static void intel_adjust_tile_offset(int *x, int *y,
* In the 90/270 rotated case, x and y are assumed
* to be already rotated to match the rotated GTT view, and
* pitch is the tile_height aligned framebuffer height.
+ *
+ * This function is used when computing the derived information
+ * under intel_framebuffer, so using any of that information
+ * here is not allowed. Anything under drm_framebuffer can be
+ * used. This is why the user has to pass in the pitch since it
+ * is specified in the rotated orientation.
*/
-u32 intel_compute_tile_offset(int *x, int *y,
- const struct drm_framebuffer *fb, int plane,
- unsigned int pitch,
- unsigned int rotation)
+static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
+ int *x, int *y,
+ const struct drm_framebuffer *fb, int plane,
+ unsigned int pitch,
+ unsigned int rotation,
+ unsigned int alignment)
{
- const struct drm_i915_private *dev_priv = to_i915(fb->dev);
uint64_t fb_modifier = fb->modifier[plane];
unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
- unsigned int offset, alignment;
-
- alignment = intel_surf_alignment(dev_priv, fb_modifier);
- if (alignment)
- alignment--;
+ unsigned int offset;
if (fb_modifier != DRM_FORMAT_MOD_NONE) {
unsigned int tile_size, tile_width, tile_height;
@@ -2548,6 +2560,141 @@ u32 intel_compute_tile_offset(int *x, int *y,
return offset & ~alignment;
}
+unsigned int intel_compute_tile_offset(int *x, int *y,
+ const struct drm_framebuffer *fb, int plane,
+ unsigned int pitch,
+ unsigned int rotation)
+{
+ const struct drm_i915_private *dev_priv = to_i915(fb->dev);
+ unsigned int alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
+
+ return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
+ rotation, alignment ? (alignment - 1) : 0);
+}
+
+/* Convert the fb->offset[] linear offset into x/y offsets */
+static void intel_fb_offset_to_xy(int *x, int *y,
+ const struct drm_framebuffer *fb, int plane)
+{
+ unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
+ unsigned int pitch = fb->pitches[plane];
+ unsigned int linear_offset = fb->offsets[plane];
+
+ *y = linear_offset / pitch;
+ *x = linear_offset % pitch / cpp;
+}
+
+static int
+intel_fill_fb_info(struct drm_i915_private *dev_priv,
+ struct drm_framebuffer *fb)
+{
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ struct intel_rotation_info *rot_info = &intel_fb->rot_info;
+ unsigned int gtt_offset_rotated = 0;
+ unsigned int max_size = 0;
+ uint32_t format = fb->pixel_format;
+ int i, num_planes = drm_format_num_planes(format);
+ unsigned int tile_size = intel_tile_size(dev_priv);
+
+ for (i = 0; i < num_planes; i++) {
+ unsigned int width, height;
+ unsigned int cpp, offset, size;
+ int x, y;
+
+ cpp = drm_format_plane_cpp(format, i);
+ width = drm_format_plane_width(fb->width, format, i);
+ height = drm_format_plane_height(fb->height, format, i);
+
+ intel_fb_offset_to_xy(&x, &y, fb, i);
+
+ /*
+ * First pixel of the framebuffer from
+ * the start of the normal gtt mapping.
+ */
+ intel_fb->normal[i].x = x;
+ intel_fb->normal[i].y = y;
+
+ offset = _intel_compute_tile_offset(dev_priv, &x, &y,
+ fb, 0, fb->pitches[i],
+ BIT(DRM_ROTATE_0), tile_size);
+ offset /= tile_size;
+ DRM_DEBUG("offset %u tiles\n", offset);
+
+ if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
+ unsigned int tile_width, tile_height;
+ unsigned int pitch;
+ struct drm_rect r;
+
+ intel_tile_dims(dev_priv, &tile_width, &tile_height,
+ fb->modifier[i], cpp);
+
+ rot_info->plane[i].offset = offset;
+ rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
+ rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
+ rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
+
+ intel_fb->rotated[i].pitch =
+ rot_info->plane[i].height * tile_height;
+
+ /* how many tiles does this plane need */
+ size = rot_info->plane[i].stride * rot_info->plane[i].height;
+ /*
+ * If the plane isn't horizontally tile aligned,
+ * we need one more tile.
+ */
+ if (x != 0)
+ size++;
+
+ pitch = intel_fb->rotated[i].pitch;
+
+ /* rotate the x/y offsets to match the GTT view */
+ r.x1 = x;
+ r.y1 = y;
+ r.x2 = x + width;
+ r.y2 = y + height;
+ drm_rect_rotate(&r, width, pitch, BIT(DRM_ROTATE_270));
+ x = r.x1;
+ y = r.y1;
+
+ /* rotate the tile dimensions to match the GTT view */
+ swap(tile_width, tile_height);
+
+ /*
+ * We only keep the x/y offsets, so push all of the
+ * gtt offset into the x/y offsets.
+ */
+ intel_adjust_tile_offset(&x, &y, tile_size,
+ tile_width, tile_height, pitch,
+ gtt_offset_rotated * tile_size, 0);
+
+ gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
+
+ /*
+ * First pixel of the framebuffer from
+ * the start of the rotated gtt mapping.
+ */
+ intel_fb->rotated[i].x = x;
+ intel_fb->rotated[i].y = y;
+ } else {
+ size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
+ x * cpp, tile_size);
+ }
+ DRM_DEBUG("%d offset %u, size %u, stride %u, height %u\n",
+ i, offset, size, rot_info->plane[i].stride, rot_info->plane[i].height);
+
+ /* how many tiles in total needed in the bo */
+ max_size = max(max_size, offset + size);
+ }
+
+ if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
+ DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
+ max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int i9xx_format_to_fourcc(int format)
{
switch (format) {
@@ -2778,7 +2925,6 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
u32 dspcntr;
i915_reg_t reg = DSPCNTR(plane);
unsigned int rotation = plane_state->base.rotation;
- int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
int x = plane_state->src.x1 >> 16;
int y = plane_state->src.y1 >> 16;
@@ -2838,30 +2984,25 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
if (IS_G4X(dev))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
- linear_offset = y * fb->pitches[0] + x * cpp;
+ intel_add_fb_offsets(&x, &y, fb, 0, rotation);
- if (INTEL_INFO(dev)->gen >= 4) {
+ if (INTEL_INFO(dev)->gen >= 4)
intel_crtc->dspaddr_offset =
intel_compute_tile_offset(&x, &y, fb, 0,
fb->pitches[0], rotation);
- linear_offset -= intel_crtc->dspaddr_offset;
- } else {
- intel_crtc->dspaddr_offset = linear_offset;
- }
if (rotation == BIT(DRM_ROTATE_180)) {
dspcntr |= DISPPLANE_ROTATE_180;
x += (crtc_state->pipe_src_w - 1);
y += (crtc_state->pipe_src_h - 1);
-
- /* Finding the last pixel of the last line of the display
- data and adding to linear_offset*/
- linear_offset +=
- (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
- (crtc_state->pipe_src_w - 1) * cpp;
}
+ linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+
+ if (INTEL_INFO(dev)->gen < 4)
+ intel_crtc->dspaddr_offset = linear_offset;
+
intel_crtc->adjusted_x = x;
intel_crtc->adjusted_y = y;
@@ -2870,7 +3011,8 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
if (INTEL_INFO(dev)->gen >= 4) {
I915_WRITE(DSPSURF(plane),
- i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
+ intel_fb_gtt_offset(fb, rotation) +
+ intel_crtc->dspaddr_offset);
I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
I915_WRITE(DSPLINOFF(plane), linear_offset);
} else
@@ -2908,7 +3050,6 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
u32 dspcntr;
i915_reg_t reg = DSPCNTR(plane);
unsigned int rotation = plane_state->base.rotation;
- int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
int x = plane_state->src.x1 >> 16;
int y = plane_state->src.y1 >> 16;
@@ -2947,26 +3088,23 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
- linear_offset = y * fb->pitches[0] + x * cpp;
+ intel_add_fb_offsets(&x, &y, fb, 0, rotation);
+
intel_crtc->dspaddr_offset =
intel_compute_tile_offset(&x, &y, fb, 0,
fb->pitches[0], rotation);
- linear_offset -= intel_crtc->dspaddr_offset;
+
if (rotation == BIT(DRM_ROTATE_180)) {
dspcntr |= DISPPLANE_ROTATE_180;
if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
x += (crtc_state->pipe_src_w - 1);
y += (crtc_state->pipe_src_h - 1);
-
- /* Finding the last pixel of the last line of the display
- data and adding to linear_offset*/
- linear_offset +=
- (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
- (crtc_state->pipe_src_w - 1) * cpp;
}
}
+ linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+
intel_crtc->adjusted_x = x;
intel_crtc->adjusted_y = y;
@@ -2974,7 +3112,8 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
I915_WRITE(DSPSURF(plane),
- i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
+ intel_fb_gtt_offset(fb, rotation) +
+ intel_crtc->dspaddr_offset);
if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
} else {
@@ -2996,32 +3135,15 @@ u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
}
}
-u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
- struct drm_i915_gem_object *obj,
- unsigned int plane)
+u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
+ unsigned int rotation)
{
+ struct drm_i915_gem_object *obj = intel_fb_obj(fb);
struct i915_ggtt_view view;
- struct i915_vma *vma;
- u64 offset;
-
- intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
- intel_plane->base.state->rotation);
-
- vma = i915_gem_obj_to_ggtt_view(obj, &view);
- if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
- view.type))
- return -1;
-
- offset = vma->node.start;
- if (plane == 1) {
- offset += vma->ggtt_view.params.rotated.uv_start_page *
- PAGE_SIZE;
- }
-
- WARN_ON(upper_32_bits(offset));
+ intel_fill_fb_ggtt_view(&view, fb, rotation);
- return lower_32_bits(offset);
+ return i915_gem_obj_ggtt_offset_view(obj, &view);
}
static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
@@ -3140,12 +3262,9 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_framebuffer *fb = plane_state->base.fb;
- struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int pipe = intel_crtc->pipe;
u32 plane_ctl, stride_div, stride;
- u32 tile_height, plane_offset, plane_size;
unsigned int rotation = plane_state->base.rotation;
- int x_offset, y_offset;
u32 surf_addr;
int scaler_id = plane_state->scaler_id;
int src_x = plane_state->src.x1 >> 16;
@@ -3166,36 +3285,49 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
plane_ctl |= skl_plane_ctl_rotation(rotation);
- stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
- fb->pixel_format);
- surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
-
- WARN_ON(drm_rect_width(&plane_state->src) == 0);
-
if (intel_rotation_90_or_270(rotation)) {
+ struct drm_rect r = {
+ .x1 = src_x,
+ .x2 = src_x + src_w,
+ .y1 = src_y,
+ .y2 = src_y + src_h,
+ };
int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+
+ /* Rotate src coordinates to match rotated GTT view */
+ drm_rect_rotate(&r, fb->width, fb->height, BIT(DRM_ROTATE_270));
- /* stride = Surface height in tiles */
- tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
- stride = DIV_ROUND_UP(fb->height, tile_height);
- x_offset = stride * tile_height - src_y - src_h;
- y_offset = src_x;
- plane_size = (src_w - 1) << 16 | (src_h - 1);
+ src_x = r.x1;
+ src_y = r.y1;
+ src_w = drm_rect_width(&r);
+ src_h = drm_rect_height(&r);
+
+ stride_div = intel_tile_height(dev_priv, fb->modifier[0], cpp);
+ stride = intel_fb->rotated[0].pitch;
} else {
- stride = fb->pitches[0] / stride_div;
- x_offset = src_x;
- y_offset = src_y;
- plane_size = (src_h - 1) << 16 | (src_w - 1);
+ stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
+ fb->pixel_format);
+ stride = fb->pitches[0];
}
- plane_offset = y_offset << 16 | x_offset;
- intel_crtc->adjusted_x = x_offset;
- intel_crtc->adjusted_y = y_offset;
+ intel_add_fb_offsets(&src_x, &src_y, fb, 0, rotation);
+ surf_addr = intel_compute_tile_offset(&src_x, &src_y, fb, 0,
+ stride, rotation);
+
+ /* Sizes are 0 based */
+ src_w--;
+ src_h--;
+ dst_w--;
+ dst_h--;
+
+ intel_crtc->adjusted_x = src_x;
+ intel_crtc->adjusted_y = src_y;
I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
- I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
- I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
- I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
+ I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
+ I915_WRITE(PLANE_STRIDE(pipe, 0), stride / stride_div);
+ I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
if (scaler_id >= 0) {
uint32_t ps_ctrl = 0;
@@ -3212,7 +3344,8 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
}
- I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
+ I915_WRITE(PLANE_SURF(pipe, 0),
+ intel_fb_gtt_offset(fb, rotation) + surf_addr);
POSTING_READ(PLANE_SURF(pipe, 0));
}
@@ -11388,7 +11521,7 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
const enum pipe pipe = intel_crtc->pipe;
- u32 ctl, stride, tile_height;
+ u32 ctl, stride;
ctl = I915_READ(PLANE_CTL(pipe, 0));
ctl &= ~PLANE_CTL_TILED_MASK;
@@ -11413,9 +11546,11 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
* linear buffers or in number of tiles for tiled buffers.
*/
if (intel_rotation_90_or_270(rotation)) {
- /* stride = Surface height in tiles */
- tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
- stride = DIV_ROUND_UP(fb->height, tile_height);
+ int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+
+ stride = intel_fb->rotated[0].pitch /
+ intel_tile_height(dev_priv, fb->modifier[0], cpp);
} else {
stride = fb->pitches[0] /
intel_fb_stride_alignment(dev_priv, fb->modifier[0],
@@ -11740,8 +11875,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (ret)
goto cleanup_pending;
- work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
- obj, 0);
+ work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
work->gtt_offset += intel_crtc->dspaddr_offset;
if (mmio_flip) {
@@ -14774,7 +14908,6 @@ static int intel_framebuffer_init(struct drm_device *dev,
struct drm_i915_gem_object *obj)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- unsigned int aligned_height;
int ret;
u32 pitch_limit, stride_alignment;
@@ -14899,17 +15032,12 @@ static int intel_framebuffer_init(struct drm_device *dev,
if (mode_cmd->offsets[0] != 0)
return -EINVAL;
- aligned_height = intel_fb_align_height(dev, mode_cmd->height,
- mode_cmd->pixel_format,
- mode_cmd->modifier[0]);
- /* FIXME drm helper for size checks (especially planar formats)? */
- if (obj->base.size < aligned_height * mode_cmd->pitches[0])
- return -EINVAL;
-
drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
intel_fb->obj = obj;
- intel_fill_fb_info(dev_priv, &intel_fb->base);
+ ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
+ if (ret)
+ return ret;
ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
if (ret) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8a0f4dfd04a6..473b4cf9a2ff 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -119,6 +119,16 @@ struct intel_framebuffer {
struct drm_framebuffer base;
struct drm_i915_gem_object *obj;
struct intel_rotation_info rot_info;
+
+ /* for each plane in the normal GTT view */
+ struct {
+ unsigned int x, y;
+ } normal[2];
+ /* for each plane in the rotated GTT view */
+ struct {
+ unsigned int x, y;
+ unsigned int pitch; /* pixels */
+ } rotated[2];
};
struct intel_fbdev {
@@ -1060,6 +1070,11 @@ void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
/* intel_display.c */
extern const struct drm_plane_funcs intel_plane_funcs;
+unsigned int intel_fb_xy_to_linear(int x, int y,
+ const struct drm_framebuffer *fb, int plane);
+void intel_add_fb_offsets(int *x, int *y,
+ const struct drm_framebuffer *fb, int plane,
+ unsigned int rotation);
unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
bool intel_has_pending_fb_unpin(struct drm_device *dev);
int intel_pch_rawclk(struct drm_device *dev);
@@ -1217,9 +1232,7 @@ void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
-u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
- struct drm_i915_gem_object *obj,
- unsigned int plane);
+u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
u32 skl_plane_ctl_format(uint32_t pixel_format);
u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 8821533561b1..86176304155d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -186,15 +186,13 @@ skl_update_plane(struct drm_plane *drm_plane,
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane = to_intel_plane(drm_plane);
struct drm_framebuffer *fb = plane_state->base.fb;
- struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
const int pipe = intel_plane->pipe;
const int plane = intel_plane->plane + 1;
u32 plane_ctl, stride_div, stride;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 surf_addr;
- u32 tile_height, plane_offset, plane_size;
unsigned int rotation = plane_state->base.rotation;
- int x_offset, y_offset;
int crtc_x = plane_state->dst.x1;
int crtc_y = plane_state->dst.y1;
uint32_t crtc_w = drm_rect_width(&plane_state->dst);
@@ -215,15 +213,6 @@ skl_update_plane(struct drm_plane *drm_plane,
plane_ctl |= skl_plane_ctl_rotation(rotation);
- stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
- fb->pixel_format);
-
- /* Sizes are 0 based */
- src_w--;
- src_h--;
- crtc_w--;
- crtc_h--;
-
if (key->flags) {
I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
@@ -235,28 +224,44 @@ skl_update_plane(struct drm_plane *drm_plane,
else if (key->flags & I915_SET_COLORKEY_SOURCE)
plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
- surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
-
if (intel_rotation_90_or_270(rotation)) {
- int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
-
- /* stride: Surface height in tiles */
- tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
- stride = DIV_ROUND_UP(fb->height, tile_height);
- plane_size = (src_w << 16) | src_h;
- x_offset = stride * tile_height - y - (src_h + 1);
- y_offset = x;
+ struct drm_rect r = {
+ .x1 = x,
+ .x2 = x + src_w,
+ .y1 = y,
+ .y2 = y + src_h,
+ };
+ unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
+
+ /* Rotate src coordinates to match rotated GTT view */
+ drm_rect_rotate(&r, fb->width, fb->height, BIT(DRM_ROTATE_270));
+
+ x = r.x1;
+ y = r.y1;
+ src_w = drm_rect_width(&r);
+ src_h = drm_rect_height(&r);
+
+ stride_div = intel_tile_height(dev_priv, fb->modifier[0], cpp);
+ stride = intel_fb->rotated[0].pitch;
} else {
- stride = fb->pitches[0] / stride_div;
- plane_size = (src_h << 16) | src_w;
- x_offset = x;
- y_offset = y;
+ stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
+ fb->pixel_format);
+ stride = fb->pitches[0];
}
- plane_offset = y_offset << 16 | x_offset;
- I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
- I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
- I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
+ intel_add_fb_offsets(&x, &y, fb, 0, rotation);
+ surf_addr = intel_compute_tile_offset(&x, &y, fb, 0,
+ stride, rotation);
+
+ /* Sizes are 0 based */
+ src_w--;
+ src_h--;
+ crtc_w--;
+ crtc_h--;
+
+ I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
+ I915_WRITE(PLANE_STRIDE(pipe, plane), stride / stride_div);
+ I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w);
/* program plane scaler */
if (plane_state->scaler_id >= 0) {
@@ -278,7 +283,8 @@ skl_update_plane(struct drm_plane *drm_plane,
}
I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
- I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
+ I915_WRITE(PLANE_SURF(pipe, plane),
+ intel_fb_gtt_offset(fb, rotation) + surf_addr);
POSTING_READ(PLANE_SURF(pipe, plane));
}
@@ -351,7 +357,6 @@ vlv_update_plane(struct drm_plane *dplane,
u32 sprctl;
u32 sprsurf_offset, linear_offset;
unsigned int rotation = dplane->state->rotation;
- int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->dst.x1;
int crtc_y = plane_state->dst.y1;
@@ -422,19 +427,19 @@ vlv_update_plane(struct drm_plane *dplane,
crtc_w--;
crtc_h--;
- linear_offset = y * fb->pitches[0] + x * cpp;
+ intel_add_fb_offsets(&x, &y, fb, 0, rotation);
sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
fb->pitches[0], rotation);
- linear_offset -= sprsurf_offset;
if (rotation == BIT(DRM_ROTATE_180)) {
sprctl |= SP_ROTATE_180;
x += src_w;
y += src_h;
- linear_offset += src_h * fb->pitches[0] + src_w * cpp;
}
+ linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+
if (key->flags) {
I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
@@ -459,8 +464,8 @@ vlv_update_plane(struct drm_plane *dplane,
I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
I915_WRITE(SPCNTR(pipe, plane), sprctl);
- I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
- sprsurf_offset);
+ I915_WRITE(SPSURF(pipe, plane),
+ intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
POSTING_READ(SPSURF(pipe, plane));
}
@@ -493,7 +498,6 @@ ivb_update_plane(struct drm_plane *plane,
u32 sprctl, sprscale = 0;
u32 sprsurf_offset, linear_offset;
unsigned int rotation = plane_state->base.rotation;
- int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->dst.x1;
int crtc_y = plane_state->dst.y1;
@@ -555,10 +559,9 @@ ivb_update_plane(struct drm_plane *plane,
if (crtc_w != src_w || crtc_h != src_h)
sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
- linear_offset = y * fb->pitches[0] + x * cpp;
+ intel_add_fb_offsets(&x, &y, fb, 0, rotation);
sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
fb->pitches[0], rotation);
- linear_offset -= sprsurf_offset;
if (rotation == BIT(DRM_ROTATE_180)) {
sprctl |= SPRITE_ROTATE_180;
@@ -567,10 +570,11 @@ ivb_update_plane(struct drm_plane *plane,
if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
x += src_w;
y += src_h;
- linear_offset += src_h * fb->pitches[0] + src_w * cpp;
}
}
+ linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+
if (key->flags) {
I915_WRITE(SPRKEYVAL(pipe), key->min_value);
I915_WRITE(SPRKEYMAX(pipe), key->max_value);
@@ -599,7 +603,7 @@ ivb_update_plane(struct drm_plane *plane,
I915_WRITE(SPRSCALE(pipe), sprscale);
I915_WRITE(SPRCTL(pipe), sprctl);
I915_WRITE(SPRSURF(pipe),
- i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
+ intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
POSTING_READ(SPRSURF(pipe));
}
@@ -634,7 +638,6 @@ ilk_update_plane(struct drm_plane *plane,
u32 dvscntr, dvsscale;
u32 dvssurf_offset, linear_offset;
unsigned int rotation = plane_state->base.rotation;
- int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->dst.x1;
int crtc_y = plane_state->dst.y1;
@@ -692,19 +695,19 @@ ilk_update_plane(struct drm_plane *plane,
if (crtc_w != src_w || crtc_h != src_h)
dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
- linear_offset = y * fb->pitches[0] + x * cpp;
+ intel_add_fb_offsets(&x, &y, fb, 0, rotation);
dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
fb->pitches[0], rotation);
- linear_offset -= dvssurf_offset;
if (rotation == BIT(DRM_ROTATE_180)) {
dvscntr |= DVS_ROTATE_180;
x += src_w;
y += src_h;
- linear_offset += src_h * fb->pitches[0] + src_w * cpp;
}
+ linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+
if (key->flags) {
I915_WRITE(DVSKEYVAL(pipe), key->min_value);
I915_WRITE(DVSKEYMAX(pipe), key->max_value);
@@ -728,7 +731,7 @@ ilk_update_plane(struct drm_plane *plane,
I915_WRITE(DVSSCALE(pipe), dvsscale);
I915_WRITE(DVSCNTR(pipe), dvscntr);
I915_WRITE(DVSSURF(pipe),
- i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
+ intel_fb_gtt_offset(fb, rotation) + dvssurf_offset);
POSTING_READ(DVSSURF(pipe));
}
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 16/18] drm/i915: Don't pass pitch to intel_compute_page_offset()
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (14 preceding siblings ...)
2016-01-20 19:05 ` [PATCH v3 15/18] drm/i915: Rewrite fb rotation GTT handling ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-25 17:53 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH 17/18] drm/i915: Pass around plane_state instead of fb+rotation ville.syrjala
` (5 subsequent siblings)
21 siblings, 1 reply; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_compute_page_offset() can dig up the correct pitch from the fb
itself, no need for the caller to pass it in.
A bit of extra care is needed for the lower level
_intel_compute_page_offset() since that one gets called before the
rotated pitch under intel_fb is populated. Note that we don't actually
call it with anything but DRM_ROTATE_0 there so we wouldn't actually
look up the rotated pitch there, but still, leave the pitch as something
the caller has to pass to _intel_compute_page_offset() as an
indicator that something is a bit special.
This leaves 'stride_div' in the skl plane update hooks as a mostly useless
variable so just get rid of it.
v2: Add a note why stride_div got nuked
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++--------------
drivers/gpu/drm/i915/intel_drv.h | 1 -
drivers/gpu/drm/i915/intel_sprite.c | 26 +++++++++++---------------
3 files changed, 27 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ef68892f4e0a..eb8ce8a99291 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2562,11 +2562,16 @@ static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
unsigned int intel_compute_tile_offset(int *x, int *y,
const struct drm_framebuffer *fb, int plane,
- unsigned int pitch,
unsigned int rotation)
{
const struct drm_i915_private *dev_priv = to_i915(fb->dev);
unsigned int alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
+ unsigned int pitch;
+
+ if (intel_rotation_90_or_270(rotation))
+ pitch = to_intel_framebuffer(fb)->rotated[plane].pitch;
+ else
+ pitch = fb->pitches[plane];
return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
rotation, alignment ? (alignment - 1) : 0);
@@ -2988,8 +2993,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
if (INTEL_INFO(dev)->gen >= 4)
intel_crtc->dspaddr_offset =
- intel_compute_tile_offset(&x, &y, fb, 0,
- fb->pitches[0], rotation);
+ intel_compute_tile_offset(&x, &y, fb, 0, rotation);
if (rotation == BIT(DRM_ROTATE_180)) {
dspcntr |= DISPPLANE_ROTATE_180;
@@ -3091,8 +3095,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
intel_add_fb_offsets(&x, &y, fb, 0, rotation);
intel_crtc->dspaddr_offset =
- intel_compute_tile_offset(&x, &y, fb, 0,
- fb->pitches[0], rotation);
+ intel_compute_tile_offset(&x, &y, fb, 0, rotation);
if (rotation == BIT(DRM_ROTATE_180)) {
dspcntr |= DISPPLANE_ROTATE_180;
@@ -3263,7 +3266,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_framebuffer *fb = plane_state->base.fb;
int pipe = intel_crtc->pipe;
- u32 plane_ctl, stride_div, stride;
+ u32 plane_ctl, stride;
unsigned int rotation = plane_state->base.rotation;
u32 surf_addr;
int scaler_id = plane_state->scaler_id;
@@ -3303,17 +3306,16 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
src_w = drm_rect_width(&r);
src_h = drm_rect_height(&r);
- stride_div = intel_tile_height(dev_priv, fb->modifier[0], cpp);
- stride = intel_fb->rotated[0].pitch;
+ stride = intel_fb->rotated[0].pitch /
+ intel_tile_height(dev_priv, fb->modifier[0], cpp);
} else {
- stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
- fb->pixel_format);
- stride = fb->pitches[0];
+ stride = fb->pitches[0] /
+ intel_fb_stride_alignment(dev_priv, fb->modifier[0],
+ fb->pixel_format);
}
intel_add_fb_offsets(&src_x, &src_y, fb, 0, rotation);
- surf_addr = intel_compute_tile_offset(&src_x, &src_y, fb, 0,
- stride, rotation);
+ surf_addr = intel_compute_tile_offset(&src_x, &src_y, fb, 0, rotation);
/* Sizes are 0 based */
src_w--;
@@ -3326,7 +3328,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
- I915_WRITE(PLANE_STRIDE(pipe, 0), stride / stride_div);
+ I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
if (scaler_id >= 0) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 473b4cf9a2ff..e3de1fc3b04d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1190,7 +1190,6 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
u32 intel_compute_tile_offset(int *x, int *y,
const struct drm_framebuffer *fb, int plane,
- unsigned int pitch,
unsigned int rotation);
void intel_prepare_reset(struct drm_device *dev);
void intel_finish_reset(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 86176304155d..31be24f27207 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -189,7 +189,7 @@ skl_update_plane(struct drm_plane *drm_plane,
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
const int pipe = intel_plane->pipe;
const int plane = intel_plane->plane + 1;
- u32 plane_ctl, stride_div, stride;
+ u32 plane_ctl, stride;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 surf_addr;
unsigned int rotation = plane_state->base.rotation;
@@ -241,17 +241,16 @@ skl_update_plane(struct drm_plane *drm_plane,
src_w = drm_rect_width(&r);
src_h = drm_rect_height(&r);
- stride_div = intel_tile_height(dev_priv, fb->modifier[0], cpp);
- stride = intel_fb->rotated[0].pitch;
+ stride = intel_fb->rotated[0].pitch /
+ intel_tile_height(dev_priv, fb->modifier[0], cpp);
} else {
- stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
- fb->pixel_format);
- stride = fb->pitches[0];
+ stride = fb->pitches[0] /
+ intel_fb_stride_alignment(dev_priv, fb->modifier[0],
+ fb->pixel_format);
}
intel_add_fb_offsets(&x, &y, fb, 0, rotation);
- surf_addr = intel_compute_tile_offset(&x, &y, fb, 0,
- stride, rotation);
+ surf_addr = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
/* Sizes are 0 based */
src_w--;
@@ -260,7 +259,7 @@ skl_update_plane(struct drm_plane *drm_plane,
crtc_h--;
I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
- I915_WRITE(PLANE_STRIDE(pipe, plane), stride / stride_div);
+ I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w);
/* program plane scaler */
@@ -428,8 +427,7 @@ vlv_update_plane(struct drm_plane *dplane,
crtc_h--;
intel_add_fb_offsets(&x, &y, fb, 0, rotation);
- sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
- fb->pitches[0], rotation);
+ sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
if (rotation == BIT(DRM_ROTATE_180)) {
sprctl |= SP_ROTATE_180;
@@ -560,8 +558,7 @@ ivb_update_plane(struct drm_plane *plane,
sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
intel_add_fb_offsets(&x, &y, fb, 0, rotation);
- sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
- fb->pitches[0], rotation);
+ sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
if (rotation == BIT(DRM_ROTATE_180)) {
sprctl |= SPRITE_ROTATE_180;
@@ -696,8 +693,7 @@ ilk_update_plane(struct drm_plane *plane,
dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
intel_add_fb_offsets(&x, &y, fb, 0, rotation);
- dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
- fb->pitches[0], rotation);
+ dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
if (rotation == BIT(DRM_ROTATE_180)) {
dvscntr |= DVS_ROTATE_180;
--
2.4.10
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH 17/18] drm/i915: Pass around plane_state instead of fb+rotation
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (15 preceding siblings ...)
2016-01-20 19:05 ` [PATCH v2 16/18] drm/i915: Don't pass pitch to intel_compute_page_offset() ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-25 17:55 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH v2 18/18] drm/i915: Make sure fb offset is (macro)pixel aligned ville.syrjala
` (4 subsequent siblings)
21 siblings, 1 reply; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_compute_tile_offset() and intel_add_fb_offsets() get passed the fb
and the rotation. As both of those come from the plane state we can just
pass that in instead.
For extra consitency pass the plane state to intel_fb_xy_to_linear() as
well even though it only really needs the fb.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 35 ++++++++++++++++++++---------------
drivers/gpu/drm/i915/intel_drv.h | 9 ++++-----
drivers/gpu/drm/i915/intel_sprite.c | 22 +++++++++++-----------
3 files changed, 35 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index eb8ce8a99291..2e6cbf65b265 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2442,8 +2442,10 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation
* with gen2/3, and 90/270 degree rotations isn't supported on any of them.
*/
unsigned int intel_fb_xy_to_linear(int x, int y,
- const struct drm_framebuffer *fb, int plane)
+ const struct intel_plane_state *state,
+ int plane)
{
+ const struct drm_framebuffer *fb = state->base.fb;
unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
unsigned int pitch = fb->pitches[plane];
@@ -2456,11 +2458,12 @@ unsigned int intel_fb_xy_to_linear(int x, int y,
* specify the start of scanout from the beginning of the gtt mapping.
*/
void intel_add_fb_offsets(int *x, int *y,
- const struct drm_framebuffer *fb, int plane,
- unsigned int rotation)
+ const struct intel_plane_state *state,
+ int plane)
{
- const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
+ unsigned int rotation = state->base.rotation;
if (intel_rotation_90_or_270(rotation)) {
*x += intel_fb->rotated[plane].x;
@@ -2561,10 +2564,12 @@ static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
}
unsigned int intel_compute_tile_offset(int *x, int *y,
- const struct drm_framebuffer *fb, int plane,
- unsigned int rotation)
+ const struct intel_plane_state *state,
+ int plane)
{
- const struct drm_i915_private *dev_priv = to_i915(fb->dev);
+ const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
+ const struct drm_framebuffer *fb = state->base.fb;
+ unsigned int rotation = state->base.rotation;
unsigned int alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
unsigned int pitch;
@@ -2989,11 +2994,11 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
if (IS_G4X(dev))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
- intel_add_fb_offsets(&x, &y, fb, 0, rotation);
+ intel_add_fb_offsets(&x, &y, plane_state, 0);
if (INTEL_INFO(dev)->gen >= 4)
intel_crtc->dspaddr_offset =
- intel_compute_tile_offset(&x, &y, fb, 0, rotation);
+ intel_compute_tile_offset(&x, &y, plane_state, 0);
if (rotation == BIT(DRM_ROTATE_180)) {
dspcntr |= DISPPLANE_ROTATE_180;
@@ -3002,7 +3007,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
y += (crtc_state->pipe_src_h - 1);
}
- linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+ linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
if (INTEL_INFO(dev)->gen < 4)
intel_crtc->dspaddr_offset = linear_offset;
@@ -3092,10 +3097,10 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
- intel_add_fb_offsets(&x, &y, fb, 0, rotation);
+ intel_add_fb_offsets(&x, &y, plane_state, 0);
intel_crtc->dspaddr_offset =
- intel_compute_tile_offset(&x, &y, fb, 0, rotation);
+ intel_compute_tile_offset(&x, &y, plane_state, 0);
if (rotation == BIT(DRM_ROTATE_180)) {
dspcntr |= DISPPLANE_ROTATE_180;
@@ -3106,7 +3111,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
}
}
- linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+ linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
intel_crtc->adjusted_x = x;
intel_crtc->adjusted_y = y;
@@ -3314,8 +3319,8 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
fb->pixel_format);
}
- intel_add_fb_offsets(&src_x, &src_y, fb, 0, rotation);
- surf_addr = intel_compute_tile_offset(&src_x, &src_y, fb, 0, rotation);
+ intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
+ surf_addr = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
/* Sizes are 0 based */
src_w--;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e3de1fc3b04d..09cfc0eea5a4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1071,10 +1071,10 @@ void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
/* intel_display.c */
extern const struct drm_plane_funcs intel_plane_funcs;
unsigned int intel_fb_xy_to_linear(int x, int y,
- const struct drm_framebuffer *fb, int plane);
+ const struct intel_plane_state *state,
+ int plane);
void intel_add_fb_offsets(int *x, int *y,
- const struct drm_framebuffer *fb, int plane,
- unsigned int rotation);
+ const struct intel_plane_state *state, int plane);
unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
bool intel_has_pending_fb_unpin(struct drm_device *dev);
int intel_pch_rawclk(struct drm_device *dev);
@@ -1189,8 +1189,7 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
u32 intel_compute_tile_offset(int *x, int *y,
- const struct drm_framebuffer *fb, int plane,
- unsigned int rotation);
+ const struct intel_plane_state *state, int plane);
void intel_prepare_reset(struct drm_device *dev);
void intel_finish_reset(struct drm_device *dev);
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 31be24f27207..ad533cc2b5f5 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -249,8 +249,8 @@ skl_update_plane(struct drm_plane *drm_plane,
fb->pixel_format);
}
- intel_add_fb_offsets(&x, &y, fb, 0, rotation);
- surf_addr = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
+ intel_add_fb_offsets(&x, &y, plane_state, 0);
+ surf_addr = intel_compute_tile_offset(&x, &y, plane_state, 0);
/* Sizes are 0 based */
src_w--;
@@ -426,8 +426,8 @@ vlv_update_plane(struct drm_plane *dplane,
crtc_w--;
crtc_h--;
- intel_add_fb_offsets(&x, &y, fb, 0, rotation);
- sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
+ intel_add_fb_offsets(&x, &y, plane_state, 0);
+ sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
if (rotation == BIT(DRM_ROTATE_180)) {
sprctl |= SP_ROTATE_180;
@@ -436,7 +436,7 @@ vlv_update_plane(struct drm_plane *dplane,
y += src_h;
}
- linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+ linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
if (key->flags) {
I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
@@ -557,8 +557,8 @@ ivb_update_plane(struct drm_plane *plane,
if (crtc_w != src_w || crtc_h != src_h)
sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
- intel_add_fb_offsets(&x, &y, fb, 0, rotation);
- sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
+ intel_add_fb_offsets(&x, &y, plane_state, 0);
+ sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
if (rotation == BIT(DRM_ROTATE_180)) {
sprctl |= SPRITE_ROTATE_180;
@@ -570,7 +570,7 @@ ivb_update_plane(struct drm_plane *plane,
}
}
- linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+ linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
if (key->flags) {
I915_WRITE(SPRKEYVAL(pipe), key->min_value);
@@ -692,8 +692,8 @@ ilk_update_plane(struct drm_plane *plane,
if (crtc_w != src_w || crtc_h != src_h)
dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
- intel_add_fb_offsets(&x, &y, fb, 0, rotation);
- dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
+ intel_add_fb_offsets(&x, &y, plane_state, 0);
+ dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
if (rotation == BIT(DRM_ROTATE_180)) {
dvscntr |= DVS_ROTATE_180;
@@ -702,7 +702,7 @@ ilk_update_plane(struct drm_plane *plane,
y += src_h;
}
- linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+ linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
if (key->flags) {
I915_WRITE(DVSKEYVAL(pipe), key->min_value);
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 18/18] drm/i915: Make sure fb offset is (macro)pixel aligned
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (16 preceding siblings ...)
2016-01-20 19:05 ` [PATCH 17/18] drm/i915: Pass around plane_state instead of fb+rotation ville.syrjala
@ 2016-01-20 19:05 ` ville.syrjala
2016-01-21 13:35 ` ✓ Fi.CI.BAT: success for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) Patchwork
` (3 subsequent siblings)
21 siblings, 0 replies; 50+ messages in thread
From: ville.syrjala @ 2016-01-20 19:05 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We convert the fb->offsets[] into x/y offsets, so they must be
(macro)pixel aligned. Check for this, and if things look good
allow fb->offsets[] != 0 when creating fbs since we now handle
them correctly.
v2: Move to last place in the series and improve the commit message
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v1)
---
drivers/gpu/drm/i915/intel_display.c | 37 +++++++++++++++++++++++++++++++++---
1 file changed, 34 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2e6cbf65b265..0538846ad20d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14909,6 +14909,37 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
}
}
+static int intel_fb_check_offsets(const struct drm_mode_fb_cmd2 *mode_cmd)
+{
+ uint32_t format = mode_cmd->pixel_format;
+ int num_planes = drm_format_num_planes(format);
+ int i;
+
+ for (i = 0; i < num_planes; i++) {
+ unsigned int cpp;
+
+ switch (format) {
+ case DRM_FORMAT_YUYV:
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_VYUY:
+ cpp = 4;
+ break;
+ default:
+ cpp = drm_format_plane_cpp(format, i);
+ break;
+ }
+
+ if (mode_cmd->offsets[i] % cpp) {
+ DRM_DEBUG("fb plane %d offset 0x%08x not (macro)pixel aligned\n",
+ i, mode_cmd->offsets[i]);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
static int intel_framebuffer_init(struct drm_device *dev,
struct intel_framebuffer *intel_fb,
struct drm_mode_fb_cmd2 *mode_cmd,
@@ -15035,9 +15066,9 @@ static int intel_framebuffer_init(struct drm_device *dev,
return -EINVAL;
}
- /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
- if (mode_cmd->offsets[0] != 0)
- return -EINVAL;
+ ret = intel_fb_check_offsets(mode_cmd);
+ if (ret)
+ return ret;
drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
intel_fb->obj = obj;
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* Re: [PATCH 14/18] drm/i915: Embed rotation_info under intel_framebuffer
2016-01-20 19:05 ` [PATCH 14/18] drm/i915: Embed rotation_info under intel_framebuffer ville.syrjala
@ 2016-01-20 21:08 ` Chris Wilson
2016-01-21 12:06 ` Ville Syrjälä
2016-01-25 17:42 ` Daniel Vetter
1 sibling, 1 reply; 50+ messages in thread
From: Chris Wilson @ 2016-01-20 21:08 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:35PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Instead of repopulatin the rotation_info struct for the fb every time
> we try to use the fb, we can just populate it once when creating the fb,
> and later we can just copy the pre-populate struct into the gtt_view.
But the rotation state isn't tied to the fb, but to the plane+fb.
i.e. I can show the same fb on an unrotated pipe at the same time as
showing it rotated, right?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 14/18] drm/i915: Embed rotation_info under intel_framebuffer
2016-01-20 21:08 ` Chris Wilson
@ 2016-01-21 12:06 ` Ville Syrjälä
2016-01-21 12:10 ` Chris Wilson
0 siblings, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2016-01-21 12:06 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On Wed, Jan 20, 2016 at 09:08:50PM +0000, Chris Wilson wrote:
> On Wed, Jan 20, 2016 at 09:05:35PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Instead of repopulatin the rotation_info struct for the fb every time
> > we try to use the fb, we can just populate it once when creating the fb,
> > and later we can just copy the pre-populate struct into the gtt_view.
>
> But the rotation state isn't tied to the fb, but to the plane+fb.
> i.e. I can show the same fb on an unrotated pipe at the same time as
> showing it rotated, right?
Yep. The rotation info basically just tells us how we need to shuffle
the pages for this particular fb if we want to scan it out in the
90/270 degree orientation.
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 14/18] drm/i915: Embed rotation_info under intel_framebuffer
2016-01-21 12:06 ` Ville Syrjälä
@ 2016-01-21 12:10 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2016-01-21 12:10 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Jan 21, 2016 at 02:06:27PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 20, 2016 at 09:08:50PM +0000, Chris Wilson wrote:
> > On Wed, Jan 20, 2016 at 09:05:35PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Instead of repopulatin the rotation_info struct for the fb every time
> > > we try to use the fb, we can just populate it once when creating the fb,
> > > and later we can just copy the pre-populate struct into the gtt_view.
> >
> > But the rotation state isn't tied to the fb, but to the plane+fb.
> > i.e. I can show the same fb on an unrotated pipe at the same time as
> > showing it rotated, right?
>
> Yep. The rotation info basically just tells us how we need to shuffle
> the pages for this particular fb if we want to scan it out in the
> 90/270 degree orientation.
Ah, gotcha, thanks for the clarification.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2)
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (17 preceding siblings ...)
2016-01-20 19:05 ` [PATCH v2 18/18] drm/i915: Make sure fb offset is (macro)pixel aligned ville.syrjala
@ 2016-01-21 13:35 ` Patchwork
2016-01-30 8:31 ` ✗ Fi.CI.BAT: failure for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) (rev2) Patchwork
` (2 subsequent siblings)
21 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2016-01-21 13:35 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Summary ==
Built on 8fe9e785ae04fa7c37f7935cff12d62e38054b60 drm-intel-nightly: 2016y-01m-21d-11h-02m-42s UTC integration manifest
bdw-nuci7 total:140 pass:131 dwarn:0 dfail:0 fail:0 skip:9
bdw-ultra total:143 pass:137 dwarn:0 dfail:0 fail:0 skip:6
bsw-nuc-2 total:143 pass:119 dwarn:0 dfail:0 fail:0 skip:24
byt-nuc total:143 pass:128 dwarn:0 dfail:0 fail:0 skip:15
hsw-brixbox total:143 pass:136 dwarn:0 dfail:0 fail:0 skip:7
hsw-gt2 total:143 pass:139 dwarn:0 dfail:0 fail:0 skip:4
ilk-hp8440p total:143 pass:104 dwarn:1 dfail:0 fail:0 skip:38
ivb-t430s total:143 pass:137 dwarn:0 dfail:0 fail:0 skip:6
skl-i5k-2 total:143 pass:134 dwarn:1 dfail:0 fail:0 skip:8
skl-i7k-2 total:143 pass:134 dwarn:1 dfail:0 fail:0 skip:8
snb-dellxps total:143 pass:129 dwarn:0 dfail:0 fail:0 skip:14
snb-x220t total:143 pass:129 dwarn:0 dfail:0 fail:1 skip:13
Results at /archive/results/CI_IGT_test/Patchwork_1235/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 01/18] drm/i915: Rename the rotated gtt view member to 'rotated'
2016-01-20 19:05 ` [PATCH 01/18] drm/i915: Rename the rotated gtt view member to 'rotated' ville.syrjala
@ 2016-01-25 16:50 ` Daniel Vetter
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 16:50 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:22PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Also rename 'rotation_info' to 'rotated' to match the view type exactly,
> this should avoid confusion which union members is valid for each view
> type.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Assuming gcc is happy: Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
> drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 4 ++--
> 3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 7377b6725c33..a3ea6b15c762 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3366,7 +3366,7 @@ static struct sg_table *
> intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
> struct drm_i915_gem_object *obj)
> {
> - struct intel_rotation_info *rot_info = &ggtt_view->params.rotation_info;
> + struct intel_rotation_info *rot_info = &ggtt_view->params.rotated;
> unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
> unsigned int size_pages_uv;
> struct sg_page_iter sg_iter;
> @@ -3598,7 +3598,7 @@ i915_ggtt_view_size(struct drm_i915_gem_object *obj,
> if (view->type == I915_GGTT_VIEW_NORMAL) {
> return obj->base.size;
> } else if (view->type == I915_GGTT_VIEW_ROTATED) {
> - return view->params.rotation_info.size;
> + return view->params.rotated.size;
> } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
> return view->params.partial.size << PAGE_SHIFT;
> } else {
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index e5737963ab79..f520c90e5377 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -155,7 +155,7 @@ struct i915_ggtt_view {
> u64 offset;
> unsigned int size;
> } partial;
> - struct intel_rotation_info rotation_info;
> + struct intel_rotation_info rotated;
> } params;
>
> struct sg_table *pages;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 06ab6df8ad48..5f8e3f7abca1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2284,7 +2284,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
> const struct drm_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(fb->dev);
> - struct intel_rotation_info *info = &view->params.rotation_info;
> + struct intel_rotation_info *info = &view->params.rotated;
> unsigned int tile_size, tile_width, tile_height, cpp;
>
> *view = i915_ggtt_view_normal;
> @@ -2951,7 +2951,7 @@ u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
> offset = vma->node.start;
>
> if (plane == 1) {
> - offset += vma->ggtt_view.params.rotation_info.uv_start_page *
> + offset += vma->ggtt_view.params.rotated.uv_start_page *
> PAGE_SIZE;
> }
>
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 02/18] drm/i915: Pass stride to rotate_pages()
2016-01-20 19:05 ` [PATCH 02/18] drm/i915: Pass stride to rotate_pages() ville.syrjala
@ 2016-01-25 16:52 ` Daniel Vetter
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 16:52 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:23PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pass stride in addition to width and height to rotate_pages(). For now
> width and stride are the same, but once framebuffer offsets enter the
> scene that may no longer be the case.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index a3ea6b15c762..d547eecac242 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3333,6 +3333,7 @@ i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
> static struct scatterlist *
> rotate_pages(const dma_addr_t *in, unsigned int offset,
> unsigned int width, unsigned int height,
> + unsigned int stride,
> struct sg_table *st, struct scatterlist *sg)
> {
> unsigned int column, row;
> @@ -3344,7 +3345,7 @@ rotate_pages(const dma_addr_t *in, unsigned int offset,
> }
>
> for (column = 0; column < width; column++) {
> - src_idx = width * (height - 1) + column;
> + src_idx = stride * (height - 1) + column;
> for (row = 0; row < height; row++) {
> st->nents++;
> /* We don't need the pages, but need to initialize
> @@ -3355,7 +3356,7 @@ rotate_pages(const dma_addr_t *in, unsigned int offset,
> sg_dma_address(sg) = in[offset + src_idx];
> sg_dma_len(sg) = PAGE_SIZE;
> sg = sg_next(sg);
> - src_idx -= width;
> + src_idx -= stride;
> }
> }
>
> @@ -3408,6 +3409,7 @@ intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
> /* Rotate the pages. */
> sg = rotate_pages(page_addr_list, 0,
> rot_info->width_pages, rot_info->height_pages,
> + rot_info->width_pages,
> st, NULL);
>
> /* Append the UV plane if NV12. */
> @@ -3423,6 +3425,7 @@ intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
> rotate_pages(page_addr_list, uv_start_page,
> rot_info->width_pages_uv,
> rot_info->height_pages_uv,
> + rot_info->width_pages_uv,
> st, sg);
> }
>
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 03/18] drm/i915: Pass rotation_info to intel_rotate_fb_obj_pages()
2016-01-20 19:05 ` [PATCH 03/18] drm/i915: Pass rotation_info to intel_rotate_fb_obj_pages() ville.syrjala
@ 2016-01-25 16:53 ` Daniel Vetter
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 16:53 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:24PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_rotate_fb_obj_pages() doens't need the entire gtt view, just the
> rotation info suffices.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d547eecac242..b3d8e2b0948c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3364,10 +3364,9 @@ rotate_pages(const dma_addr_t *in, unsigned int offset,
> }
>
> static struct sg_table *
> -intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
> +intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
> struct drm_i915_gem_object *obj)
> {
> - struct intel_rotation_info *rot_info = &ggtt_view->params.rotated;
> unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
> unsigned int size_pages_uv;
> struct sg_page_iter sg_iter;
> @@ -3507,7 +3506,7 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma)
> vma->ggtt_view.pages = vma->obj->pages;
> else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
> vma->ggtt_view.pages =
> - intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
> + intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj);
> else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
> vma->ggtt_view.pages =
> intel_partial_pages(&vma->ggtt_view, vma->obj);
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 04/18] drm/i915: Make display gtt offsets u32
2016-01-20 19:05 ` [PATCH 04/18] drm/i915: Make display gtt offsets u32 ville.syrjala
@ 2016-01-25 17:00 ` Daniel Vetter
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 17:00 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:25PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Using 'unsigned long' for ggtt offsets doesn't make much sense. Use
> 'u32' instead since we've not yet seen a >4GiB ggtt.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
I hunted down every occurenve of _offset in intel_display.c and
intel_sprite.c and could indeed not find any other worthy of conversion.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++------------
> drivers/gpu/drm/i915/intel_drv.h | 12 ++++++------
> drivers/gpu/drm/i915/intel_sprite.c | 6 +++---
> 3 files changed, 19 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5f8e3f7abca1..0f5df7a66cc4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2448,11 +2448,11 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
>
> /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
> * is assumed to be a power-of-two. */
> -unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> - int *x, int *y,
> - uint64_t fb_modifier,
> - unsigned int cpp,
> - unsigned int pitch)
> +u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> + int *x, int *y,
> + uint64_t fb_modifier,
> + unsigned int cpp,
> + unsigned int pitch)
> {
> if (fb_modifier != DRM_FORMAT_MOD_NONE) {
> unsigned int tile_size, tile_width, tile_height;
> @@ -2706,14 +2706,12 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> struct drm_framebuffer *fb = plane_state->base.fb;
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> int plane = intel_crtc->plane;
> - unsigned long linear_offset;
> - int x = plane_state->src.x1 >> 16;
> - int y = plane_state->src.y1 >> 16;
> + u32 linear_offset;
> u32 dspcntr;
> i915_reg_t reg = DSPCNTR(plane);
> - int pixel_size;
> -
> - pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> + int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> + int x = plane_state->src.x1 >> 16;
> + int y = plane_state->src.y1 >> 16;
>
> dspcntr = DISPPLANE_GAMMA_ENABLE;
>
> @@ -2839,7 +2837,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> struct drm_framebuffer *fb = plane_state->base.fb;
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> int plane = intel_crtc->plane;
> - unsigned long linear_offset;
> + u32 linear_offset;
> u32 dspcntr;
> i915_reg_t reg = DSPCNTR(plane);
> int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index bc970125ec76..f620023ed134 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -575,7 +575,7 @@ struct intel_crtc {
> /* Display surface base address adjustement for pageflips. Note that on
> * gen4+ this only adjusts up to a tile, offsets within a tile are
> * handled in the hw itself (with the TILEOFF register). */
> - unsigned long dspaddr_offset;
> + u32 dspaddr_offset;
> int adjusted_x;
> int adjusted_y;
>
> @@ -1172,11 +1172,11 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
> void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
> #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
> #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
> -unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> - int *x, int *y,
> - uint64_t fb_modifier,
> - unsigned int cpp,
> - unsigned int pitch);
> +u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> + int *x, int *y,
> + uint64_t fb_modifier,
> + unsigned int cpp,
> + unsigned int pitch);
> void intel_prepare_reset(struct drm_device *dev);
> void intel_finish_reset(struct drm_device *dev);
> void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 0875c8e0ec0a..f1ee7db0811a 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -350,7 +350,7 @@ vlv_update_plane(struct drm_plane *dplane,
> int pipe = intel_plane->pipe;
> int plane = intel_plane->plane;
> u32 sprctl;
> - unsigned long sprsurf_offset, linear_offset;
> + u32 sprsurf_offset, linear_offset;
> int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> int crtc_x = plane_state->dst.x1;
> @@ -493,7 +493,7 @@ ivb_update_plane(struct drm_plane *plane,
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> enum pipe pipe = intel_plane->pipe;
> u32 sprctl, sprscale = 0;
> - unsigned long sprsurf_offset, linear_offset;
> + u32 sprsurf_offset, linear_offset;
> int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> int crtc_x = plane_state->dst.x1;
> @@ -635,8 +635,8 @@ ilk_update_plane(struct drm_plane *plane,
> struct drm_framebuffer *fb = plane_state->base.fb;
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> int pipe = intel_plane->pipe;
> - unsigned long dvssurf_offset, linear_offset;
> u32 dvscntr, dvsscale;
> + u32 dvssurf_offset, linear_offset;
> int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> int crtc_x = plane_state->dst.x1;
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 05/18] drm/i915: Standardize on 'cpp' for bytes per pixel
2016-01-20 19:05 ` [PATCH 05/18] drm/i915: Standardize on 'cpp' for bytes per pixel ville.syrjala
@ 2016-01-25 17:05 ` Daniel Vetter
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 17:05 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:26PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We more or less randomly call the "bytes per pixel" value
> 'cpp', 'bytes_per_pixel', 'pixel_size', or even 'bpp'. Let's just pick
> one and stick to it. I've chosen 'cpp'.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Concurred on the cpp bikeshed, and reviewed all the changes in this patch.
I didn't apply&check that you caught them all though this time around.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_display.c | 22 +++---
> drivers/gpu/drm/i915/intel_pm.c | 128 +++++++++++++++++------------------
> drivers/gpu/drm/i915/intel_sprite.c | 34 ++++------
> 3 files changed, 87 insertions(+), 97 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0f5df7a66cc4..f94ddad704b2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2709,7 +2709,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> u32 linear_offset;
> u32 dspcntr;
> i915_reg_t reg = DSPCNTR(plane);
> - int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> + int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> int x = plane_state->src.x1 >> 16;
> int y = plane_state->src.y1 >> 16;
>
> @@ -2769,13 +2769,12 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> if (IS_G4X(dev))
> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>
> - linear_offset = y * fb->pitches[0] + x * pixel_size;
> + linear_offset = y * fb->pitches[0] + x * cpp;
>
> if (INTEL_INFO(dev)->gen >= 4) {
> intel_crtc->dspaddr_offset =
> intel_compute_tile_offset(dev_priv, &x, &y,
> - fb->modifier[0],
> - pixel_size,
> + fb->modifier[0], cpp,
> fb->pitches[0]);
> linear_offset -= intel_crtc->dspaddr_offset;
> } else {
> @@ -2792,7 +2791,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> data and adding to linear_offset*/
> linear_offset +=
> (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
> - (crtc_state->pipe_src_w - 1) * pixel_size;
> + (crtc_state->pipe_src_w - 1) * cpp;
> }
>
> intel_crtc->adjusted_x = x;
> @@ -2840,7 +2839,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> u32 linear_offset;
> u32 dspcntr;
> i915_reg_t reg = DSPCNTR(plane);
> - int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> + int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> int x = plane_state->src.x1 >> 16;
> int y = plane_state->src.y1 >> 16;
>
> @@ -2879,11 +2878,10 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>
> - linear_offset = y * fb->pitches[0] + x * pixel_size;
> + linear_offset = y * fb->pitches[0] + x * cpp;
> intel_crtc->dspaddr_offset =
> intel_compute_tile_offset(dev_priv, &x, &y,
> - fb->modifier[0],
> - pixel_size,
> + fb->modifier[0], cpp,
> fb->pitches[0]);
> linear_offset -= intel_crtc->dspaddr_offset;
> if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> @@ -2897,7 +2895,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> data and adding to linear_offset*/
> linear_offset +=
> (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
> - (crtc_state->pipe_src_w - 1) * pixel_size;
> + (crtc_state->pipe_src_w - 1) * cpp;
> }
> }
>
> @@ -14680,10 +14678,12 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
> u32 gen = INTEL_INFO(dev)->gen;
>
> if (gen >= 9) {
> + int cpp = drm_format_plane_cpp(pixel_format, 0);
> +
> /* "The stride in bytes must not exceed the of the size of 8K
> * pixels and 32K bytes."
> */
> - return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
> + return min(8192 * cpp, 32768);
> } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
> return 32*1024;
> } else if (gen >= 4) {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 20bf854eae8c..31bc4ea395ac 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -548,7 +548,7 @@ static const struct intel_watermark_params i845_wm_info = {
> * intel_calculate_wm - calculate watermark level
> * @clock_in_khz: pixel clock
> * @wm: chip FIFO params
> - * @pixel_size: display pixel size
> + * @cpp: bytes per pixel
> * @latency_ns: memory latency for the platform
> *
> * Calculate the watermark level (the level at which the display plane will
> @@ -564,8 +564,7 @@ static const struct intel_watermark_params i845_wm_info = {
> */
> static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
> const struct intel_watermark_params *wm,
> - int fifo_size,
> - int pixel_size,
> + int fifo_size, int cpp,
> unsigned long latency_ns)
> {
> long entries_required, wm_size;
> @@ -576,7 +575,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
> * clocks go from a few thousand to several hundred thousand.
> * latency is usually a few thousand
> */
> - entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
> + entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
> 1000;
> entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
>
> @@ -640,13 +639,13 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
> crtc = single_enabled_crtc(dev);
> if (crtc) {
> const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
> - int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
> + int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
> int clock = adjusted_mode->crtc_clock;
>
> /* Display SR */
> wm = intel_calculate_wm(clock, &pineview_display_wm,
> pineview_display_wm.fifo_size,
> - pixel_size, latency->display_sr);
> + cpp, latency->display_sr);
> reg = I915_READ(DSPFW1);
> reg &= ~DSPFW_SR_MASK;
> reg |= FW_WM(wm, SR);
> @@ -656,7 +655,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
> /* cursor SR */
> wm = intel_calculate_wm(clock, &pineview_cursor_wm,
> pineview_display_wm.fifo_size,
> - pixel_size, latency->cursor_sr);
> + cpp, latency->cursor_sr);
> reg = I915_READ(DSPFW3);
> reg &= ~DSPFW_CURSOR_SR_MASK;
> reg |= FW_WM(wm, CURSOR_SR);
> @@ -665,7 +664,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
> /* Display HPLL off SR */
> wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
> pineview_display_hplloff_wm.fifo_size,
> - pixel_size, latency->display_hpll_disable);
> + cpp, latency->display_hpll_disable);
> reg = I915_READ(DSPFW3);
> reg &= ~DSPFW_HPLL_SR_MASK;
> reg |= FW_WM(wm, HPLL_SR);
> @@ -674,7 +673,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
> /* cursor HPLL off SR */
> wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
> pineview_display_hplloff_wm.fifo_size,
> - pixel_size, latency->cursor_hpll_disable);
> + cpp, latency->cursor_hpll_disable);
> reg = I915_READ(DSPFW3);
> reg &= ~DSPFW_HPLL_CURSOR_MASK;
> reg |= FW_WM(wm, HPLL_CURSOR);
> @@ -698,7 +697,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
> {
> struct drm_crtc *crtc;
> const struct drm_display_mode *adjusted_mode;
> - int htotal, hdisplay, clock, pixel_size;
> + int htotal, hdisplay, clock, cpp;
> int line_time_us, line_count;
> int entries, tlb_miss;
>
> @@ -713,10 +712,10 @@ static bool g4x_compute_wm0(struct drm_device *dev,
> clock = adjusted_mode->crtc_clock;
> htotal = adjusted_mode->crtc_htotal;
> hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
> - pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
> + cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
>
> /* Use the small buffer method to calculate plane watermark */
> - entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
> + entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
> tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
> if (tlb_miss > 0)
> entries += tlb_miss;
> @@ -728,7 +727,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
> /* Use the large buffer method to calculate cursor watermark */
> line_time_us = max(htotal * 1000 / clock, 1);
> line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
> - entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
> + entries = line_count * crtc->cursor->state->crtc_w * cpp;
> tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
> if (tlb_miss > 0)
> entries += tlb_miss;
> @@ -784,7 +783,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
> {
> struct drm_crtc *crtc;
> const struct drm_display_mode *adjusted_mode;
> - int hdisplay, htotal, pixel_size, clock;
> + int hdisplay, htotal, cpp, clock;
> unsigned long line_time_us;
> int line_count, line_size;
> int small, large;
> @@ -800,21 +799,21 @@ static bool g4x_compute_srwm(struct drm_device *dev,
> clock = adjusted_mode->crtc_clock;
> htotal = adjusted_mode->crtc_htotal;
> hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
> - pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
> + cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
>
> line_time_us = max(htotal * 1000 / clock, 1);
> line_count = (latency_ns / line_time_us + 1000) / 1000;
> - line_size = hdisplay * pixel_size;
> + line_size = hdisplay * cpp;
>
> /* Use the minimum of the small and large buffer method for primary */
> - small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
> + small = ((clock * cpp / 1000) * latency_ns) / 1000;
> large = line_count * line_size;
>
> entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
> *display_wm = entries + display->guard_size;
>
> /* calculate the self-refresh watermark for display cursor */
> - entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
> + entries = line_count * cpp * crtc->cursor->state->crtc_w;
> entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
> *cursor_wm = entries + cursor->guard_size;
>
> @@ -906,13 +905,13 @@ enum vlv_wm_level {
> static unsigned int vlv_wm_method2(unsigned int pixel_rate,
> unsigned int pipe_htotal,
> unsigned int horiz_pixels,
> - unsigned int bytes_per_pixel,
> + unsigned int cpp,
> unsigned int latency)
> {
> unsigned int ret;
>
> ret = (latency * pixel_rate) / (pipe_htotal * 10000);
> - ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
> + ret = (ret + 1) * horiz_pixels * cpp;
> ret = DIV_ROUND_UP(ret, 64);
>
> return ret;
> @@ -941,7 +940,7 @@ static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
> int level)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> - int clock, htotal, pixel_size, width, wm;
> + int clock, htotal, cpp, width, wm;
>
> if (dev_priv->wm.pri_latency[level] == 0)
> return USHRT_MAX;
> @@ -949,7 +948,7 @@ static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
> if (!state->visible)
> return 0;
>
> - pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
> + cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
> clock = crtc->config->base.adjusted_mode.crtc_clock;
> htotal = crtc->config->base.adjusted_mode.crtc_htotal;
> width = crtc->config->pipe_src_w;
> @@ -965,7 +964,7 @@ static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
> */
> wm = 63;
> } else {
> - wm = vlv_wm_method2(clock, htotal, width, pixel_size,
> + wm = vlv_wm_method2(clock, htotal, width, cpp,
> dev_priv->wm.pri_latency[level] * 10);
> }
>
> @@ -1439,7 +1438,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
> int clock = adjusted_mode->crtc_clock;
> int htotal = adjusted_mode->crtc_htotal;
> int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
> - int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
> + int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
> unsigned long line_time_us;
> int entries;
>
> @@ -1447,7 +1446,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
>
> /* Use ns/us then divide to preserve precision */
> entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
> - pixel_size * hdisplay;
> + cpp * hdisplay;
> entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
> srwm = I965_FIFO_SIZE - entries;
> if (srwm < 0)
> @@ -1457,7 +1456,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
> entries, srwm);
>
> entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
> - pixel_size * crtc->cursor->state->crtc_w;
> + cpp * crtc->cursor->state->crtc_w;
> entries = DIV_ROUND_UP(entries,
> i965_cursor_wm_info.cacheline_size);
> cursor_sr = i965_cursor_wm_info.fifo_size -
> @@ -1518,7 +1517,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> crtc = intel_get_crtc_for_plane(dev, 0);
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *adjusted_mode;
> - int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
> + int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
> if (IS_GEN2(dev))
> cpp = 4;
>
> @@ -1540,7 +1539,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> crtc = intel_get_crtc_for_plane(dev, 1);
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *adjusted_mode;
> - int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
> + int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
> if (IS_GEN2(dev))
> cpp = 4;
>
> @@ -1586,7 +1585,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> int clock = adjusted_mode->crtc_clock;
> int htotal = adjusted_mode->crtc_htotal;
> int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
> - int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
> + int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
> unsigned long line_time_us;
> int entries;
>
> @@ -1594,7 +1593,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
>
> /* Use ns/us then divide to preserve precision */
> entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
> - pixel_size * hdisplay;
> + cpp * hdisplay;
> entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
> DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
> srwm = wm_info->fifo_size - entries;
> @@ -1685,15 +1684,14 @@ uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
> }
>
> /* latency must be in 0.1us units. */
> -static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
> - uint32_t latency)
> +static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
> {
> uint64_t ret;
>
> if (WARN(latency == 0, "Latency value missing\n"))
> return UINT_MAX;
>
> - ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
> + ret = (uint64_t) pixel_rate * cpp * latency;
> ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
>
> return ret;
> @@ -1701,7 +1699,7 @@ static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
>
> /* latency must be in 0.1us units. */
> static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
> - uint32_t horiz_pixels, uint8_t bytes_per_pixel,
> + uint32_t horiz_pixels, uint8_t cpp,
> uint32_t latency)
> {
> uint32_t ret;
> @@ -1712,13 +1710,13 @@ static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
> return UINT_MAX;
>
> ret = (latency * pixel_rate) / (pipe_htotal * 10000);
> - ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
> + ret = (ret + 1) * horiz_pixels * cpp;
> ret = DIV_ROUND_UP(ret, 64) + 2;
> return ret;
> }
>
> static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
> - uint8_t bytes_per_pixel)
> + uint8_t cpp)
> {
> /*
> * Neither of these should be possible since this function shouldn't be
> @@ -1726,12 +1724,12 @@ static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
> * extra paranoid to avoid a potential divide-by-zero if we screw up
> * elsewhere in the driver.
> */
> - if (WARN_ON(!bytes_per_pixel))
> + if (WARN_ON(!cpp))
> return 0;
> if (WARN_ON(!horiz_pixels))
> return 0;
>
> - return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
> + return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
> }
>
> struct ilk_wm_maximums {
> @@ -1750,13 +1748,14 @@ static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
> uint32_t mem_value,
> bool is_lp)
> {
> - int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
> + int cpp = pstate->base.fb ?
> + drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
> uint32_t method1, method2;
>
> if (!cstate->base.active || !pstate->visible)
> return 0;
>
> - method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
> + method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
>
> if (!is_lp)
> return method1;
> @@ -1764,8 +1763,7 @@ static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
> method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
> cstate->base.adjusted_mode.crtc_htotal,
> drm_rect_width(&pstate->dst),
> - bpp,
> - mem_value);
> + cpp, mem_value);
>
> return min(method1, method2);
> }
> @@ -1778,18 +1776,18 @@ static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
> const struct intel_plane_state *pstate,
> uint32_t mem_value)
> {
> - int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
> + int cpp = pstate->base.fb ?
> + drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
> uint32_t method1, method2;
>
> if (!cstate->base.active || !pstate->visible)
> return 0;
>
> - method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
> + method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
> method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
> cstate->base.adjusted_mode.crtc_htotal,
> drm_rect_width(&pstate->dst),
> - bpp,
> - mem_value);
> + cpp, mem_value);
> return min(method1, method2);
> }
>
> @@ -1801,7 +1799,8 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
> const struct intel_plane_state *pstate,
> uint32_t mem_value)
> {
> - int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
> + int cpp = pstate->base.fb ?
> + drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
>
> if (!cstate->base.active || !pstate->visible)
> return 0;
> @@ -1809,8 +1808,7 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
> return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
> cstate->base.adjusted_mode.crtc_htotal,
> drm_rect_width(&pstate->dst),
> - bpp,
> - mem_value);
> + cpp, mem_value);
> }
>
> /* Only for WM_LP. */
> @@ -1818,12 +1816,13 @@ static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
> const struct intel_plane_state *pstate,
> uint32_t pri_val)
> {
> - int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
> + int cpp = pstate->base.fb ?
> + drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
>
> if (!cstate->base.active || !pstate->visible)
> return 0;
>
> - return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
> + return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
> }
>
> static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
> @@ -3042,26 +3041,25 @@ static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
>
> /*
> * The max latency should be 257 (max the punit can code is 255 and we add 2us
> - * for the read latency) and bytes_per_pixel should always be <= 8, so that
> + * for the read latency) and cpp should always be <= 8, so that
> * should allow pixel_rate up to ~2 GHz which seems sufficient since max
> * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
> */
> -static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
> - uint32_t latency)
> +static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
> {
> uint32_t wm_intermediate_val, ret;
>
> if (latency == 0)
> return UINT_MAX;
>
> - wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
> + wm_intermediate_val = latency * pixel_rate * cpp / 512;
> ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
>
> return ret;
> }
>
> static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
> - uint32_t horiz_pixels, uint8_t bytes_per_pixel,
> + uint32_t horiz_pixels, uint8_t cpp,
> uint64_t tiling, uint32_t latency)
> {
> uint32_t ret;
> @@ -3071,7 +3069,7 @@ static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
> if (latency == 0)
> return UINT_MAX;
>
> - plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
> + plane_bytes_per_line = horiz_pixels * cpp;
>
> if (tiling == I915_FORMAT_MOD_Y_TILED ||
> tiling == I915_FORMAT_MOD_Yf_TILED) {
> @@ -3121,23 +3119,21 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> uint32_t plane_bytes_per_line, plane_blocks_per_line;
> uint32_t res_blocks, res_lines;
> uint32_t selected_result;
> - uint8_t bytes_per_pixel;
> + uint8_t cpp;
>
> if (latency == 0 || !cstate->base.active || !fb)
> return false;
>
> - bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
> + cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
> - bytes_per_pixel,
> - latency);
> + cpp, latency);
> method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
> cstate->base.adjusted_mode.crtc_htotal,
> cstate->pipe_src_w,
> - bytes_per_pixel,
> - fb->modifier[0],
> + cpp, fb->modifier[0],
> latency);
>
> - plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
> + plane_bytes_per_line = cstate->pipe_src_w * cpp;
> plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
>
> if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
> @@ -3145,11 +3141,11 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> uint32_t min_scanlines = 4;
> uint32_t y_tile_minimum;
> if (intel_rotation_90_or_270(plane->state->rotation)) {
> - int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
> + int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
> drm_format_plane_cpp(fb->pixel_format, 1) :
> drm_format_plane_cpp(fb->pixel_format, 0);
>
> - switch (bpp) {
> + switch (cpp) {
> case 1:
> min_scanlines = 16;
> break;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index f1ee7db0811a..a2582c455b36 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -351,7 +351,7 @@ vlv_update_plane(struct drm_plane *dplane,
> int plane = intel_plane->plane;
> u32 sprctl;
> u32 sprsurf_offset, linear_offset;
> - int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> + int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> int crtc_x = plane_state->dst.x1;
> int crtc_y = plane_state->dst.y1;
> @@ -422,10 +422,9 @@ vlv_update_plane(struct drm_plane *dplane,
> crtc_w--;
> crtc_h--;
>
> - linear_offset = y * fb->pitches[0] + x * pixel_size;
> + linear_offset = y * fb->pitches[0] + x * cpp;
> sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
> - fb->modifier[0],
> - pixel_size,
> + fb->modifier[0], cpp,
> fb->pitches[0]);
> linear_offset -= sprsurf_offset;
>
> @@ -434,7 +433,7 @@ vlv_update_plane(struct drm_plane *dplane,
>
> x += src_w;
> y += src_h;
> - linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
> + linear_offset += src_h * fb->pitches[0] + src_w * cpp;
> }
>
> if (key->flags) {
> @@ -494,7 +493,7 @@ ivb_update_plane(struct drm_plane *plane,
> enum pipe pipe = intel_plane->pipe;
> u32 sprctl, sprscale = 0;
> u32 sprsurf_offset, linear_offset;
> - int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> + int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> int crtc_x = plane_state->dst.x1;
> int crtc_y = plane_state->dst.y1;
> @@ -556,10 +555,9 @@ ivb_update_plane(struct drm_plane *plane,
> if (crtc_w != src_w || crtc_h != src_h)
> sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
>
> - linear_offset = y * fb->pitches[0] + x * pixel_size;
> + linear_offset = y * fb->pitches[0] + x * cpp;
> sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
> - fb->modifier[0],
> - pixel_size,
> + fb->modifier[0], cpp,
> fb->pitches[0]);
> linear_offset -= sprsurf_offset;
>
> @@ -570,8 +568,7 @@ ivb_update_plane(struct drm_plane *plane,
> if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> x += src_w;
> y += src_h;
> - linear_offset += src_h * fb->pitches[0] +
> - src_w * pixel_size;
> + linear_offset += src_h * fb->pitches[0] + src_w * cpp;
> }
> }
>
> @@ -637,7 +634,7 @@ ilk_update_plane(struct drm_plane *plane,
> int pipe = intel_plane->pipe;
> u32 dvscntr, dvsscale;
> u32 dvssurf_offset, linear_offset;
> - int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> + int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> int crtc_x = plane_state->dst.x1;
> int crtc_y = plane_state->dst.y1;
> @@ -695,10 +692,9 @@ ilk_update_plane(struct drm_plane *plane,
> if (crtc_w != src_w || crtc_h != src_h)
> dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
>
> - linear_offset = y * fb->pitches[0] + x * pixel_size;
> + linear_offset = y * fb->pitches[0] + x * cpp;
> dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
> - fb->modifier[0],
> - pixel_size,
> + fb->modifier[0], cpp,
> fb->pitches[0]);
> linear_offset -= dvssurf_offset;
>
> @@ -707,7 +703,7 @@ ilk_update_plane(struct drm_plane *plane,
>
> x += src_w;
> y += src_h;
> - linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
> + linear_offset += src_h * fb->pitches[0] + src_w * cpp;
> }
>
> if (key->flags) {
> @@ -772,7 +768,6 @@ intel_check_sprite_plane(struct drm_plane *plane,
> int hscale, vscale;
> int max_scale, min_scale;
> bool can_scale;
> - int pixel_size;
>
> if (!fb) {
> state->visible = false;
> @@ -894,6 +889,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
> /* Check size restrictions when scaling */
> if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
> unsigned int width_bytes;
> + int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
>
> WARN_ON(!can_scale);
>
> @@ -905,9 +901,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
> if (src_w < 3 || src_h < 3)
> state->visible = false;
>
> - pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
> - width_bytes = ((src_x * pixel_size) & 63) +
> - src_w * pixel_size;
> + width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
>
> if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
> width_bytes > 4096 || fb->pitches[0] > 4096)) {
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height()
2016-01-20 19:05 ` [PATCH v2 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height() ville.syrjala
@ 2016-01-25 17:08 ` Daniel Vetter
2016-01-28 18:15 ` Ville Syrjälä
2016-01-29 18:01 ` [PATCH v3 " ville.syrjala
2016-02-09 15:29 ` [PATCH v4 " ville.syrjala
2 siblings, 1 reply; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 17:08 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx, dri-devel
On Wed, Jan 20, 2016 at 09:05:27PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add a few helpers to get the dimensions of the chroma plane(s).
>
> v2: Add kernel-doc (Daniel)
>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> include/drm/drm_crtc.h | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index c65a212db77e..91195c403422 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -2482,6 +2482,36 @@ extern int drm_format_num_planes(uint32_t format);
> extern int drm_format_plane_cpp(uint32_t format, int plane);
> extern int drm_format_horz_chroma_subsampling(uint32_t format);
> extern int drm_format_vert_chroma_subsampling(uint32_t format);
> +/**
> + * drm_format_plane_width - width of the plane given the first plane
> + * @width: width of the first plane
> + * @format: pixel format
> + * @plane: plane index
> + *
kerneldoc style is
+ * Returns:
+ * blabla
> + * Returns the width of @plane, given that the width of the first plane
> + * is @width.
> + */
> +static inline int drm_format_plane_width(int width, uint32_t format, int plane)
> +{
For consistency with other helpers I think we should put an
if (plane >= drm_format_num_planes(format))
return 0;
here. Also I think static inline is overkill for these, and grouping them
together with the others in drm_crtc.c will make it easier to extract them
into a new file (since drm_crtc.c is kinda sprawling a bit).
With those nitpicks applied: Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> + if (plane == 0)
> + return width;
> + return width / drm_format_horz_chroma_subsampling(format);
> +}
> +/**
> + * drm_format_plane_height - height of the plane given the first plane
> + * @height: height of the first plane
> + * @format: pixel format
> + * @plane: plane index
> + *
> + * Returns the height of @plane, given that the height of the first plane
> + * is @height.
> + */
> +static inline int drm_format_plane_height(int height, uint32_t format, int plane)
> +{
> + if (plane == 0)
> + return height;
> + return height / drm_format_vert_chroma_subsampling(format);
> +}
> extern const char *drm_get_format_name(uint32_t format);
> extern struct drm_property *drm_mode_create_rotation_property(struct drm_device *dev,
> unsigned int supported_rotations);
> --
> 2.4.10
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 07/18] drm/i915: Fix intel_tile_width() parameters
2016-01-20 19:05 ` [PATCH 07/18] drm/i915: Fix intel_tile_width() parameters ville.syrjala
@ 2016-01-25 17:12 ` Daniel Vetter
2016-01-28 18:35 ` Ville Syrjälä
0 siblings, 1 reply; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 17:12 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:28PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The fb_modifiers and cpp arguments passed to intel_tile_width() in
> intel_fill_fb_ggtt_view() got accidentally swapped around. I'm pretty
> sure I fixed this already, but could be I lost the fix accidentally
> during some rebases or something. Anyway, fix it up for real.
>
> Fixes: d9b3288ecf2f ("drm/i915: change intel_fill_fb_ggtt_view() to use the real tile size")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just to check my understanding: We did blow up in the MISSING_CASE in
tile_width for this in some igt, right? Please add a Testcase: igt/foo/bar
line for the one that makes it go boom. With that
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: drm-intel-fixes@lists.freedesktop.org
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f94ddad704b2..cfd52ea68e34 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2306,7 +2306,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
> tile_size = intel_tile_size(dev_priv);
>
> cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> - tile_width = intel_tile_width(dev_priv, cpp, fb->modifier[0]);
> + tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp);
> tile_height = tile_size / tile_width;
>
> info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 09/18] drm/i915: Support for extra alignment for tiled surfaces
2016-01-20 19:05 ` [PATCH v2 09/18] drm/i915: Support for extra alignment for tiled surfaces ville.syrjala
@ 2016-01-25 17:24 ` Daniel Vetter
2016-01-25 17:55 ` Ville Syrjälä
0 siblings, 1 reply; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 17:24 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:30PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> SKL+ needs >4K alignment for tiled surfaces, so make
> intel_compute_page_offset() handle it.
>
> The way we do it is first we compute the closest tile boundary
> as before, and then figure out how many tiles we need to go
> to reach the desired alignment. The difference in the offset
> is then added into the x/y offsets.
>
> v2: Be less confusing wrt. units (pixels vs. bytes) (Daniel)
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++++++++++++++++----
> 1 file changed, 42 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bda3224021b2..a102fabce5b4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2459,6 +2459,35 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
> }
>
> /*
> + * Adjust the tile offset by moving the difference into
> + * the x/y offsets.
> + *
> + * Input tile dimensions and pitch must already be
> + * rotated to match x and y, and in pixel units.
> + */
> +static void intel_adjust_tile_offset(int *x, int *y,
> + unsigned int tile_width,
> + unsigned int tile_height,
> + unsigned int tile_size,
> + unsigned int pitch_tiles,
> + unsigned int old_offset,
> + unsigned int new_offset)
> +{
> + unsigned int tiles;
> +
> + WARN_ON(old_offset & (tile_size - 1));
> + WARN_ON(new_offset & (tile_size - 1));
> + WARN_ON(new_offset > old_offset);
> +
> + tiles = (old_offset - new_offset) / tile_size;
> + if (tiles == 0)
> + return;
> +
> + *y += tiles / pitch_tiles * tile_height;
> + *x += tiles % pitch_tiles * tile_width;
> +}
> +
> +/*
> * Computes the linear offset to the base tile and adjusts
> * x, y. bytes per pixel is assumed to be a power-of-two.
> *
> @@ -2473,6 +2502,12 @@ u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> unsigned int pitch,
> unsigned int rotation)
> {
> + unsigned int offset, alignment;
> +
> + alignment = intel_surf_alignment(dev_priv, fb_modifier);
> + if (alignment)
> + alignment--;
Still voting for offset_aligned = ALIGN(offset, ...) per
http://article.gmane.org/gmane.comp.freedesktop.xorg.drivers.intel/72294
(at the very bottom, with the r-b for this patch).
> +
> if (fb_modifier != DRM_FORMAT_MOD_NONE) {
> unsigned int tile_size, tile_width, tile_height;
> unsigned int tile_rows, tiles, pitch_tiles;
> @@ -2494,16 +2529,18 @@ u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> tiles = *x / tile_width;
> *x %= tile_width;
>
> - return (tile_rows * pitch_tiles + tiles) * tile_size;
> - } else {
> - unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
> - unsigned int offset;
> + offset = (tile_rows * pitch_tiles + tiles) * tile_size;
pitch_tiles seems undefined here, does this compile?
-Daniel
>
> + intel_adjust_tile_offset(x, y, tile_width, tile_height,
> + tile_size, pitch_tiles,
> + offset, offset & ~alignment);
> + } else {
> offset = *y * pitch + *x * cpp;
> *y = (offset & alignment) / pitch;
> *x = ((offset & alignment) - *y * pitch) / cpp;
> - return offset & ~alignment;
> }
> +
> + return offset & ~alignment;
> }
>
> static int i9xx_format_to_fourcc(int format)
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v3 08/18] drm/i915: Pass 90/270 vs. 0/180 rotation info for intel_gen4_compute_page_offset()
2016-01-20 19:05 ` [PATCH v3 08/18] drm/i915: Pass 90/270 vs. 0/180 rotation info for intel_gen4_compute_page_offset() ville.syrjala
@ 2016-01-25 17:30 ` Daniel Vetter
2016-01-28 18:51 ` Ville Syrjälä
0 siblings, 1 reply; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 17:30 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:29PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The page aligned surface address calculation needs to know which way
> things are rotated. The contract now says that the caller must pass the
> rotate x/y coordinates, as well as the tile_height aligned stride in
> the tile_height direction. This will make it fairly simple to deal with
> 90/270 degree rotation on SKL+ where we have to deal with the rotated
> view into the GTT.
>
> v2: Pass rotation instead of bool even thoughwe only care about 0/180 vs. 90/270
> v3: Introduce intel_tile_dims(), and don't mix up different units so much
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2)
> ---
> drivers/gpu/drm/i915/intel_display.c | 66 +++++++++++++++++++++++++-----------
> drivers/gpu/drm/i915/intel_drv.h | 3 +-
> drivers/gpu/drm/i915/intel_sprite.c | 18 +++++-----
> 3 files changed, 59 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index cfd52ea68e34..bda3224021b2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2269,6 +2269,18 @@ unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
> intel_tile_width(dev_priv, fb_modifier, cpp);
> }
>
> +/* Return the tile dimensions in pixel units */
> +static void intel_tile_dims(const struct drm_i915_private *dev_priv,
> + unsigned int *tile_width,
> + unsigned int *tile_height,
> + uint64_t fb_modifier,
> + unsigned int cpp)
> +{
> + *tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
> + *tile_height = intel_tile_size(dev_priv) / *tile_width;
> + *tile_width /= cpp;
Seems like my suggestion to use tile_width in cpp wasn't that awesome, at
least we still have a big confusion right here. Not sure what to do,
especially since these kind of changes are super-painful to review. Could
we perhaps go back to the old versions and untangle this mess afterwards?
Iirc I've follow-up with r-b tags to all patches in the old series for
that approach.
No idea really what would be best here ...
-Daniel
> +}
> +
> unsigned int
> intel_fb_align_height(struct drm_device *dev, unsigned int height,
> uint32_t pixel_format, uint64_t fb_modifier)
> @@ -2306,19 +2318,19 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
> tile_size = intel_tile_size(dev_priv);
>
> cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> - tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp);
> - tile_height = tile_size / tile_width;
> + intel_tile_dims(dev_priv, &tile_width, &tile_height,
> + fb->modifier[0], cpp);
>
> - info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
> + info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
> info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
> info->size = info->width_pages * info->height_pages * tile_size;
>
> if (info->pixel_format == DRM_FORMAT_NV12) {
> cpp = drm_format_plane_cpp(fb->pixel_format, 1);
> - tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp);
> - tile_height = tile_size / tile_width;
> + intel_tile_dims(dev_priv, &tile_width, &tile_height,
> + fb->modifier[1], cpp);
>
> - info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width);
> + info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
> info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
> info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
> }
> @@ -2446,29 +2458,43 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
> i915_gem_object_unpin_from_display_plane(obj, &view);
> }
>
> -/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
> - * is assumed to be a power-of-two. */
> +/*
> + * Computes the linear offset to the base tile and adjusts
> + * x, y. bytes per pixel is assumed to be a power-of-two.
> + *
> + * In the 90/270 rotated case, x and y are assumed
> + * to be already rotated to match the rotated GTT view, and
> + * pitch is the tile_height aligned framebuffer height.
> + */
> u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> int *x, int *y,
> uint64_t fb_modifier,
> unsigned int cpp,
> - unsigned int pitch)
> + unsigned int pitch,
> + unsigned int rotation)
> {
> if (fb_modifier != DRM_FORMAT_MOD_NONE) {
> unsigned int tile_size, tile_width, tile_height;
> - unsigned int tile_rows, tiles;
> + unsigned int tile_rows, tiles, pitch_tiles;
>
> tile_size = intel_tile_size(dev_priv);
> - tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
> - tile_height = tile_size / tile_width;
> + intel_tile_dims(dev_priv, &tile_width, &tile_height,
> + fb_modifier, cpp);
> +
> + if (intel_rotation_90_or_270(rotation)) {
> + pitch_tiles = pitch / tile_height;
> + swap(tile_width, tile_height);
> + } else {
> + pitch_tiles = pitch / (tile_width * cpp);
> + }
>
> tile_rows = *y / tile_height;
> *y %= tile_height;
>
> - tiles = *x / (tile_width/cpp);
> - *x %= tile_width/cpp;
> + tiles = *x / tile_width;
> + *x %= tile_width;
>
> - return tile_rows * pitch * tile_height + tiles * tile_size;
> + return (tile_rows * pitch_tiles + tiles) * tile_size;
> } else {
> unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
> unsigned int offset;
> @@ -2709,6 +2735,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> u32 linear_offset;
> u32 dspcntr;
> i915_reg_t reg = DSPCNTR(plane);
> + unsigned int rotation = plane_state->base.rotation;
> int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> int x = plane_state->src.x1 >> 16;
> int y = plane_state->src.y1 >> 16;
> @@ -2775,13 +2802,13 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> intel_crtc->dspaddr_offset =
> intel_compute_tile_offset(dev_priv, &x, &y,
> fb->modifier[0], cpp,
> - fb->pitches[0]);
> + fb->pitches[0], rotation);
> linear_offset -= intel_crtc->dspaddr_offset;
> } else {
> intel_crtc->dspaddr_offset = linear_offset;
> }
>
> - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> + if (rotation == BIT(DRM_ROTATE_180)) {
> dspcntr |= DISPPLANE_ROTATE_180;
>
> x += (crtc_state->pipe_src_w - 1);
> @@ -2839,6 +2866,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> u32 linear_offset;
> u32 dspcntr;
> i915_reg_t reg = DSPCNTR(plane);
> + unsigned int rotation = plane_state->base.rotation;
> int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> int x = plane_state->src.x1 >> 16;
> int y = plane_state->src.y1 >> 16;
> @@ -2882,9 +2910,9 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> intel_crtc->dspaddr_offset =
> intel_compute_tile_offset(dev_priv, &x, &y,
> fb->modifier[0], cpp,
> - fb->pitches[0]);
> + fb->pitches[0], rotation);
> linear_offset -= intel_crtc->dspaddr_offset;
> - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> + if (rotation == BIT(DRM_ROTATE_180)) {
> dspcntr |= DISPPLANE_ROTATE_180;
>
> if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index f620023ed134..223693dbfe7c 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1176,7 +1176,8 @@ u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> int *x, int *y,
> uint64_t fb_modifier,
> unsigned int cpp,
> - unsigned int pitch);
> + unsigned int pitch,
> + unsigned int rotation);
> void intel_prepare_reset(struct drm_device *dev);
> void intel_finish_reset(struct drm_device *dev);
> void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index a2582c455b36..7dc2b8b2a4ac 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -193,7 +193,7 @@ skl_update_plane(struct drm_plane *drm_plane,
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> u32 surf_addr;
> u32 tile_height, plane_offset, plane_size;
> - unsigned int rotation;
> + unsigned int rotation = plane_state->base.rotation;
> int x_offset, y_offset;
> int crtc_x = plane_state->dst.x1;
> int crtc_y = plane_state->dst.y1;
> @@ -213,7 +213,6 @@ skl_update_plane(struct drm_plane *drm_plane,
> plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
> plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
>
> - rotation = plane_state->base.rotation;
> plane_ctl |= skl_plane_ctl_rotation(rotation);
>
> stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
> @@ -351,6 +350,7 @@ vlv_update_plane(struct drm_plane *dplane,
> int plane = intel_plane->plane;
> u32 sprctl;
> u32 sprsurf_offset, linear_offset;
> + unsigned int rotation = dplane->state->rotation;
> int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> int crtc_x = plane_state->dst.x1;
> @@ -425,10 +425,10 @@ vlv_update_plane(struct drm_plane *dplane,
> linear_offset = y * fb->pitches[0] + x * cpp;
> sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
> fb->modifier[0], cpp,
> - fb->pitches[0]);
> + fb->pitches[0], rotation);
> linear_offset -= sprsurf_offset;
>
> - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> + if (rotation == BIT(DRM_ROTATE_180)) {
> sprctl |= SP_ROTATE_180;
>
> x += src_w;
> @@ -493,6 +493,7 @@ ivb_update_plane(struct drm_plane *plane,
> enum pipe pipe = intel_plane->pipe;
> u32 sprctl, sprscale = 0;
> u32 sprsurf_offset, linear_offset;
> + unsigned int rotation = plane_state->base.rotation;
> int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> int crtc_x = plane_state->dst.x1;
> @@ -558,10 +559,10 @@ ivb_update_plane(struct drm_plane *plane,
> linear_offset = y * fb->pitches[0] + x * cpp;
> sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
> fb->modifier[0], cpp,
> - fb->pitches[0]);
> + fb->pitches[0], rotation);
> linear_offset -= sprsurf_offset;
>
> - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> + if (rotation == BIT(DRM_ROTATE_180)) {
> sprctl |= SPRITE_ROTATE_180;
>
> /* HSW and BDW does this automagically in hardware */
> @@ -634,6 +635,7 @@ ilk_update_plane(struct drm_plane *plane,
> int pipe = intel_plane->pipe;
> u32 dvscntr, dvsscale;
> u32 dvssurf_offset, linear_offset;
> + unsigned int rotation = plane_state->base.rotation;
> int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> int crtc_x = plane_state->dst.x1;
> @@ -695,10 +697,10 @@ ilk_update_plane(struct drm_plane *plane,
> linear_offset = y * fb->pitches[0] + x * cpp;
> dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
> fb->modifier[0], cpp,
> - fb->pitches[0]);
> + fb->pitches[0], rotation);
> linear_offset -= dvssurf_offset;
>
> - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> + if (rotation == BIT(DRM_ROTATE_180)) {
> dvscntr |= DVS_ROTATE_180;
>
> x += src_w;
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 12/18] drm/i915: Reorganize intel_rotation_info
2016-01-20 19:05 ` [PATCH 12/18] drm/i915: Reorganize intel_rotation_info ville.syrjala
@ 2016-01-25 17:38 ` Daniel Vetter
2016-01-25 18:03 ` Ville Syrjälä
0 siblings, 1 reply; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 17:38 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:33PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Throw out a bunch of unnecessary stuff from struct intel_rotation_info,
> and pull most of the remaining stuff to live under an array of
> per-color plane sub-structures.
>
> What still remains outside the sub-structure will be reorgranized later
> as well, but that requires more work elsewhere so leave it be for now.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 35 +++++++++++++++--------------------
> drivers/gpu/drm/i915/i915_gem_gtt.h | 11 ++++-------
> drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++----------
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 4 files changed, 35 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index b3d8e2b0948c..f95468cd0470 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3367,7 +3367,7 @@ static struct sg_table *
> intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
> struct drm_i915_gem_object *obj)
> {
> - unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
> + unsigned int size_pages = rot_info->plane[0].width * rot_info->plane[0].height;
> unsigned int size_pages_uv;
> struct sg_page_iter sg_iter;
> unsigned long i;
> @@ -3385,7 +3385,7 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
>
> /* Account for UV plane with NV12. */
> if (rot_info->pixel_format == DRM_FORMAT_NV12)
> - size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
> + size_pages_uv = rot_info->plane[1].width * rot_info->plane[1].height;
> else
> size_pages_uv = 0;
>
> @@ -3407,9 +3407,9 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
>
> /* Rotate the pages. */
> sg = rotate_pages(page_addr_list, 0,
> - rot_info->width_pages, rot_info->height_pages,
> - rot_info->width_pages,
> - st, NULL);
> + rot_info->plane[0].width, rot_info->plane[0].height,
> + rot_info->plane[0].width,
> + st, NULL);
>
> /* Append the UV plane if NV12. */
> if (rot_info->pixel_format == DRM_FORMAT_NV12) {
> @@ -3421,18 +3421,15 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
>
> rot_info->uv_start_page = uv_start_page;
>
> - rotate_pages(page_addr_list, uv_start_page,
> - rot_info->width_pages_uv,
> - rot_info->height_pages_uv,
> - rot_info->width_pages_uv,
> + rotate_pages(page_addr_list, rot_info->uv_start_page,
> + rot_info->plane[1].width, rot_info->plane[1].height,
> + rot_info->plane[1].width,
> st, sg);
> }
>
> - DRM_DEBUG_KMS(
> - "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
> - obj->base.size, rot_info->pitch, rot_info->height,
> - rot_info->pixel_format, rot_info->width_pages,
> - rot_info->height_pages, size_pages + size_pages_uv,
> + DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
> + obj->base.size, rot_info->plane[0].width,
> + rot_info->plane[0].height, size_pages + size_pages_uv,
> size_pages);
>
> drm_free_large(page_addr_list);
> @@ -3444,11 +3441,9 @@ err_sg_alloc:
> err_st_alloc:
> drm_free_large(page_addr_list);
>
> - DRM_DEBUG_KMS(
> - "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
> - obj->base.size, ret, rot_info->pitch, rot_info->height,
> - rot_info->pixel_format, rot_info->width_pages,
> - rot_info->height_pages, size_pages + size_pages_uv,
> + DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n",
> + obj->base.size, ret, rot_info->plane[0].width,
> + rot_info->plane[0].height, size_pages + size_pages_uv,
> size_pages);
> return ERR_PTR(ret);
> }
> @@ -3600,7 +3595,7 @@ i915_ggtt_view_size(struct drm_i915_gem_object *obj,
> if (view->type == I915_GGTT_VIEW_NORMAL) {
> return obj->base.size;
> } else if (view->type == I915_GGTT_VIEW_ROTATED) {
> - return view->params.rotated.size;
> + return intel_rotation_info_size(&view->params.rotated) << PAGE_SHIFT;
Isn't this a hidden bugfix? before this was size, now it's size+size_uv.
If you agree then please add a blurb to the commit message (or better,
split this out into a tiny prep patch). Otherwise didn't spot anything,
with either approach
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
> return view->params.partial.size << PAGE_SHIFT;
> } else {
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index f520c90e5377..4b8a378b9d3f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -135,16 +135,13 @@ enum i915_ggtt_view_type {
> };
>
> struct intel_rotation_info {
> - unsigned int height;
> - unsigned int pitch;
> unsigned int uv_offset;
> uint32_t pixel_format;
> - uint64_t fb_modifier;
> - unsigned int width_pages, height_pages;
> - uint64_t size;
> - unsigned int width_pages_uv, height_pages_uv;
> - uint64_t size_uv;
> unsigned int uv_start_page;
> + struct {
> + /* tiles */
> + unsigned int width, height;
> + } plane[2];
> };
>
> struct i915_ggtt_view {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 084c8ae3668f..899ffb1a9b10 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2291,6 +2291,17 @@ intel_fb_align_height(struct drm_device *dev, unsigned int height,
> return ALIGN(height, tile_height);
> }
>
> +unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
> +{
> + unsigned int size = 0;
> + int i;
> +
> + for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
> + size += rot_info->plane[i].width * rot_info->plane[i].height;
> +
> + return size;
> +}
> +
> static void
> intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
> const struct drm_framebuffer *fb,
> @@ -2307,11 +2318,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
>
> *view = i915_ggtt_view_rotated;
>
> - info->height = fb->height;
> - info->pixel_format = fb->pixel_format;
> - info->pitch = fb->pitches[0];
> info->uv_offset = fb->offsets[1];
> - info->fb_modifier = fb->modifier[0];
>
> tile_size = intel_tile_size(dev_priv);
>
> @@ -2319,18 +2326,16 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
> intel_tile_dims(dev_priv, &tile_width, &tile_height,
> fb->modifier[0], cpp);
>
> - info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
> - info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
> - info->size = info->width_pages * info->height_pages * tile_size;
> + info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
> + info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
>
> if (info->pixel_format == DRM_FORMAT_NV12) {
> cpp = drm_format_plane_cpp(fb->pixel_format, 1);
> intel_tile_dims(dev_priv, &tile_width, &tile_height,
> fb->modifier[1], cpp);
>
> - info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
> - info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
> - info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
> + info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
> + info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index b9ef9d5f1041..f251f253cc99 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1059,6 +1059,7 @@ void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
>
> /* intel_display.c */
> extern const struct drm_plane_funcs intel_plane_funcs;
> +unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
> bool intel_has_pending_fb_unpin(struct drm_device *dev);
> int intel_pch_rawclk(struct drm_device *dev);
> int intel_hrawclk(struct drm_device *dev);
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 13/18] drm/i915: Move the NULL sg handling out from rotate_pages()
2016-01-20 19:05 ` [PATCH 13/18] drm/i915: Move the NULL sg handling out from rotate_pages() ville.syrjala
@ 2016-01-25 17:40 ` Daniel Vetter
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 17:40 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:34PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> rotate_pages() checks to see if it got called with a NULL sg, and then
> goes to extract it from sg->sgl. It always gets called with a NULL sg
> for the first plane, so moving the initial 'sg=st->sgl' assignment out
> into intel_rotate_fb_obj_pages() seems less special-casey.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 18 ++++++++----------
> 1 file changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index f95468cd0470..db80ec08cca4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3339,11 +3339,6 @@ rotate_pages(const dma_addr_t *in, unsigned int offset,
> unsigned int column, row;
> unsigned int src_idx;
>
> - if (!sg) {
> - st->nents = 0;
> - sg = st->sgl;
> - }
> -
> for (column = 0; column < width; column++) {
> src_idx = stride * (height - 1) + column;
> for (row = 0; row < height; row++) {
> @@ -3405,11 +3400,14 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
> i++;
> }
>
> + st->nents = 0;
> + sg = st->sgl;
> +
> /* Rotate the pages. */
> sg = rotate_pages(page_addr_list, 0,
> rot_info->plane[0].width, rot_info->plane[0].height,
> rot_info->plane[0].width,
> - st, NULL);
> + st, sg);
>
> /* Append the UV plane if NV12. */
> if (rot_info->pixel_format == DRM_FORMAT_NV12) {
> @@ -3421,10 +3419,10 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
>
> rot_info->uv_start_page = uv_start_page;
>
> - rotate_pages(page_addr_list, rot_info->uv_start_page,
> - rot_info->plane[1].width, rot_info->plane[1].height,
> - rot_info->plane[1].width,
> - st, sg);
> + sg = rotate_pages(page_addr_list, rot_info->uv_start_page,
> + rot_info->plane[1].width, rot_info->plane[1].height,
> + rot_info->plane[1].width,
> + st, sg);
> }
>
> DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 14/18] drm/i915: Embed rotation_info under intel_framebuffer
2016-01-20 19:05 ` [PATCH 14/18] drm/i915: Embed rotation_info under intel_framebuffer ville.syrjala
2016-01-20 21:08 ` Chris Wilson
@ 2016-01-25 17:42 ` Daniel Vetter
1 sibling, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 17:42 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:35PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Instead of repopulatin the rotation_info struct for the fb every time
> we try to use the fb, we can just populate it once when creating the fb,
> and later we can just copy the pre-populate struct into the gtt_view.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's hope this doesn't balloon too badly in the future, but I think
that's unlikely given how rotation works currently (and on other hw).
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++-----------
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 2 files changed, 17 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 899ffb1a9b10..7ed33b5eb443 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2307,18 +2307,20 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
> const struct drm_framebuffer *fb,
> unsigned int rotation)
> {
> - struct drm_i915_private *dev_priv = to_i915(fb->dev);
> - struct intel_rotation_info *info = &view->params.rotated;
> - unsigned int tile_size, tile_width, tile_height, cpp;
> -
> - *view = i915_ggtt_view_normal;
> -
> - if (!intel_rotation_90_or_270(rotation))
> - return;
> -
> - *view = i915_ggtt_view_rotated;
> + if (intel_rotation_90_or_270(rotation)) {
> + *view = i915_ggtt_view_rotated;
> + view->params.rotated = to_intel_framebuffer(fb)->rot_info;
> + } else {
> + *view = i915_ggtt_view_normal;
> + }
> +}
>
> - info->uv_offset = fb->offsets[1];
> +static void
> +intel_fill_fb_info(struct drm_i915_private *dev_priv,
> + struct drm_framebuffer *fb)
> +{
> + struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
> + unsigned int tile_size, tile_width, tile_height, cpp;
>
> tile_size = intel_tile_size(dev_priv);
>
> @@ -2334,6 +2336,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
> intel_tile_dims(dev_priv, &tile_width, &tile_height,
> fb->modifier[1], cpp);
>
> + info->uv_offset = fb->offsets[1];
> info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
> info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
> }
> @@ -14906,6 +14909,8 @@ static int intel_framebuffer_init(struct drm_device *dev,
> drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
> intel_fb->obj = obj;
>
> + intel_fill_fb_info(dev_priv, &intel_fb->base);
> +
> ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
> if (ret) {
> DRM_ERROR("framebuffer init failed %d\n", ret);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index f251f253cc99..8a0f4dfd04a6 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -118,6 +118,7 @@ enum intel_output_type {
> struct intel_framebuffer {
> struct drm_framebuffer base;
> struct drm_i915_gem_object *obj;
> + struct intel_rotation_info rot_info;
> };
>
> struct intel_fbdev {
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 16/18] drm/i915: Don't pass pitch to intel_compute_page_offset()
2016-01-20 19:05 ` [PATCH v2 16/18] drm/i915: Don't pass pitch to intel_compute_page_offset() ville.syrjala
@ 2016-01-25 17:53 ` Daniel Vetter
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 17:53 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:37PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_compute_page_offset() can dig up the correct pitch from the fb
> itself, no need for the caller to pass it in.
>
> A bit of extra care is needed for the lower level
> _intel_compute_page_offset() since that one gets called before the
> rotated pitch under intel_fb is populated. Note that we don't actually
> call it with anything but DRM_ROTATE_0 there so we wouldn't actually
> look up the rotated pitch there, but still, leave the pitch as something
> the caller has to pass to _intel_compute_page_offset() as an
> indicator that something is a bit special.
>
> This leaves 'stride_div' in the skl plane update hooks as a mostly useless
> variable so just get rid of it.
>
> v2: Add a note why stride_div got nuked
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++--------------
> drivers/gpu/drm/i915/intel_drv.h | 1 -
> drivers/gpu/drm/i915/intel_sprite.c | 26 +++++++++++---------------
> 3 files changed, 27 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ef68892f4e0a..eb8ce8a99291 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2562,11 +2562,16 @@ static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
>
> unsigned int intel_compute_tile_offset(int *x, int *y,
> const struct drm_framebuffer *fb, int plane,
> - unsigned int pitch,
> unsigned int rotation)
> {
> const struct drm_i915_private *dev_priv = to_i915(fb->dev);
> unsigned int alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
> + unsigned int pitch;
> +
> + if (intel_rotation_90_or_270(rotation))
> + pitch = to_intel_framebuffer(fb)->rotated[plane].pitch;
> + else
> + pitch = fb->pitches[plane];
>
> return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
> rotation, alignment ? (alignment - 1) : 0);
> @@ -2988,8 +2993,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
>
> if (INTEL_INFO(dev)->gen >= 4)
> intel_crtc->dspaddr_offset =
> - intel_compute_tile_offset(&x, &y, fb, 0,
> - fb->pitches[0], rotation);
> + intel_compute_tile_offset(&x, &y, fb, 0, rotation);
>
> if (rotation == BIT(DRM_ROTATE_180)) {
> dspcntr |= DISPPLANE_ROTATE_180;
> @@ -3091,8 +3095,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> intel_add_fb_offsets(&x, &y, fb, 0, rotation);
>
> intel_crtc->dspaddr_offset =
> - intel_compute_tile_offset(&x, &y, fb, 0,
> - fb->pitches[0], rotation);
> + intel_compute_tile_offset(&x, &y, fb, 0, rotation);
>
> if (rotation == BIT(DRM_ROTATE_180)) {
> dspcntr |= DISPPLANE_ROTATE_180;
> @@ -3263,7 +3266,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_framebuffer *fb = plane_state->base.fb;
> int pipe = intel_crtc->pipe;
> - u32 plane_ctl, stride_div, stride;
> + u32 plane_ctl, stride;
> unsigned int rotation = plane_state->base.rotation;
> u32 surf_addr;
> int scaler_id = plane_state->scaler_id;
> @@ -3303,17 +3306,16 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
> src_w = drm_rect_width(&r);
> src_h = drm_rect_height(&r);
>
> - stride_div = intel_tile_height(dev_priv, fb->modifier[0], cpp);
> - stride = intel_fb->rotated[0].pitch;
> + stride = intel_fb->rotated[0].pitch /
> + intel_tile_height(dev_priv, fb->modifier[0], cpp);
> } else {
> - stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
> - fb->pixel_format);
> - stride = fb->pitches[0];
> + stride = fb->pitches[0] /
> + intel_fb_stride_alignment(dev_priv, fb->modifier[0],
> + fb->pixel_format);
> }
>
> intel_add_fb_offsets(&src_x, &src_y, fb, 0, rotation);
> - surf_addr = intel_compute_tile_offset(&src_x, &src_y, fb, 0,
> - stride, rotation);
> + surf_addr = intel_compute_tile_offset(&src_x, &src_y, fb, 0, rotation);
>
> /* Sizes are 0 based */
> src_w--;
> @@ -3326,7 +3328,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
>
> I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
> I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
> - I915_WRITE(PLANE_STRIDE(pipe, 0), stride / stride_div);
> + I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
> I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
>
> if (scaler_id >= 0) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 473b4cf9a2ff..e3de1fc3b04d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1190,7 +1190,6 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
> #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
> u32 intel_compute_tile_offset(int *x, int *y,
> const struct drm_framebuffer *fb, int plane,
> - unsigned int pitch,
> unsigned int rotation);
> void intel_prepare_reset(struct drm_device *dev);
> void intel_finish_reset(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 86176304155d..31be24f27207 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -189,7 +189,7 @@ skl_update_plane(struct drm_plane *drm_plane,
> struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> const int pipe = intel_plane->pipe;
> const int plane = intel_plane->plane + 1;
> - u32 plane_ctl, stride_div, stride;
> + u32 plane_ctl, stride;
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> u32 surf_addr;
> unsigned int rotation = plane_state->base.rotation;
> @@ -241,17 +241,16 @@ skl_update_plane(struct drm_plane *drm_plane,
> src_w = drm_rect_width(&r);
> src_h = drm_rect_height(&r);
>
> - stride_div = intel_tile_height(dev_priv, fb->modifier[0], cpp);
> - stride = intel_fb->rotated[0].pitch;
> + stride = intel_fb->rotated[0].pitch /
> + intel_tile_height(dev_priv, fb->modifier[0], cpp);
> } else {
> - stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
> - fb->pixel_format);
> - stride = fb->pitches[0];
> + stride = fb->pitches[0] /
> + intel_fb_stride_alignment(dev_priv, fb->modifier[0],
> + fb->pixel_format);
> }
>
> intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> - surf_addr = intel_compute_tile_offset(&x, &y, fb, 0,
> - stride, rotation);
> + surf_addr = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
>
> /* Sizes are 0 based */
> src_w--;
> @@ -260,7 +259,7 @@ skl_update_plane(struct drm_plane *drm_plane,
> crtc_h--;
>
> I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
> - I915_WRITE(PLANE_STRIDE(pipe, plane), stride / stride_div);
> + I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
> I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w);
>
> /* program plane scaler */
> @@ -428,8 +427,7 @@ vlv_update_plane(struct drm_plane *dplane,
> crtc_h--;
>
> intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> - sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
> - fb->pitches[0], rotation);
> + sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
>
> if (rotation == BIT(DRM_ROTATE_180)) {
> sprctl |= SP_ROTATE_180;
> @@ -560,8 +558,7 @@ ivb_update_plane(struct drm_plane *plane,
> sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
>
> intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> - sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
> - fb->pitches[0], rotation);
> + sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
>
> if (rotation == BIT(DRM_ROTATE_180)) {
> sprctl |= SPRITE_ROTATE_180;
> @@ -696,8 +693,7 @@ ilk_update_plane(struct drm_plane *plane,
> dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
>
> intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> - dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
> - fb->pitches[0], rotation);
> + dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
>
> if (rotation == BIT(DRM_ROTATE_180)) {
> dvscntr |= DVS_ROTATE_180;
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 09/18] drm/i915: Support for extra alignment for tiled surfaces
2016-01-25 17:24 ` Daniel Vetter
@ 2016-01-25 17:55 ` Ville Syrjälä
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjälä @ 2016-01-25 17:55 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Mon, Jan 25, 2016 at 06:24:05PM +0100, Daniel Vetter wrote:
> On Wed, Jan 20, 2016 at 09:05:30PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > SKL+ needs >4K alignment for tiled surfaces, so make
> > intel_compute_page_offset() handle it.
> >
> > The way we do it is first we compute the closest tile boundary
> > as before, and then figure out how many tiles we need to go
> > to reach the desired alignment. The difference in the offset
> > is then added into the x/y offsets.
> >
> > v2: Be less confusing wrt. units (pixels vs. bytes) (Daniel)
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++++++++++++++++----
> > 1 file changed, 42 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index bda3224021b2..a102fabce5b4 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2459,6 +2459,35 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
> > }
> >
> > /*
> > + * Adjust the tile offset by moving the difference into
> > + * the x/y offsets.
> > + *
> > + * Input tile dimensions and pitch must already be
> > + * rotated to match x and y, and in pixel units.
> > + */
> > +static void intel_adjust_tile_offset(int *x, int *y,
> > + unsigned int tile_width,
> > + unsigned int tile_height,
> > + unsigned int tile_size,
> > + unsigned int pitch_tiles,
> > + unsigned int old_offset,
> > + unsigned int new_offset)
> > +{
> > + unsigned int tiles;
> > +
> > + WARN_ON(old_offset & (tile_size - 1));
> > + WARN_ON(new_offset & (tile_size - 1));
> > + WARN_ON(new_offset > old_offset);
> > +
> > + tiles = (old_offset - new_offset) / tile_size;
> > + if (tiles == 0)
> > + return;
> > +
> > + *y += tiles / pitch_tiles * tile_height;
> > + *x += tiles % pitch_tiles * tile_width;
> > +}
> > +
> > +/*
> > * Computes the linear offset to the base tile and adjusts
> > * x, y. bytes per pixel is assumed to be a power-of-two.
> > *
> > @@ -2473,6 +2502,12 @@ u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> > unsigned int pitch,
> > unsigned int rotation)
> > {
> > + unsigned int offset, alignment;
> > +
> > + alignment = intel_surf_alignment(dev_priv, fb_modifier);
> > + if (alignment)
> > + alignment--;
>
> Still voting for offset_aligned = ALIGN(offset, ...) per
>
> http://article.gmane.org/gmane.comp.freedesktop.xorg.drivers.intel/72294
>
> (at the very bottom, with the r-b for this patch).
And as I replied there, ALIGN doesn't do what we want.
>
> > +
> > if (fb_modifier != DRM_FORMAT_MOD_NONE) {
> > unsigned int tile_size, tile_width, tile_height;
> > unsigned int tile_rows, tiles, pitch_tiles;
> > @@ -2494,16 +2529,18 @@ u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> > tiles = *x / tile_width;
> > *x %= tile_width;
> >
> > - return (tile_rows * pitch_tiles + tiles) * tile_size;
> > - } else {
> > - unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
> > - unsigned int offset;
> > + offset = (tile_rows * pitch_tiles + tiles) * tile_size;
>
> pitch_tiles seems undefined here, does this compile?
Yes. Diff just likes to make patches hard to read.
> -Daniel
>
> >
> > + intel_adjust_tile_offset(x, y, tile_width, tile_height,
> > + tile_size, pitch_tiles,
> > + offset, offset & ~alignment);
> > + } else {
> > offset = *y * pitch + *x * cpp;
> > *y = (offset & alignment) / pitch;
> > *x = ((offset & alignment) - *y * pitch) / cpp;
> > - return offset & ~alignment;
> > }
> > +
> > + return offset & ~alignment;
> > }
> >
> > static int i9xx_format_to_fourcc(int format)
> > --
> > 2.4.10
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 17/18] drm/i915: Pass around plane_state instead of fb+rotation
2016-01-20 19:05 ` [PATCH 17/18] drm/i915: Pass around plane_state instead of fb+rotation ville.syrjala
@ 2016-01-25 17:55 ` Daniel Vetter
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2016-01-25 17:55 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jan 20, 2016 at 09:05:38PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_compute_tile_offset() and intel_add_fb_offsets() get passed the fb
> and the rotation. As both of those come from the plane state we can just
> pass that in instead.
>
> For extra consitency pass the plane state to intel_fb_xy_to_linear() as
> well even though it only really needs the fb.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_display.c | 35 ++++++++++++++++++++---------------
> drivers/gpu/drm/i915/intel_drv.h | 9 ++++-----
> drivers/gpu/drm/i915/intel_sprite.c | 22 +++++++++++-----------
> 3 files changed, 35 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index eb8ce8a99291..2e6cbf65b265 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2442,8 +2442,10 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation
> * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
> */
> unsigned int intel_fb_xy_to_linear(int x, int y,
> - const struct drm_framebuffer *fb, int plane)
> + const struct intel_plane_state *state,
> + int plane)
> {
> + const struct drm_framebuffer *fb = state->base.fb;
> unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
> unsigned int pitch = fb->pitches[plane];
>
> @@ -2456,11 +2458,12 @@ unsigned int intel_fb_xy_to_linear(int x, int y,
> * specify the start of scanout from the beginning of the gtt mapping.
> */
> void intel_add_fb_offsets(int *x, int *y,
> - const struct drm_framebuffer *fb, int plane,
> - unsigned int rotation)
> + const struct intel_plane_state *state,
> + int plane)
>
> {
> - const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> + const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
> + unsigned int rotation = state->base.rotation;
>
> if (intel_rotation_90_or_270(rotation)) {
> *x += intel_fb->rotated[plane].x;
> @@ -2561,10 +2564,12 @@ static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
> }
>
> unsigned int intel_compute_tile_offset(int *x, int *y,
> - const struct drm_framebuffer *fb, int plane,
> - unsigned int rotation)
> + const struct intel_plane_state *state,
> + int plane)
> {
> - const struct drm_i915_private *dev_priv = to_i915(fb->dev);
> + const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
> + const struct drm_framebuffer *fb = state->base.fb;
> + unsigned int rotation = state->base.rotation;
> unsigned int alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
> unsigned int pitch;
>
> @@ -2989,11 +2994,11 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> if (IS_G4X(dev))
> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>
> - intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> + intel_add_fb_offsets(&x, &y, plane_state, 0);
>
> if (INTEL_INFO(dev)->gen >= 4)
> intel_crtc->dspaddr_offset =
> - intel_compute_tile_offset(&x, &y, fb, 0, rotation);
> + intel_compute_tile_offset(&x, &y, plane_state, 0);
>
> if (rotation == BIT(DRM_ROTATE_180)) {
> dspcntr |= DISPPLANE_ROTATE_180;
> @@ -3002,7 +3007,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> y += (crtc_state->pipe_src_h - 1);
> }
>
> - linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
> + linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>
> if (INTEL_INFO(dev)->gen < 4)
> intel_crtc->dspaddr_offset = linear_offset;
> @@ -3092,10 +3097,10 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>
> - intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> + intel_add_fb_offsets(&x, &y, plane_state, 0);
>
> intel_crtc->dspaddr_offset =
> - intel_compute_tile_offset(&x, &y, fb, 0, rotation);
> + intel_compute_tile_offset(&x, &y, plane_state, 0);
>
> if (rotation == BIT(DRM_ROTATE_180)) {
> dspcntr |= DISPPLANE_ROTATE_180;
> @@ -3106,7 +3111,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> }
> }
>
> - linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
> + linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>
> intel_crtc->adjusted_x = x;
> intel_crtc->adjusted_y = y;
> @@ -3314,8 +3319,8 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
> fb->pixel_format);
> }
>
> - intel_add_fb_offsets(&src_x, &src_y, fb, 0, rotation);
> - surf_addr = intel_compute_tile_offset(&src_x, &src_y, fb, 0, rotation);
> + intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
> + surf_addr = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
>
> /* Sizes are 0 based */
> src_w--;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e3de1fc3b04d..09cfc0eea5a4 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1071,10 +1071,10 @@ void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
> /* intel_display.c */
> extern const struct drm_plane_funcs intel_plane_funcs;
> unsigned int intel_fb_xy_to_linear(int x, int y,
> - const struct drm_framebuffer *fb, int plane);
> + const struct intel_plane_state *state,
> + int plane);
> void intel_add_fb_offsets(int *x, int *y,
> - const struct drm_framebuffer *fb, int plane,
> - unsigned int rotation);
> + const struct intel_plane_state *state, int plane);
> unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
> bool intel_has_pending_fb_unpin(struct drm_device *dev);
> int intel_pch_rawclk(struct drm_device *dev);
> @@ -1189,8 +1189,7 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
> #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
> #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
> u32 intel_compute_tile_offset(int *x, int *y,
> - const struct drm_framebuffer *fb, int plane,
> - unsigned int rotation);
> + const struct intel_plane_state *state, int plane);
> void intel_prepare_reset(struct drm_device *dev);
> void intel_finish_reset(struct drm_device *dev);
> void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 31be24f27207..ad533cc2b5f5 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -249,8 +249,8 @@ skl_update_plane(struct drm_plane *drm_plane,
> fb->pixel_format);
> }
>
> - intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> - surf_addr = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
> + intel_add_fb_offsets(&x, &y, plane_state, 0);
> + surf_addr = intel_compute_tile_offset(&x, &y, plane_state, 0);
>
> /* Sizes are 0 based */
> src_w--;
> @@ -426,8 +426,8 @@ vlv_update_plane(struct drm_plane *dplane,
> crtc_w--;
> crtc_h--;
>
> - intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> - sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
> + intel_add_fb_offsets(&x, &y, plane_state, 0);
> + sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
>
> if (rotation == BIT(DRM_ROTATE_180)) {
> sprctl |= SP_ROTATE_180;
> @@ -436,7 +436,7 @@ vlv_update_plane(struct drm_plane *dplane,
> y += src_h;
> }
>
> - linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
> + linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>
> if (key->flags) {
> I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
> @@ -557,8 +557,8 @@ ivb_update_plane(struct drm_plane *plane,
> if (crtc_w != src_w || crtc_h != src_h)
> sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
>
> - intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> - sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
> + intel_add_fb_offsets(&x, &y, plane_state, 0);
> + sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
>
> if (rotation == BIT(DRM_ROTATE_180)) {
> sprctl |= SPRITE_ROTATE_180;
> @@ -570,7 +570,7 @@ ivb_update_plane(struct drm_plane *plane,
> }
> }
>
> - linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
> + linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>
> if (key->flags) {
> I915_WRITE(SPRKEYVAL(pipe), key->min_value);
> @@ -692,8 +692,8 @@ ilk_update_plane(struct drm_plane *plane,
> if (crtc_w != src_w || crtc_h != src_h)
> dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
>
> - intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> - dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
> + intel_add_fb_offsets(&x, &y, plane_state, 0);
> + dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
>
> if (rotation == BIT(DRM_ROTATE_180)) {
> dvscntr |= DVS_ROTATE_180;
> @@ -702,7 +702,7 @@ ilk_update_plane(struct drm_plane *plane,
> y += src_h;
> }
>
> - linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
> + linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>
> if (key->flags) {
> I915_WRITE(DVSKEYVAL(pipe), key->min_value);
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 12/18] drm/i915: Reorganize intel_rotation_info
2016-01-25 17:38 ` Daniel Vetter
@ 2016-01-25 18:03 ` Ville Syrjälä
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjälä @ 2016-01-25 18:03 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Mon, Jan 25, 2016 at 06:38:57PM +0100, Daniel Vetter wrote:
> On Wed, Jan 20, 2016 at 09:05:33PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Throw out a bunch of unnecessary stuff from struct intel_rotation_info,
> > and pull most of the remaining stuff to live under an array of
> > per-color plane sub-structures.
> >
> > What still remains outside the sub-structure will be reorgranized later
> > as well, but that requires more work elsewhere so leave it be for now.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_gem_gtt.c | 35 +++++++++++++++--------------------
> > drivers/gpu/drm/i915/i915_gem_gtt.h | 11 ++++-------
> > drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++----------
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > 4 files changed, 35 insertions(+), 37 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index b3d8e2b0948c..f95468cd0470 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -3367,7 +3367,7 @@ static struct sg_table *
> > intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
> > struct drm_i915_gem_object *obj)
> > {
> > - unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
> > + unsigned int size_pages = rot_info->plane[0].width * rot_info->plane[0].height;
> > unsigned int size_pages_uv;
> > struct sg_page_iter sg_iter;
> > unsigned long i;
> > @@ -3385,7 +3385,7 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
> >
> > /* Account for UV plane with NV12. */
> > if (rot_info->pixel_format == DRM_FORMAT_NV12)
> > - size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
> > + size_pages_uv = rot_info->plane[1].width * rot_info->plane[1].height;
> > else
> > size_pages_uv = 0;
> >
> > @@ -3407,9 +3407,9 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
> >
> > /* Rotate the pages. */
> > sg = rotate_pages(page_addr_list, 0,
> > - rot_info->width_pages, rot_info->height_pages,
> > - rot_info->width_pages,
> > - st, NULL);
> > + rot_info->plane[0].width, rot_info->plane[0].height,
> > + rot_info->plane[0].width,
> > + st, NULL);
> >
> > /* Append the UV plane if NV12. */
> > if (rot_info->pixel_format == DRM_FORMAT_NV12) {
> > @@ -3421,18 +3421,15 @@ intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
> >
> > rot_info->uv_start_page = uv_start_page;
> >
> > - rotate_pages(page_addr_list, uv_start_page,
> > - rot_info->width_pages_uv,
> > - rot_info->height_pages_uv,
> > - rot_info->width_pages_uv,
> > + rotate_pages(page_addr_list, rot_info->uv_start_page,
> > + rot_info->plane[1].width, rot_info->plane[1].height,
> > + rot_info->plane[1].width,
> > st, sg);
> > }
> >
> > - DRM_DEBUG_KMS(
> > - "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
> > - obj->base.size, rot_info->pitch, rot_info->height,
> > - rot_info->pixel_format, rot_info->width_pages,
> > - rot_info->height_pages, size_pages + size_pages_uv,
> > + DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
> > + obj->base.size, rot_info->plane[0].width,
> > + rot_info->plane[0].height, size_pages + size_pages_uv,
> > size_pages);
> >
> > drm_free_large(page_addr_list);
> > @@ -3444,11 +3441,9 @@ err_sg_alloc:
> > err_st_alloc:
> > drm_free_large(page_addr_list);
> >
> > - DRM_DEBUG_KMS(
> > - "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
> > - obj->base.size, ret, rot_info->pitch, rot_info->height,
> > - rot_info->pixel_format, rot_info->width_pages,
> > - rot_info->height_pages, size_pages + size_pages_uv,
> > + DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n",
> > + obj->base.size, ret, rot_info->plane[0].width,
> > + rot_info->plane[0].height, size_pages + size_pages_uv,
> > size_pages);
> > return ERR_PTR(ret);
> > }
> > @@ -3600,7 +3595,7 @@ i915_ggtt_view_size(struct drm_i915_gem_object *obj,
> > if (view->type == I915_GGTT_VIEW_NORMAL) {
> > return obj->base.size;
> > } else if (view->type == I915_GGTT_VIEW_ROTATED) {
> > - return view->params.rotated.size;
> > + return intel_rotation_info_size(&view->params.rotated) << PAGE_SHIFT;
>
> Isn't this a hidden bugfix? before this was size, now it's size+size_uv.
Hmm. I suppose. TBH didn't even notice that myself.
>
> If you agree then please add a blurb to the commit message (or better,
> split this out into a tiny prep patch). Otherwise didn't spot anything,
> with either approach
>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> > } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
> > return view->params.partial.size << PAGE_SHIFT;
> > } else {
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> > index f520c90e5377..4b8a378b9d3f 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> > @@ -135,16 +135,13 @@ enum i915_ggtt_view_type {
> > };
> >
> > struct intel_rotation_info {
> > - unsigned int height;
> > - unsigned int pitch;
> > unsigned int uv_offset;
> > uint32_t pixel_format;
> > - uint64_t fb_modifier;
> > - unsigned int width_pages, height_pages;
> > - uint64_t size;
> > - unsigned int width_pages_uv, height_pages_uv;
> > - uint64_t size_uv;
> > unsigned int uv_start_page;
> > + struct {
> > + /* tiles */
> > + unsigned int width, height;
> > + } plane[2];
> > };
> >
> > struct i915_ggtt_view {
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 084c8ae3668f..899ffb1a9b10 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2291,6 +2291,17 @@ intel_fb_align_height(struct drm_device *dev, unsigned int height,
> > return ALIGN(height, tile_height);
> > }
> >
> > +unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
> > +{
> > + unsigned int size = 0;
> > + int i;
> > +
> > + for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
> > + size += rot_info->plane[i].width * rot_info->plane[i].height;
> > +
> > + return size;
> > +}
> > +
> > static void
> > intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
> > const struct drm_framebuffer *fb,
> > @@ -2307,11 +2318,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
> >
> > *view = i915_ggtt_view_rotated;
> >
> > - info->height = fb->height;
> > - info->pixel_format = fb->pixel_format;
> > - info->pitch = fb->pitches[0];
> > info->uv_offset = fb->offsets[1];
> > - info->fb_modifier = fb->modifier[0];
> >
> > tile_size = intel_tile_size(dev_priv);
> >
> > @@ -2319,18 +2326,16 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
> > intel_tile_dims(dev_priv, &tile_width, &tile_height,
> > fb->modifier[0], cpp);
> >
> > - info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
> > - info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
> > - info->size = info->width_pages * info->height_pages * tile_size;
> > + info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
> > + info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
> >
> > if (info->pixel_format == DRM_FORMAT_NV12) {
> > cpp = drm_format_plane_cpp(fb->pixel_format, 1);
> > intel_tile_dims(dev_priv, &tile_width, &tile_height,
> > fb->modifier[1], cpp);
> >
> > - info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
> > - info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
> > - info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
> > + info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
> > + info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
> > }
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index b9ef9d5f1041..f251f253cc99 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1059,6 +1059,7 @@ void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
> >
> > /* intel_display.c */
> > extern const struct drm_plane_funcs intel_plane_funcs;
> > +unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
> > bool intel_has_pending_fb_unpin(struct drm_device *dev);
> > int intel_pch_rawclk(struct drm_device *dev);
> > int intel_hrawclk(struct drm_device *dev);
> > --
> > 2.4.10
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height()
2016-01-25 17:08 ` Daniel Vetter
@ 2016-01-28 18:15 ` Ville Syrjälä
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjälä @ 2016-01-28 18:15 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, dri-devel
On Mon, Jan 25, 2016 at 06:08:23PM +0100, Daniel Vetter wrote:
> On Wed, Jan 20, 2016 at 09:05:27PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Add a few helpers to get the dimensions of the chroma plane(s).
> >
> > v2: Add kernel-doc (Daniel)
> >
> > Cc: dri-devel@lists.freedesktop.org
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> > include/drm/drm_crtc.h | 30 ++++++++++++++++++++++++++++++
> > 1 file changed, 30 insertions(+)
> >
> > diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> > index c65a212db77e..91195c403422 100644
> > --- a/include/drm/drm_crtc.h
> > +++ b/include/drm/drm_crtc.h
> > @@ -2482,6 +2482,36 @@ extern int drm_format_num_planes(uint32_t format);
> > extern int drm_format_plane_cpp(uint32_t format, int plane);
> > extern int drm_format_horz_chroma_subsampling(uint32_t format);
> > extern int drm_format_vert_chroma_subsampling(uint32_t format);
> > +/**
> > + * drm_format_plane_width - width of the plane given the first plane
> > + * @width: width of the first plane
> > + * @format: pixel format
> > + * @plane: plane index
> > + *
>
> kerneldoc style is
>
> + * Returns:
> + * blabla
Hmm. I guess I should read some kind of manual of style or whatever.
>
> > + * Returns the width of @plane, given that the width of the first plane
> > + * is @width.
> > + */
> > +static inline int drm_format_plane_width(int width, uint32_t format, int plane)
> > +{
>
> For consistency with other helpers I think we should put an
>
> if (plane >= drm_format_num_planes(format))
> return 0;
>
> here. Also I think static inline is overkill for these, and grouping them
> together with the others in drm_crtc.c will make it easier to extract them
> into a new file (since drm_crtc.c is kinda sprawling a bit).
Well with the static inline I was aiming for the compiler to eliminate
the function calls entirely for the typical plane==0 constant case. But
if we add the num_planes check, then it's pretty much going to do that
function call anyway.
>
> With those nitpicks applied: Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> > + if (plane == 0)
> > + return width;
> > + return width / drm_format_horz_chroma_subsampling(format);
> > +}
> > +/**
> > + * drm_format_plane_height - height of the plane given the first plane
> > + * @height: height of the first plane
> > + * @format: pixel format
> > + * @plane: plane index
> > + *
> > + * Returns the height of @plane, given that the height of the first plane
> > + * is @height.
> > + */
> > +static inline int drm_format_plane_height(int height, uint32_t format, int plane)
> > +{
> > + if (plane == 0)
> > + return height;
> > + return height / drm_format_vert_chroma_subsampling(format);
> > +}
> > extern const char *drm_get_format_name(uint32_t format);
> > extern struct drm_property *drm_mode_create_rotation_property(struct drm_device *dev,
> > unsigned int supported_rotations);
> > --
> > 2.4.10
> >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 07/18] drm/i915: Fix intel_tile_width() parameters
2016-01-25 17:12 ` Daniel Vetter
@ 2016-01-28 18:35 ` Ville Syrjälä
2016-01-28 19:04 ` Ville Syrjälä
0 siblings, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2016-01-28 18:35 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Mon, Jan 25, 2016 at 06:12:15PM +0100, Daniel Vetter wrote:
> On Wed, Jan 20, 2016 at 09:05:28PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The fb_modifiers and cpp arguments passed to intel_tile_width() in
> > intel_fill_fb_ggtt_view() got accidentally swapped around. I'm pretty
> > sure I fixed this already, but could be I lost the fix accidentally
> > during some rebases or something. Anyway, fix it up for real.
> >
> > Fixes: d9b3288ecf2f ("drm/i915: change intel_fill_fb_ggtt_view() to use the real tile size")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Just to check my understanding: We did blow up in the MISSING_CASE in
> tile_width for this in some igt, right? Please add a Testcase: igt/foo/bar
> line for the one that makes it go boom. With that
This will do for example:
Testcase: igt/kms_rotation_crc/primary-rotation-90
>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: drm-intel-fixes@lists.freedesktop.org
>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index f94ddad704b2..cfd52ea68e34 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2306,7 +2306,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
> > tile_size = intel_tile_size(dev_priv);
> >
> > cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > - tile_width = intel_tile_width(dev_priv, cpp, fb->modifier[0]);
> > + tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp);
> > tile_height = tile_size / tile_width;
> >
> > info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
> > --
> > 2.4.10
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v3 08/18] drm/i915: Pass 90/270 vs. 0/180 rotation info for intel_gen4_compute_page_offset()
2016-01-25 17:30 ` Daniel Vetter
@ 2016-01-28 18:51 ` Ville Syrjälä
2016-02-10 7:35 ` Daniel Vetter
0 siblings, 1 reply; 50+ messages in thread
From: Ville Syrjälä @ 2016-01-28 18:51 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Mon, Jan 25, 2016 at 06:30:17PM +0100, Daniel Vetter wrote:
> On Wed, Jan 20, 2016 at 09:05:29PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The page aligned surface address calculation needs to know which way
> > things are rotated. The contract now says that the caller must pass the
> > rotate x/y coordinates, as well as the tile_height aligned stride in
> > the tile_height direction. This will make it fairly simple to deal with
> > 90/270 degree rotation on SKL+ where we have to deal with the rotated
> > view into the GTT.
> >
> > v2: Pass rotation instead of bool even thoughwe only care about 0/180 vs. 90/270
> > v3: Introduce intel_tile_dims(), and don't mix up different units so much
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2)
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 66 +++++++++++++++++++++++++-----------
> > drivers/gpu/drm/i915/intel_drv.h | 3 +-
> > drivers/gpu/drm/i915/intel_sprite.c | 18 +++++-----
> > 3 files changed, 59 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index cfd52ea68e34..bda3224021b2 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2269,6 +2269,18 @@ unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
> > intel_tile_width(dev_priv, fb_modifier, cpp);
> > }
> >
> > +/* Return the tile dimensions in pixel units */
> > +static void intel_tile_dims(const struct drm_i915_private *dev_priv,
> > + unsigned int *tile_width,
> > + unsigned int *tile_height,
> > + uint64_t fb_modifier,
> > + unsigned int cpp)
> > +{
> > + *tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
> > + *tile_height = intel_tile_size(dev_priv) / *tile_width;
> > + *tile_width /= cpp;
>
> Seems like my suggestion to use tile_width in cpp wasn't that awesome, at
> least we still have a big confusion right here. Not sure what to do,
> especially since these kind of changes are super-painful to review. Could
> we perhaps go back to the old versions and untangle this mess afterwards?
> Iirc I've follow-up with r-b tags to all patches in the old series for
> that approach.
Hmm. What did I do differently in the old approach again? Other than not
having the confusion isolated to this one function. One step forward and
two back doens't sound productive. Plus I have some more patches on top
of this one already, so not pleasant at all.
Anyway, to avoid more confusion I suppose one thing that could be done
is this:
- intel_tile_width
+ intel_tile_width_bytes
intel_tile_dims()
{
tile_width_bytes = intel_tile_width_bytes()
*tile_height = tile_size / tile_width_bytes;
*tile_width = tile_width_bytes / cpp;
}
>
> No idea really what would be best here ...
> -Daniel
>
> > +}
> > +
> > unsigned int
> > intel_fb_align_height(struct drm_device *dev, unsigned int height,
> > uint32_t pixel_format, uint64_t fb_modifier)
> > @@ -2306,19 +2318,19 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
> > tile_size = intel_tile_size(dev_priv);
> >
> > cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > - tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp);
> > - tile_height = tile_size / tile_width;
> > + intel_tile_dims(dev_priv, &tile_width, &tile_height,
> > + fb->modifier[0], cpp);
> >
> > - info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
> > + info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
> > info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
> > info->size = info->width_pages * info->height_pages * tile_size;
> >
> > if (info->pixel_format == DRM_FORMAT_NV12) {
> > cpp = drm_format_plane_cpp(fb->pixel_format, 1);
> > - tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp);
> > - tile_height = tile_size / tile_width;
> > + intel_tile_dims(dev_priv, &tile_width, &tile_height,
> > + fb->modifier[1], cpp);
> >
> > - info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width);
> > + info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
> > info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
> > info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
> > }
> > @@ -2446,29 +2458,43 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
> > i915_gem_object_unpin_from_display_plane(obj, &view);
> > }
> >
> > -/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
> > - * is assumed to be a power-of-two. */
> > +/*
> > + * Computes the linear offset to the base tile and adjusts
> > + * x, y. bytes per pixel is assumed to be a power-of-two.
> > + *
> > + * In the 90/270 rotated case, x and y are assumed
> > + * to be already rotated to match the rotated GTT view, and
> > + * pitch is the tile_height aligned framebuffer height.
> > + */
> > u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> > int *x, int *y,
> > uint64_t fb_modifier,
> > unsigned int cpp,
> > - unsigned int pitch)
> > + unsigned int pitch,
> > + unsigned int rotation)
> > {
> > if (fb_modifier != DRM_FORMAT_MOD_NONE) {
> > unsigned int tile_size, tile_width, tile_height;
> > - unsigned int tile_rows, tiles;
> > + unsigned int tile_rows, tiles, pitch_tiles;
> >
> > tile_size = intel_tile_size(dev_priv);
> > - tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
> > - tile_height = tile_size / tile_width;
> > + intel_tile_dims(dev_priv, &tile_width, &tile_height,
> > + fb_modifier, cpp);
> > +
> > + if (intel_rotation_90_or_270(rotation)) {
> > + pitch_tiles = pitch / tile_height;
> > + swap(tile_width, tile_height);
> > + } else {
> > + pitch_tiles = pitch / (tile_width * cpp);
> > + }
> >
> > tile_rows = *y / tile_height;
> > *y %= tile_height;
> >
> > - tiles = *x / (tile_width/cpp);
> > - *x %= tile_width/cpp;
> > + tiles = *x / tile_width;
> > + *x %= tile_width;
> >
> > - return tile_rows * pitch * tile_height + tiles * tile_size;
> > + return (tile_rows * pitch_tiles + tiles) * tile_size;
> > } else {
> > unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
> > unsigned int offset;
> > @@ -2709,6 +2735,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> > u32 linear_offset;
> > u32 dspcntr;
> > i915_reg_t reg = DSPCNTR(plane);
> > + unsigned int rotation = plane_state->base.rotation;
> > int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > int x = plane_state->src.x1 >> 16;
> > int y = plane_state->src.y1 >> 16;
> > @@ -2775,13 +2802,13 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> > intel_crtc->dspaddr_offset =
> > intel_compute_tile_offset(dev_priv, &x, &y,
> > fb->modifier[0], cpp,
> > - fb->pitches[0]);
> > + fb->pitches[0], rotation);
> > linear_offset -= intel_crtc->dspaddr_offset;
> > } else {
> > intel_crtc->dspaddr_offset = linear_offset;
> > }
> >
> > - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> > + if (rotation == BIT(DRM_ROTATE_180)) {
> > dspcntr |= DISPPLANE_ROTATE_180;
> >
> > x += (crtc_state->pipe_src_w - 1);
> > @@ -2839,6 +2866,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> > u32 linear_offset;
> > u32 dspcntr;
> > i915_reg_t reg = DSPCNTR(plane);
> > + unsigned int rotation = plane_state->base.rotation;
> > int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > int x = plane_state->src.x1 >> 16;
> > int y = plane_state->src.y1 >> 16;
> > @@ -2882,9 +2910,9 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> > intel_crtc->dspaddr_offset =
> > intel_compute_tile_offset(dev_priv, &x, &y,
> > fb->modifier[0], cpp,
> > - fb->pitches[0]);
> > + fb->pitches[0], rotation);
> > linear_offset -= intel_crtc->dspaddr_offset;
> > - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> > + if (rotation == BIT(DRM_ROTATE_180)) {
> > dspcntr |= DISPPLANE_ROTATE_180;
> >
> > if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index f620023ed134..223693dbfe7c 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1176,7 +1176,8 @@ u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> > int *x, int *y,
> > uint64_t fb_modifier,
> > unsigned int cpp,
> > - unsigned int pitch);
> > + unsigned int pitch,
> > + unsigned int rotation);
> > void intel_prepare_reset(struct drm_device *dev);
> > void intel_finish_reset(struct drm_device *dev);
> > void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index a2582c455b36..7dc2b8b2a4ac 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -193,7 +193,7 @@ skl_update_plane(struct drm_plane *drm_plane,
> > const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > u32 surf_addr;
> > u32 tile_height, plane_offset, plane_size;
> > - unsigned int rotation;
> > + unsigned int rotation = plane_state->base.rotation;
> > int x_offset, y_offset;
> > int crtc_x = plane_state->dst.x1;
> > int crtc_y = plane_state->dst.y1;
> > @@ -213,7 +213,6 @@ skl_update_plane(struct drm_plane *drm_plane,
> > plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
> > plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
> >
> > - rotation = plane_state->base.rotation;
> > plane_ctl |= skl_plane_ctl_rotation(rotation);
> >
> > stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
> > @@ -351,6 +350,7 @@ vlv_update_plane(struct drm_plane *dplane,
> > int plane = intel_plane->plane;
> > u32 sprctl;
> > u32 sprsurf_offset, linear_offset;
> > + unsigned int rotation = dplane->state->rotation;
> > int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > int crtc_x = plane_state->dst.x1;
> > @@ -425,10 +425,10 @@ vlv_update_plane(struct drm_plane *dplane,
> > linear_offset = y * fb->pitches[0] + x * cpp;
> > sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
> > fb->modifier[0], cpp,
> > - fb->pitches[0]);
> > + fb->pitches[0], rotation);
> > linear_offset -= sprsurf_offset;
> >
> > - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> > + if (rotation == BIT(DRM_ROTATE_180)) {
> > sprctl |= SP_ROTATE_180;
> >
> > x += src_w;
> > @@ -493,6 +493,7 @@ ivb_update_plane(struct drm_plane *plane,
> > enum pipe pipe = intel_plane->pipe;
> > u32 sprctl, sprscale = 0;
> > u32 sprsurf_offset, linear_offset;
> > + unsigned int rotation = plane_state->base.rotation;
> > int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > int crtc_x = plane_state->dst.x1;
> > @@ -558,10 +559,10 @@ ivb_update_plane(struct drm_plane *plane,
> > linear_offset = y * fb->pitches[0] + x * cpp;
> > sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
> > fb->modifier[0], cpp,
> > - fb->pitches[0]);
> > + fb->pitches[0], rotation);
> > linear_offset -= sprsurf_offset;
> >
> > - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> > + if (rotation == BIT(DRM_ROTATE_180)) {
> > sprctl |= SPRITE_ROTATE_180;
> >
> > /* HSW and BDW does this automagically in hardware */
> > @@ -634,6 +635,7 @@ ilk_update_plane(struct drm_plane *plane,
> > int pipe = intel_plane->pipe;
> > u32 dvscntr, dvsscale;
> > u32 dvssurf_offset, linear_offset;
> > + unsigned int rotation = plane_state->base.rotation;
> > int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > int crtc_x = plane_state->dst.x1;
> > @@ -695,10 +697,10 @@ ilk_update_plane(struct drm_plane *plane,
> > linear_offset = y * fb->pitches[0] + x * cpp;
> > dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
> > fb->modifier[0], cpp,
> > - fb->pitches[0]);
> > + fb->pitches[0], rotation);
> > linear_offset -= dvssurf_offset;
> >
> > - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> > + if (rotation == BIT(DRM_ROTATE_180)) {
> > dvscntr |= DVS_ROTATE_180;
> >
> > x += src_w;
> > --
> > 2.4.10
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH 07/18] drm/i915: Fix intel_tile_width() parameters
2016-01-28 18:35 ` Ville Syrjälä
@ 2016-01-28 19:04 ` Ville Syrjälä
0 siblings, 0 replies; 50+ messages in thread
From: Ville Syrjälä @ 2016-01-28 19:04 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Jan 28, 2016 at 08:35:26PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 25, 2016 at 06:12:15PM +0100, Daniel Vetter wrote:
> > On Wed, Jan 20, 2016 at 09:05:28PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > The fb_modifiers and cpp arguments passed to intel_tile_width() in
> > > intel_fill_fb_ggtt_view() got accidentally swapped around. I'm pretty
> > > sure I fixed this already, but could be I lost the fix accidentally
> > > during some rebases or something. Anyway, fix it up for real.
> > >
> > > Fixes: d9b3288ecf2f ("drm/i915: change intel_fill_fb_ggtt_view() to use the real tile size")
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Just to check my understanding: We did blow up in the MISSING_CASE in
> > tile_width for this in some igt, right? Please add a Testcase: igt/foo/bar
> > line for the one that makes it go boom. With that
>
> This will do for example:
> Testcase: igt/kms_rotation_crc/primary-rotation-90
And pushed up to this patch (except for the drm_format_plane_width/height
patch, which I skipped for now), thanks for the reviews.
>
> >
> > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Cc: drm-intel-fixes@lists.freedesktop.org
> >
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index f94ddad704b2..cfd52ea68e34 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -2306,7 +2306,7 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
> > > tile_size = intel_tile_size(dev_priv);
> > >
> > > cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > > - tile_width = intel_tile_width(dev_priv, cpp, fb->modifier[0]);
> > > + tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp);
> > > tile_height = tile_size / tile_width;
> > >
> > > info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
> > > --
> > > 2.4.10
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
>
> --
> Ville Syrjälä
> Intel OTC
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v3 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height()
2016-01-20 19:05 ` [PATCH v2 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height() ville.syrjala
2016-01-25 17:08 ` Daniel Vetter
@ 2016-01-29 18:01 ` ville.syrjala
2016-02-09 9:08 ` Daniel Vetter
2016-02-09 15:29 ` [PATCH v4 " ville.syrjala
2 siblings, 1 reply; 50+ messages in thread
From: ville.syrjala @ 2016-01-29 18:01 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a few helpers to get the dimensions of the chroma plane(s).
v2: Add kernel-doc (Daniel)
v3: Fix kerneldoc "Returns:" style (Daniel)
Uninline the functions and check for num_planes (Daniel)
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/drm_crtc.c | 40 ++++++++++++++++++++++++++++++++++++++++
include/drm/drm_crtc.h | 2 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 6e6514ef9968..c708b37972de 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -5715,6 +5715,46 @@ int drm_format_vert_chroma_subsampling(uint32_t format)
EXPORT_SYMBOL(drm_format_vert_chroma_subsampling);
/**
+ * drm_format_plane_width - width of the plane given the first plane
+ * @width: width of the first plane
+ * @format: pixel format
+ * @plane: plane index
+ *
+ * Returns:
+ * The width of @plane, given that the width of the first plane is @width.
+ */
+int drm_format_plane_width(int width, uint32_t format, int plane)
+{
+ if (plane >= drm_format_num_planes(format))
+ return 0;
+
+ if (plane == 0)
+ return width;
+
+ return width / drm_format_horz_chroma_subsampling(format);
+}
+
+/**
+ * drm_format_plane_height - height of the plane given the first plane
+ * @height: height of the first plane
+ * @format: pixel format
+ * @plane: plane index
+ *
+ * Returns:
+ * The height of @plane, given that the height of the first plane is @height.
+ */
+int drm_format_plane_height(int height, uint32_t format, int plane)
+{
+ if (plane >= drm_format_num_planes(format))
+ return 0;
+
+ if (plane == 0)
+ return height;
+
+ return height / drm_format_vert_chroma_subsampling(format);
+}
+
+/**
* drm_rotation_simplify() - Try to simplify the rotation
* @rotation: Rotation to be simplified
* @supported_rotations: Supported rotations
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index c65a212db77e..3a4b53ecd121 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -2482,6 +2482,8 @@ extern int drm_format_num_planes(uint32_t format);
extern int drm_format_plane_cpp(uint32_t format, int plane);
extern int drm_format_horz_chroma_subsampling(uint32_t format);
extern int drm_format_vert_chroma_subsampling(uint32_t format);
+extern int drm_format_plane_width(int width, uint32_t format, int plane);
+extern int drm_format_plane_height(int height, uint32_t format, int plane);
extern const char *drm_get_format_name(uint32_t format);
extern struct drm_property *drm_mode_create_rotation_property(struct drm_device *dev,
unsigned int supported_rotations);
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) (rev2)
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (18 preceding siblings ...)
2016-01-21 13:35 ` ✓ Fi.CI.BAT: success for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) Patchwork
@ 2016-01-30 8:31 ` Patchwork
2016-02-01 8:31 ` Patchwork
2016-02-09 16:31 ` ✗ Fi.CI.BAT: failure for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) (rev3) Patchwork
21 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2016-01-30 8:31 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Summary ==
Series 2679v2 drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2)
2016-01-29T18:01:25.652420 http://patchwork.freedesktop.org/api/1.0/series/2679/revisions/2/mbox/
Applying: drm/i915: Rename the rotated gtt view member to 'rotated'
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_gem_gtt.c
M drivers/gpu/drm/i915/i915_gem_gtt.h
M drivers/gpu/drm/i915/intel_display.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_gem_gtt.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_gem_gtt.c
Patch failed at 0001 drm/i915: Rename the rotated gtt view member to 'rotated'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) (rev2)
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (19 preceding siblings ...)
2016-01-30 8:31 ` ✗ Fi.CI.BAT: failure for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) (rev2) Patchwork
@ 2016-02-01 8:31 ` Patchwork
2016-02-09 16:31 ` ✗ Fi.CI.BAT: failure for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) (rev3) Patchwork
21 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2016-02-01 8:31 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Summary ==
Series 2679v2 drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2)
2016-01-29T18:01:25.652420 http://patchwork.freedesktop.org/api/1.0/series/2679/revisions/2/mbox/
Applying: drm/i915: Rename the rotated gtt view member to 'rotated'
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_gem_gtt.c
M drivers/gpu/drm/i915/i915_gem_gtt.h
M drivers/gpu/drm/i915/intel_display.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_gem_gtt.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_gem_gtt.c
Patch failed at 0001 drm/i915: Rename the rotated gtt view member to 'rotated'
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v3 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height()
2016-01-29 18:01 ` [PATCH v3 " ville.syrjala
@ 2016-02-09 9:08 ` Daniel Vetter
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2016-02-09 9:08 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx, dri-devel
On Fri, Jan 29, 2016 at 08:01:19PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add a few helpers to get the dimensions of the chroma plane(s).
>
> v2: Add kernel-doc (Daniel)
> v3: Fix kerneldoc "Returns:" style (Daniel)
> Uninline the functions and check for num_planes (Daniel)
>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Applied to drm-misc, thanks.
-Daniel
> ---
> drivers/gpu/drm/drm_crtc.c | 40 ++++++++++++++++++++++++++++++++++++++++
> include/drm/drm_crtc.h | 2 ++
> 2 files changed, 42 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> index 6e6514ef9968..c708b37972de 100644
> --- a/drivers/gpu/drm/drm_crtc.c
> +++ b/drivers/gpu/drm/drm_crtc.c
> @@ -5715,6 +5715,46 @@ int drm_format_vert_chroma_subsampling(uint32_t format)
> EXPORT_SYMBOL(drm_format_vert_chroma_subsampling);
>
> /**
> + * drm_format_plane_width - width of the plane given the first plane
> + * @width: width of the first plane
> + * @format: pixel format
> + * @plane: plane index
> + *
> + * Returns:
> + * The width of @plane, given that the width of the first plane is @width.
> + */
> +int drm_format_plane_width(int width, uint32_t format, int plane)
> +{
> + if (plane >= drm_format_num_planes(format))
> + return 0;
> +
> + if (plane == 0)
> + return width;
> +
> + return width / drm_format_horz_chroma_subsampling(format);
> +}
> +
> +/**
> + * drm_format_plane_height - height of the plane given the first plane
> + * @height: height of the first plane
> + * @format: pixel format
> + * @plane: plane index
> + *
> + * Returns:
> + * The height of @plane, given that the height of the first plane is @height.
> + */
> +int drm_format_plane_height(int height, uint32_t format, int plane)
> +{
> + if (plane >= drm_format_num_planes(format))
> + return 0;
> +
> + if (plane == 0)
> + return height;
> +
> + return height / drm_format_vert_chroma_subsampling(format);
> +}
> +
> +/**
> * drm_rotation_simplify() - Try to simplify the rotation
> * @rotation: Rotation to be simplified
> * @supported_rotations: Supported rotations
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index c65a212db77e..3a4b53ecd121 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -2482,6 +2482,8 @@ extern int drm_format_num_planes(uint32_t format);
> extern int drm_format_plane_cpp(uint32_t format, int plane);
> extern int drm_format_horz_chroma_subsampling(uint32_t format);
> extern int drm_format_vert_chroma_subsampling(uint32_t format);
> +extern int drm_format_plane_width(int width, uint32_t format, int plane);
> +extern int drm_format_plane_height(int height, uint32_t format, int plane);
> extern const char *drm_get_format_name(uint32_t format);
> extern struct drm_property *drm_mode_create_rotation_property(struct drm_device *dev,
> unsigned int supported_rotations);
> --
> 2.4.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v4 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height()
2016-01-20 19:05 ` [PATCH v2 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height() ville.syrjala
2016-01-25 17:08 ` Daniel Vetter
2016-01-29 18:01 ` [PATCH v3 " ville.syrjala
@ 2016-02-09 15:29 ` ville.syrjala
2 siblings, 0 replies; 50+ messages in thread
From: ville.syrjala @ 2016-02-09 15:29 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a few helpers to get the dimensions of the chroma plane(s).
v2: Add kernel-doc (Daniel)
v3: Fix kerneldoc "Returns:" style (Daniel)
Uninline the functions and check for num_planes (Daniel)
v4: Add the required EXPORT_SYMBOL()s
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
drivers/gpu/drm/drm_crtc.c | 42 ++++++++++++++++++++++++++++++++++++++++++
include/drm/drm_crtc.h | 2 ++
2 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 6e6514ef9968..1685eb33b4f3 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -5715,6 +5715,48 @@ int drm_format_vert_chroma_subsampling(uint32_t format)
EXPORT_SYMBOL(drm_format_vert_chroma_subsampling);
/**
+ * drm_format_plane_width - width of the plane given the first plane
+ * @width: width of the first plane
+ * @format: pixel format
+ * @plane: plane index
+ *
+ * Returns:
+ * The width of @plane, given that the width of the first plane is @width.
+ */
+int drm_format_plane_width(int width, uint32_t format, int plane)
+{
+ if (plane >= drm_format_num_planes(format))
+ return 0;
+
+ if (plane == 0)
+ return width;
+
+ return width / drm_format_horz_chroma_subsampling(format);
+}
+EXPORT_SYMBOL(drm_format_plane_width);
+
+/**
+ * drm_format_plane_height - height of the plane given the first plane
+ * @height: height of the first plane
+ * @format: pixel format
+ * @plane: plane index
+ *
+ * Returns:
+ * The height of @plane, given that the height of the first plane is @height.
+ */
+int drm_format_plane_height(int height, uint32_t format, int plane)
+{
+ if (plane >= drm_format_num_planes(format))
+ return 0;
+
+ if (plane == 0)
+ return height;
+
+ return height / drm_format_vert_chroma_subsampling(format);
+}
+EXPORT_SYMBOL(drm_format_plane_height);
+
+/**
* drm_rotation_simplify() - Try to simplify the rotation
* @rotation: Rotation to be simplified
* @supported_rotations: Supported rotations
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index c65a212db77e..3a4b53ecd121 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -2482,6 +2482,8 @@ extern int drm_format_num_planes(uint32_t format);
extern int drm_format_plane_cpp(uint32_t format, int plane);
extern int drm_format_horz_chroma_subsampling(uint32_t format);
extern int drm_format_vert_chroma_subsampling(uint32_t format);
+extern int drm_format_plane_width(int width, uint32_t format, int plane);
+extern int drm_format_plane_height(int height, uint32_t format, int plane);
extern const char *drm_get_format_name(uint32_t format);
extern struct drm_property *drm_mode_create_rotation_property(struct drm_device *dev,
unsigned int supported_rotations);
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) (rev3)
2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
` (20 preceding siblings ...)
2016-02-01 8:31 ` Patchwork
@ 2016-02-09 16:31 ` Patchwork
21 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2016-02-09 16:31 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Summary ==
Series 2679v3 drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2)
2016-02-09T15:30:40.543598 http://patchwork.freedesktop.org/api/1.0/series/2679/revisions/3/mbox/
Applying: drm/i915: Rename the rotated gtt view member to 'rotated'
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_gem_gtt.c
M drivers/gpu/drm/i915/i915_gem_gtt.h
M drivers/gpu/drm/i915/intel_display.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_gem_gtt.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_gem_gtt.c
Patch failed at 0001 drm/i915: Rename the rotated gtt view member to 'rotated'
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v3 08/18] drm/i915: Pass 90/270 vs. 0/180 rotation info for intel_gen4_compute_page_offset()
2016-01-28 18:51 ` Ville Syrjälä
@ 2016-02-10 7:35 ` Daniel Vetter
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2016-02-10 7:35 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Jan 28, 2016 at 08:51:14PM +0200, Ville Syrjälä wrote:
> On Mon, Jan 25, 2016 at 06:30:17PM +0100, Daniel Vetter wrote:
> > On Wed, Jan 20, 2016 at 09:05:29PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > The page aligned surface address calculation needs to know which way
> > > things are rotated. The contract now says that the caller must pass the
> > > rotate x/y coordinates, as well as the tile_height aligned stride in
> > > the tile_height direction. This will make it fairly simple to deal with
> > > 90/270 degree rotation on SKL+ where we have to deal with the rotated
> > > view into the GTT.
> > >
> > > v2: Pass rotation instead of bool even thoughwe only care about 0/180 vs. 90/270
> > > v3: Introduce intel_tile_dims(), and don't mix up different units so much
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v2)
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 66 +++++++++++++++++++++++++-----------
> > > drivers/gpu/drm/i915/intel_drv.h | 3 +-
> > > drivers/gpu/drm/i915/intel_sprite.c | 18 +++++-----
> > > 3 files changed, 59 insertions(+), 28 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index cfd52ea68e34..bda3224021b2 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -2269,6 +2269,18 @@ unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
> > > intel_tile_width(dev_priv, fb_modifier, cpp);
> > > }
> > >
> > > +/* Return the tile dimensions in pixel units */
> > > +static void intel_tile_dims(const struct drm_i915_private *dev_priv,
> > > + unsigned int *tile_width,
> > > + unsigned int *tile_height,
> > > + uint64_t fb_modifier,
> > > + unsigned int cpp)
> > > +{
> > > + *tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
> > > + *tile_height = intel_tile_size(dev_priv) / *tile_width;
> > > + *tile_width /= cpp;
> >
> > Seems like my suggestion to use tile_width in cpp wasn't that awesome, at
> > least we still have a big confusion right here. Not sure what to do,
> > especially since these kind of changes are super-painful to review. Could
> > we perhaps go back to the old versions and untangle this mess afterwards?
> > Iirc I've follow-up with r-b tags to all patches in the old series for
> > that approach.
>
> Hmm. What did I do differently in the old approach again? Other than not
> having the confusion isolated to this one function. One step forward and
> two back doens't sound productive. Plus I have some more patches on top
> of this one already, so not pleasant at all.
Old patch reused the same variables for values both in bytes and pixels
(and the conversion happened deep down in some function call, without any
comments). This here looks better, but still suffers a bit from confusing
naming.
>
> Anyway, to avoid more confusion I suppose one thing that could be done
> is this:
> - intel_tile_width
> + intel_tile_width_bytes
>
> intel_tile_dims()
> {
> tile_width_bytes = intel_tile_width_bytes()
> *tile_height = tile_size / tile_width_bytes;
> *tile_width = tile_width_bytes / cpp;
> }
Yeah that sounds reasonable I think.
-Daniel
>
> >
> > No idea really what would be best here ...
> > -Daniel
> >
> > > +}
> > > +
> > > unsigned int
> > > intel_fb_align_height(struct drm_device *dev, unsigned int height,
> > > uint32_t pixel_format, uint64_t fb_modifier)
> > > @@ -2306,19 +2318,19 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
> > > tile_size = intel_tile_size(dev_priv);
> > >
> > > cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > > - tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp);
> > > - tile_height = tile_size / tile_width;
> > > + intel_tile_dims(dev_priv, &tile_width, &tile_height,
> > > + fb->modifier[0], cpp);
> > >
> > > - info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
> > > + info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
> > > info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
> > > info->size = info->width_pages * info->height_pages * tile_size;
> > >
> > > if (info->pixel_format == DRM_FORMAT_NV12) {
> > > cpp = drm_format_plane_cpp(fb->pixel_format, 1);
> > > - tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp);
> > > - tile_height = tile_size / tile_width;
> > > + intel_tile_dims(dev_priv, &tile_width, &tile_height,
> > > + fb->modifier[1], cpp);
> > >
> > > - info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width);
> > > + info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
> > > info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
> > > info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
> > > }
> > > @@ -2446,29 +2458,43 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
> > > i915_gem_object_unpin_from_display_plane(obj, &view);
> > > }
> > >
> > > -/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
> > > - * is assumed to be a power-of-two. */
> > > +/*
> > > + * Computes the linear offset to the base tile and adjusts
> > > + * x, y. bytes per pixel is assumed to be a power-of-two.
> > > + *
> > > + * In the 90/270 rotated case, x and y are assumed
> > > + * to be already rotated to match the rotated GTT view, and
> > > + * pitch is the tile_height aligned framebuffer height.
> > > + */
> > > u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> > > int *x, int *y,
> > > uint64_t fb_modifier,
> > > unsigned int cpp,
> > > - unsigned int pitch)
> > > + unsigned int pitch,
> > > + unsigned int rotation)
> > > {
> > > if (fb_modifier != DRM_FORMAT_MOD_NONE) {
> > > unsigned int tile_size, tile_width, tile_height;
> > > - unsigned int tile_rows, tiles;
> > > + unsigned int tile_rows, tiles, pitch_tiles;
> > >
> > > tile_size = intel_tile_size(dev_priv);
> > > - tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
> > > - tile_height = tile_size / tile_width;
> > > + intel_tile_dims(dev_priv, &tile_width, &tile_height,
> > > + fb_modifier, cpp);
> > > +
> > > + if (intel_rotation_90_or_270(rotation)) {
> > > + pitch_tiles = pitch / tile_height;
> > > + swap(tile_width, tile_height);
> > > + } else {
> > > + pitch_tiles = pitch / (tile_width * cpp);
> > > + }
> > >
> > > tile_rows = *y / tile_height;
> > > *y %= tile_height;
> > >
> > > - tiles = *x / (tile_width/cpp);
> > > - *x %= tile_width/cpp;
> > > + tiles = *x / tile_width;
> > > + *x %= tile_width;
> > >
> > > - return tile_rows * pitch * tile_height + tiles * tile_size;
> > > + return (tile_rows * pitch_tiles + tiles) * tile_size;
> > > } else {
> > > unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
> > > unsigned int offset;
> > > @@ -2709,6 +2735,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> > > u32 linear_offset;
> > > u32 dspcntr;
> > > i915_reg_t reg = DSPCNTR(plane);
> > > + unsigned int rotation = plane_state->base.rotation;
> > > int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > > int x = plane_state->src.x1 >> 16;
> > > int y = plane_state->src.y1 >> 16;
> > > @@ -2775,13 +2802,13 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> > > intel_crtc->dspaddr_offset =
> > > intel_compute_tile_offset(dev_priv, &x, &y,
> > > fb->modifier[0], cpp,
> > > - fb->pitches[0]);
> > > + fb->pitches[0], rotation);
> > > linear_offset -= intel_crtc->dspaddr_offset;
> > > } else {
> > > intel_crtc->dspaddr_offset = linear_offset;
> > > }
> > >
> > > - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> > > + if (rotation == BIT(DRM_ROTATE_180)) {
> > > dspcntr |= DISPPLANE_ROTATE_180;
> > >
> > > x += (crtc_state->pipe_src_w - 1);
> > > @@ -2839,6 +2866,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> > > u32 linear_offset;
> > > u32 dspcntr;
> > > i915_reg_t reg = DSPCNTR(plane);
> > > + unsigned int rotation = plane_state->base.rotation;
> > > int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > > int x = plane_state->src.x1 >> 16;
> > > int y = plane_state->src.y1 >> 16;
> > > @@ -2882,9 +2910,9 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> > > intel_crtc->dspaddr_offset =
> > > intel_compute_tile_offset(dev_priv, &x, &y,
> > > fb->modifier[0], cpp,
> > > - fb->pitches[0]);
> > > + fb->pitches[0], rotation);
> > > linear_offset -= intel_crtc->dspaddr_offset;
> > > - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> > > + if (rotation == BIT(DRM_ROTATE_180)) {
> > > dspcntr |= DISPPLANE_ROTATE_180;
> > >
> > > if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > > index f620023ed134..223693dbfe7c 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1176,7 +1176,8 @@ u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
> > > int *x, int *y,
> > > uint64_t fb_modifier,
> > > unsigned int cpp,
> > > - unsigned int pitch);
> > > + unsigned int pitch,
> > > + unsigned int rotation);
> > > void intel_prepare_reset(struct drm_device *dev);
> > > void intel_finish_reset(struct drm_device *dev);
> > > void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > > index a2582c455b36..7dc2b8b2a4ac 100644
> > > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > > @@ -193,7 +193,7 @@ skl_update_plane(struct drm_plane *drm_plane,
> > > const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > u32 surf_addr;
> > > u32 tile_height, plane_offset, plane_size;
> > > - unsigned int rotation;
> > > + unsigned int rotation = plane_state->base.rotation;
> > > int x_offset, y_offset;
> > > int crtc_x = plane_state->dst.x1;
> > > int crtc_y = plane_state->dst.y1;
> > > @@ -213,7 +213,6 @@ skl_update_plane(struct drm_plane *drm_plane,
> > > plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
> > > plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
> > >
> > > - rotation = plane_state->base.rotation;
> > > plane_ctl |= skl_plane_ctl_rotation(rotation);
> > >
> > > stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
> > > @@ -351,6 +350,7 @@ vlv_update_plane(struct drm_plane *dplane,
> > > int plane = intel_plane->plane;
> > > u32 sprctl;
> > > u32 sprsurf_offset, linear_offset;
> > > + unsigned int rotation = dplane->state->rotation;
> > > int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > > const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > int crtc_x = plane_state->dst.x1;
> > > @@ -425,10 +425,10 @@ vlv_update_plane(struct drm_plane *dplane,
> > > linear_offset = y * fb->pitches[0] + x * cpp;
> > > sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
> > > fb->modifier[0], cpp,
> > > - fb->pitches[0]);
> > > + fb->pitches[0], rotation);
> > > linear_offset -= sprsurf_offset;
> > >
> > > - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> > > + if (rotation == BIT(DRM_ROTATE_180)) {
> > > sprctl |= SP_ROTATE_180;
> > >
> > > x += src_w;
> > > @@ -493,6 +493,7 @@ ivb_update_plane(struct drm_plane *plane,
> > > enum pipe pipe = intel_plane->pipe;
> > > u32 sprctl, sprscale = 0;
> > > u32 sprsurf_offset, linear_offset;
> > > + unsigned int rotation = plane_state->base.rotation;
> > > int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > > const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > int crtc_x = plane_state->dst.x1;
> > > @@ -558,10 +559,10 @@ ivb_update_plane(struct drm_plane *plane,
> > > linear_offset = y * fb->pitches[0] + x * cpp;
> > > sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
> > > fb->modifier[0], cpp,
> > > - fb->pitches[0]);
> > > + fb->pitches[0], rotation);
> > > linear_offset -= sprsurf_offset;
> > >
> > > - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> > > + if (rotation == BIT(DRM_ROTATE_180)) {
> > > sprctl |= SPRITE_ROTATE_180;
> > >
> > > /* HSW and BDW does this automagically in hardware */
> > > @@ -634,6 +635,7 @@ ilk_update_plane(struct drm_plane *plane,
> > > int pipe = intel_plane->pipe;
> > > u32 dvscntr, dvsscale;
> > > u32 dvssurf_offset, linear_offset;
> > > + unsigned int rotation = plane_state->base.rotation;
> > > int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
> > > const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > int crtc_x = plane_state->dst.x1;
> > > @@ -695,10 +697,10 @@ ilk_update_plane(struct drm_plane *plane,
> > > linear_offset = y * fb->pitches[0] + x * cpp;
> > > dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
> > > fb->modifier[0], cpp,
> > > - fb->pitches[0]);
> > > + fb->pitches[0], rotation);
> > > linear_offset -= dvssurf_offset;
> > >
> > > - if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
> > > + if (rotation == BIT(DRM_ROTATE_180)) {
> > > dvscntr |= DVS_ROTATE_180;
> > >
> > > x += src_w;
> > > --
> > > 2.4.10
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
>
> --
> Ville Syrjälä
> Intel OTC
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Thread overview: 50+ messages (download: mbox.gz follow: Atom feed
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2016-01-20 19:05 [PATCH v2 00/18] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) ville.syrjala
2016-01-20 19:05 ` [PATCH 01/18] drm/i915: Rename the rotated gtt view member to 'rotated' ville.syrjala
2016-01-25 16:50 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH 02/18] drm/i915: Pass stride to rotate_pages() ville.syrjala
2016-01-25 16:52 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH 03/18] drm/i915: Pass rotation_info to intel_rotate_fb_obj_pages() ville.syrjala
2016-01-25 16:53 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH 04/18] drm/i915: Make display gtt offsets u32 ville.syrjala
2016-01-25 17:00 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH 05/18] drm/i915: Standardize on 'cpp' for bytes per pixel ville.syrjala
2016-01-25 17:05 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH v2 06/18] drm: Add drm_format_plane_width() and drm_format_plane_height() ville.syrjala
2016-01-25 17:08 ` Daniel Vetter
2016-01-28 18:15 ` Ville Syrjälä
2016-01-29 18:01 ` [PATCH v3 " ville.syrjala
2016-02-09 9:08 ` Daniel Vetter
2016-02-09 15:29 ` [PATCH v4 " ville.syrjala
2016-01-20 19:05 ` [PATCH 07/18] drm/i915: Fix intel_tile_width() parameters ville.syrjala
2016-01-25 17:12 ` Daniel Vetter
2016-01-28 18:35 ` Ville Syrjälä
2016-01-28 19:04 ` Ville Syrjälä
2016-01-20 19:05 ` [PATCH v3 08/18] drm/i915: Pass 90/270 vs. 0/180 rotation info for intel_gen4_compute_page_offset() ville.syrjala
2016-01-25 17:30 ` Daniel Vetter
2016-01-28 18:51 ` Ville Syrjälä
2016-02-10 7:35 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH v2 09/18] drm/i915: Support for extra alignment for tiled surfaces ville.syrjala
2016-01-25 17:24 ` Daniel Vetter
2016-01-25 17:55 ` Ville Syrjälä
2016-01-20 19:05 ` [PATCH v2 10/18] drm/i915: Don't pass plane+plane_state to intel_pin_and_fence_fb_obj() ville.syrjala
2016-01-20 19:05 ` [PATCH 11/18] drm/i915: Pass drm_frambuffer to intel_compute_page_offset() ville.syrjala
2016-01-20 19:05 ` [PATCH 12/18] drm/i915: Reorganize intel_rotation_info ville.syrjala
2016-01-25 17:38 ` Daniel Vetter
2016-01-25 18:03 ` Ville Syrjälä
2016-01-20 19:05 ` [PATCH 13/18] drm/i915: Move the NULL sg handling out from rotate_pages() ville.syrjala
2016-01-25 17:40 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH 14/18] drm/i915: Embed rotation_info under intel_framebuffer ville.syrjala
2016-01-20 21:08 ` Chris Wilson
2016-01-21 12:06 ` Ville Syrjälä
2016-01-21 12:10 ` Chris Wilson
2016-01-25 17:42 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH v3 15/18] drm/i915: Rewrite fb rotation GTT handling ville.syrjala
2016-01-20 19:05 ` [PATCH v2 16/18] drm/i915: Don't pass pitch to intel_compute_page_offset() ville.syrjala
2016-01-25 17:53 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH 17/18] drm/i915: Pass around plane_state instead of fb+rotation ville.syrjala
2016-01-25 17:55 ` Daniel Vetter
2016-01-20 19:05 ` [PATCH v2 18/18] drm/i915: Make sure fb offset is (macro)pixel aligned ville.syrjala
2016-01-21 13:35 ` ✓ Fi.CI.BAT: success for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) Patchwork
2016-01-30 8:31 ` ✗ Fi.CI.BAT: failure for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) (rev2) Patchwork
2016-02-01 8:31 ` Patchwork
2016-02-09 16:31 ` ✗ Fi.CI.BAT: failure for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v2) (rev3) Patchwork
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