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* [PATCH] drm/i915: Skip PIPESTAT reads from irq handler on VLV/CHV when power well is down
@ 2016-02-18 19:54 ville.syrjala
  2016-02-19  8:20 ` ✗ Fi.CI.BAT: failure for " Patchwork
  2016-02-19 15:37 ` [PATCH] " Imre Deak
  0 siblings, 2 replies; 7+ messages in thread
From: ville.syrjala @ 2016-02-18 19:54 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

PIPESTAT registers live in the display power well on VLV/CHV, so we
shouldn't access them when things are powered down. Let's check
whether the display interrupts are on or off before accessing the
PIPESTAT registers.

Another option would be to read the PIPESTAT registers only when
the IIR register indicates that there's a pending pipe event. But
that would mean we might miss even more underrun reports than we
do now, because the underrun status bit lives in PIPESTAT but doesn't
actually generate an interrupt.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93738
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 25a89373df63..d56c261ad867 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1651,6 +1651,12 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
 	int pipe;
 
 	spin_lock(&dev_priv->irq_lock);
+
+	if (!dev_priv->display_irqs_enabled) {
+		spin_unlock(&dev_priv->irq_lock);
+		return;
+	}
+
 	for_each_pipe(dev_priv, pipe) {
 		i915_reg_t reg;
 		u32 mask, iir_bit = 0;
-- 
2.4.10

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^ permalink raw reply related	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2016-02-22 17:46 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-02-18 19:54 [PATCH] drm/i915: Skip PIPESTAT reads from irq handler on VLV/CHV when power well is down ville.syrjala
2016-02-19  8:20 ` ✗ Fi.CI.BAT: failure for " Patchwork
2016-02-19 19:28   ` Ville Syrjälä
2016-02-22 15:42   ` Ville Syrjälä
2016-02-19 15:37 ` [PATCH] " Imre Deak
2016-02-19 15:50   ` Ville Syrjälä
2016-02-22 17:46   ` Ville Syrjälä

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