From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915: Add for_each_pipe_masked()
Date: Mon, 22 Feb 2016 19:47:10 +0200 [thread overview]
Message-ID: <20160222174710.GE23290@intel.com> (raw)
In-Reply-To: <1456150713.9487.14.camel@intel.com>
On Mon, Feb 22, 2016 at 04:18:33PM +0200, Imre Deak wrote:
> On pe, 2016-02-19 at 20:47 +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > for_each_pipe_masked() can be used to iterate over the pipes
> > included in the user provided pipe mask. Removes a few lines of
> > duplicated code.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
Series pushed to dinq. Thanks for the review.
>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 3 +++
> > drivers/gpu/drm/i915/i915_irq.c | 27 +++++++++------------------
> > 2 files changed, 12 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 6644c2e354c1..00ab9c0e18e0 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -261,6 +261,9 @@ struct i915_hotplug {
> >
> > #define for_each_pipe(__dev_priv, __p) \
> > for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes;
> > (__p)++)
> > +#define for_each_pipe_masked(__dev_priv, __p, __mask) \
> > + for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes;
> > (__p)++) \
> > + for_each_if ((__mask) & (1 << (__p)))
> > #define for_each_plane(__dev_priv, __pipe, __p)
> > \
> > for ((__p) = 0;
> > \
> > (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] +
> > 1; \
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index a9048e1b96e5..d1a46ef5ab3f 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3349,33 +3349,24 @@ void gen8_irq_power_well_post_enable(struct
> > drm_i915_private *dev_priv,
> > unsigned int pipe_mask)
> > {
> > uint32_t extra_ier = GEN8_PIPE_VBLANK |
> > GEN8_PIPE_FIFO_UNDERRUN;
> > + enum pipe pipe;
> >
> > spin_lock_irq(&dev_priv->irq_lock);
> > - if (pipe_mask & 1 << PIPE_A)
> > - GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
> > - dev_priv->de_irq_mask[PIPE_A],
> > - ~dev_priv->de_irq_mask[PIPE_A] |
> > extra_ier);
> > - if (pipe_mask & 1 << PIPE_B)
> > - GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
> > - dev_priv->de_irq_mask[PIPE_B],
> > - ~dev_priv->de_irq_mask[PIPE_B] |
> > extra_ier);
> > - if (pipe_mask & 1 << PIPE_C)
> > - GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
> > - dev_priv->de_irq_mask[PIPE_C],
> > - ~dev_priv->de_irq_mask[PIPE_C] |
> > extra_ier);
> > + for_each_pipe_masked(dev_priv, pipe, pipe_mask)
> > + GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
> > + dev_priv->de_irq_mask[pipe],
> > + ~dev_priv->de_irq_mask[pipe] |
> > extra_ier);
> > spin_unlock_irq(&dev_priv->irq_lock);
> > }
> >
> > void gen8_irq_power_well_pre_disable(struct drm_i915_private
> > *dev_priv,
> > unsigned int pipe_mask)
> > {
> > + enum pipe pipe;
> > +
> > spin_lock_irq(&dev_priv->irq_lock);
> > - if (pipe_mask & 1 << PIPE_A)
> > - GEN8_IRQ_RESET_NDX(DE_PIPE, PIPE_A);
> > - if (pipe_mask & 1 << PIPE_B)
> > - GEN8_IRQ_RESET_NDX(DE_PIPE, PIPE_B);
> > - if (pipe_mask & 1 << PIPE_C)
> > - GEN8_IRQ_RESET_NDX(DE_PIPE, PIPE_C);
> > + for_each_pipe_masked(dev_priv, pipe, pipe_mask)
> > + GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
> > spin_unlock_irq(&dev_priv->irq_lock);
> >
> > /* make sure we're done processing display irqs */
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2016-02-22 17:47 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-19 18:47 [PATCH 1/2] drm/i915: Make sure pipe interrupts are processed before turning off power well on BDW+ ville.syrjala
2016-02-19 18:47 ` [PATCH 2/2] drm/i915: Add for_each_pipe_masked() ville.syrjala
2016-02-22 14:18 ` Imre Deak
2016-02-22 17:47 ` Ville Syrjälä [this message]
2016-02-22 11:18 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Make sure pipe interrupts are processed before turning off power well on BDW+ Patchwork
2016-02-22 14:59 ` Ville Syrjälä
2016-02-22 13:59 ` [PATCH 1/2] " Imre Deak
2016-02-22 14:16 ` Ville Syrjälä
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