* [PATCH 1/6] drm/i915: Dump ddi_pll_sel in hex instead of decimal on HSW/BDW
2016-02-17 19:41 [PATCH 0/6] drm/i915: Some FDI related dotclock stuff ville.syrjala
@ 2016-02-17 19:41 ` ville.syrjala
2016-02-18 13:19 ` Imre Deak
2016-02-17 19:41 ` [PATCH 2/6] drm/i915: Move the encoder vs. FDI dotclock check out from encoder .get_config() ville.syrjala
` (6 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: ville.syrjala @ 2016-02-17 19:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On HSW/BDW ddi_pll_sel is the actual register value. Let's dump
it in hex so that people migth actually understand what it says.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index afcabe455ad1..f0f88061a9e5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12220,7 +12220,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
pipe_config->dpll_hw_state.cfgcr1,
pipe_config->dpll_hw_state.cfgcr2);
} else if (HAS_DDI(dev)) {
- DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
+ DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
pipe_config->ddi_pll_sel,
pipe_config->dpll_hw_state.wrpll,
pipe_config->dpll_hw_state.spll);
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/6] drm/i915: Dump ddi_pll_sel in hex instead of decimal on HSW/BDW
2016-02-17 19:41 ` [PATCH 1/6] drm/i915: Dump ddi_pll_sel in hex instead of decimal on HSW/BDW ville.syrjala
@ 2016-02-18 13:19 ` Imre Deak
0 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2016-02-18 13:19 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On ke, 2016-02-17 at 21:41 +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On HSW/BDW ddi_pll_sel is the actual register value. Let's dump
> it in hex so that people migth actually understand what it says.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index afcabe455ad1..f0f88061a9e5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12220,7 +12220,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> pipe_config->dpll_hw_state.cfgcr1,
> pipe_config->dpll_hw_state.cfgcr2);
> } else if (HAS_DDI(dev)) {
> - DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
> + DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
> pipe_config->ddi_pll_sel,
> pipe_config->dpll_hw_state.wrpll,
> pipe_config->dpll_hw_state.spll);
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/6] drm/i915: Move the encoder vs. FDI dotclock check out from encoder .get_config()
2016-02-17 19:41 [PATCH 0/6] drm/i915: Some FDI related dotclock stuff ville.syrjala
2016-02-17 19:41 ` [PATCH 1/6] drm/i915: Dump ddi_pll_sel in hex instead of decimal on HSW/BDW ville.syrjala
@ 2016-02-17 19:41 ` ville.syrjala
2016-02-18 18:18 ` Imre Deak
2016-02-17 19:41 ` [PATCH 3/6] drm/i915: Remove the SPLL==270Mhz assumption from intel_fdi_link_freq() ville.syrjala
` (5 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: ville.syrjala @ 2016-02-17 19:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently we check if the encoder's idea of dotclock agrees with what
we calculated based on the FDI parameters. We do this in the encoder
.get_config() hooks, which isn't so nice in case the BIOS (or some other
outside party) made a mess of the state and we're just trying to take
over.
So as a prep step to being able sanitize such a bogus state, move the
the sanity check to just after we've read out the entire state. If
we then need to sanitize a bad state, it should be easier to move the
sanity check to occur after sanitation instead of before it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_crt.c | 10 +------
drivers/gpu/drm/i915/intel_display.c | 57 ++++++++++++++++++++----------------
drivers/gpu/drm/i915/intel_dp.c | 11 ++-----
drivers/gpu/drm/i915/intel_drv.h | 3 --
drivers/gpu/drm/i915/intel_hdmi.c | 3 --
drivers/gpu/drm/i915/intel_lvds.c | 8 +----
drivers/gpu/drm/i915/intel_sdvo.c | 4 +--
7 files changed, 38 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index e686a91a416e..f4c88d93a164 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -120,17 +120,9 @@ static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
static void intel_crt_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
- struct drm_device *dev = encoder->base.dev;
- int dotclock;
-
pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
- dotclock = pipe_config->port_clock;
-
- if (HAS_PCH_SPLIT(dev))
- ironlake_check_encoder_dotclock(pipe_config, dotclock);
-
- pipe_config->base.adjusted_mode.crtc_clock = dotclock;
+ pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
}
static void hsw_crt_get_config(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f0f88061a9e5..99001e117517 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -224,12 +224,11 @@ static void intel_update_czclk(struct drm_i915_private *dev_priv)
}
static inline u32 /* units of 100MHz */
-intel_fdi_link_freq(struct drm_device *dev)
+intel_fdi_link_freq(struct drm_i915_private *dev_priv)
{
- if (IS_GEN5(dev)) {
- struct drm_i915_private *dev_priv = dev->dev_private;
+ if (IS_GEN5(dev_priv))
return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
- } else
+ else
return 27;
}
@@ -6589,7 +6588,7 @@ retry:
* Hence the bw of each lane in terms of the mode signal
* is:
*/
- link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
+ link_bw = intel_fdi_link_freq(to_i915(dev)) * MHz(100)/KHz(1)/10;
fdi_dotclock = adjusted_mode->crtc_clock;
@@ -6601,8 +6600,7 @@ retry:
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
link_bw, &pipe_config->fdi_m_n);
- ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
- intel_crtc->pipe, pipe_config);
+ ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
pipe_config->pipe_bpp -= 2*3;
DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
@@ -10765,19 +10763,18 @@ int intel_dotclock_calculate(int link_freq,
static void ironlake_pch_clock_get(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
- struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
/* read out port_clock from the DPLL */
i9xx_crtc_clock_get(crtc, pipe_config);
/*
- * This value does not include pixel_multiplier.
- * We will check that port_clock and adjusted_mode.crtc_clock
- * agree once we know their relationship in the encoder's
- * get_config() function.
+ * In case there is an active pipe without active ports,
+ * we may need some idea for the dotclock anyway.
+ * Calculate one based on the FDI configuration.
*/
pipe_config->base.adjusted_mode.crtc_clock =
- intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
+ intel_dotclock_calculate(intel_fdi_link_freq(dev_priv) * 10000,
&pipe_config->fdi_m_n);
}
@@ -12788,6 +12785,24 @@ intel_pipe_config_compare(struct drm_device *dev,
return ret;
}
+static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *pipe_config)
+{
+ if (pipe_config->has_pch_encoder) {
+ int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv) * 10000,
+ &pipe_config->fdi_m_n);
+ int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
+
+ /*
+ * FDI already provided one idea for the dotclock.
+ * Yell if the encoder disagrees.
+ */
+ WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
+ "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
+ fdi_dotclock, dotclock);
+ }
+}
+
static void check_wm_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -12961,6 +12976,8 @@ check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
if (!crtc->state->active)
continue;
+ intel_pipe_config_sanity_check(dev_priv, pipe_config);
+
sw_config = to_intel_crtc_state(crtc->state);
if (!intel_pipe_config_compare(dev, sw_config,
pipe_config, false)) {
@@ -13033,18 +13050,6 @@ intel_modeset_check_state(struct drm_device *dev,
check_shared_dpll_state(dev);
}
-void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
- int dotclock)
-{
- /*
- * FDI already provided one idea for the dotclock.
- * Yell if the encoder disagrees.
- */
- WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
- "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
- pipe_config->base.adjusted_mode.crtc_clock, dotclock);
-}
-
static void update_scanline_offset(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
@@ -15847,6 +15852,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
update_scanline_offset(crtc);
}
+
+ intel_pipe_config_sanity_check(dev_priv, crtc->config);
}
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cbc06596659a..f272b3541e00 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2409,7 +2409,6 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = dev->dev_private;
enum port port = dp_to_dig_port(intel_dp)->port;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
- int dotclock;
tmp = I915_READ(intel_dp->output_reg);
@@ -2459,13 +2458,9 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
pipe_config->port_clock = 270000;
}
- dotclock = intel_dotclock_calculate(pipe_config->port_clock,
- &pipe_config->dp_m_n);
-
- if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
- ironlake_check_encoder_dotclock(pipe_config, dotclock);
-
- pipe_config->base.adjusted_mode.crtc_clock = dotclock;
+ pipe_config->base.adjusted_mode.crtc_clock =
+ intel_dotclock_calculate(pipe_config->port_clock,
+ &pipe_config->dp_m_n);
if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f95f8b22939f..c25a8880b4e8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1197,9 +1197,6 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
-void
-ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
- int dotclock);
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
intel_clock_t *best_clock);
int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 80b44c054087..d8060e6251f8 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -952,9 +952,6 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
if (pipe_config->pixel_multiplier)
dotclock /= pipe_config->pixel_multiplier;
- if (HAS_PCH_SPLIT(dev_priv->dev))
- ironlake_check_encoder_dotclock(pipe_config, dotclock);
-
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
}
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 30a8403a8f4f..b35342f7b969 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -109,7 +109,6 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
u32 tmp, flags = 0;
- int dotclock;
tmp = I915_READ(lvds_encoder->reg);
if (tmp & LVDS_HSYNC_POLARITY)
@@ -130,12 +129,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
}
- dotclock = pipe_config->port_clock;
-
- if (HAS_PCH_SPLIT(dev_priv->dev))
- ironlake_check_encoder_dotclock(pipe_config, dotclock);
-
- pipe_config->base.adjusted_mode.crtc_clock = dotclock;
+ pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
}
static void intel_pre_enable_lvds(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 4ecc076c4041..fae64bc93c1b 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1398,12 +1398,10 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
}
dotclock = pipe_config->port_clock;
+
if (pipe_config->pixel_multiplier)
dotclock /= pipe_config->pixel_multiplier;
- if (HAS_PCH_SPLIT(dev))
- ironlake_check_encoder_dotclock(pipe_config, dotclock);
-
pipe_config->base.adjusted_mode.crtc_clock = dotclock;
/* Cross check the port pixel multiplier with the sdvo encoder state. */
--
2.4.10
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 2/6] drm/i915: Move the encoder vs. FDI dotclock check out from encoder .get_config()
2016-02-17 19:41 ` [PATCH 2/6] drm/i915: Move the encoder vs. FDI dotclock check out from encoder .get_config() ville.syrjala
@ 2016-02-18 18:18 ` Imre Deak
0 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2016-02-18 18:18 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On ke, 2016-02-17 at 21:41 +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Currently we check if the encoder's idea of dotclock agrees with what
> we calculated based on the FDI parameters. We do this in the encoder
> .get_config() hooks, which isn't so nice in case the BIOS (or some
> other
> outside party) made a mess of the state and we're just trying to take
> over.
>
> So as a prep step to being able sanitize such a bogus state, move the
> the sanity check to just after we've read out the entire state. If
> we then need to sanitize a bad state, it should be easier to move the
> sanity check to occur after sanitation instead of before it.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Separating the get-config and check steps makes things more logical in
any case. Looks ok to me:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_crt.c | 10 +------
> drivers/gpu/drm/i915/intel_display.c | 57 ++++++++++++++++++++----
> ------------
> drivers/gpu/drm/i915/intel_dp.c | 11 ++-----
> drivers/gpu/drm/i915/intel_drv.h | 3 --
> drivers/gpu/drm/i915/intel_hdmi.c | 3 --
> drivers/gpu/drm/i915/intel_lvds.c | 8 +----
> drivers/gpu/drm/i915/intel_sdvo.c | 4 +--
> 7 files changed, 38 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> b/drivers/gpu/drm/i915/intel_crt.c
> index e686a91a416e..f4c88d93a164 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -120,17 +120,9 @@ static unsigned int intel_crt_get_flags(struct
> intel_encoder *encoder)
> static void intel_crt_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state
> *pipe_config)
> {
> - struct drm_device *dev = encoder->base.dev;
> - int dotclock;
> -
> pipe_config->base.adjusted_mode.flags |=
> intel_crt_get_flags(encoder);
>
> - dotclock = pipe_config->port_clock;
> -
> - if (HAS_PCH_SPLIT(dev))
> - ironlake_check_encoder_dotclock(pipe_config,
> dotclock);
> -
> - pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> + pipe_config->base.adjusted_mode.crtc_clock = pipe_config-
> >port_clock;
> }
>
> static void hsw_crt_get_config(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index f0f88061a9e5..99001e117517 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -224,12 +224,11 @@ static void intel_update_czclk(struct
> drm_i915_private *dev_priv)
> }
>
> static inline u32 /* units of 100MHz */
> -intel_fdi_link_freq(struct drm_device *dev)
> +intel_fdi_link_freq(struct drm_i915_private *dev_priv)
> {
> - if (IS_GEN5(dev)) {
> - struct drm_i915_private *dev_priv = dev-
> >dev_private;
> + if (IS_GEN5(dev_priv))
> return (I915_READ(FDI_PLL_BIOS_0) &
> FDI_PLL_FB_CLOCK_MASK) + 2;
> - } else
> + else
> return 27;
> }
>
> @@ -6589,7 +6588,7 @@ retry:
> * Hence the bw of each lane in terms of the mode signal
> * is:
> */
> - link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
> + link_bw = intel_fdi_link_freq(to_i915(dev)) *
> MHz(100)/KHz(1)/10;
>
> fdi_dotclock = adjusted_mode->crtc_clock;
>
> @@ -6601,8 +6600,7 @@ retry:
> intel_link_compute_m_n(pipe_config->pipe_bpp, lane,
> fdi_dotclock,
> link_bw, &pipe_config->fdi_m_n);
>
> - ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
> - intel_crtc->pipe,
> pipe_config);
> + ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe,
> pipe_config);
> if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
> pipe_config->pipe_bpp -= 2*3;
> DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe
> bpp to %i\n",
> @@ -10765,19 +10763,18 @@ int intel_dotclock_calculate(int link_freq,
> static void ironlake_pch_clock_get(struct intel_crtc *crtc,
> struct intel_crtc_state
> *pipe_config)
> {
> - struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> /* read out port_clock from the DPLL */
> i9xx_crtc_clock_get(crtc, pipe_config);
>
> /*
> - * This value does not include pixel_multiplier.
> - * We will check that port_clock and
> adjusted_mode.crtc_clock
> - * agree once we know their relationship in the encoder's
> - * get_config() function.
> + * In case there is an active pipe without active ports,
> + * we may need some idea for the dotclock anyway.
> + * Calculate one based on the FDI configuration.
> */
> pipe_config->base.adjusted_mode.crtc_clock =
> - intel_dotclock_calculate(intel_fdi_link_freq(dev) *
> 10000,
> + intel_dotclock_calculate(intel_fdi_link_freq(dev_pri
> v) * 10000,
> &pipe_config->fdi_m_n);
> }
>
> @@ -12788,6 +12785,24 @@ intel_pipe_config_compare(struct drm_device
> *dev,
> return ret;
> }
>
> +static void intel_pipe_config_sanity_check(struct drm_i915_private
> *dev_priv,
> + const struct
> intel_crtc_state *pipe_config)
> +{
> + if (pipe_config->has_pch_encoder) {
> + int fdi_dotclock =
> intel_dotclock_calculate(intel_fdi_link_freq(dev_priv) * 10000,
> + &pipe_co
> nfig->fdi_m_n);
> + int dotclock = pipe_config-
> >base.adjusted_mode.crtc_clock;
> +
> + /*
> + * FDI already provided one idea for the dotclock.
> + * Yell if the encoder disagrees.
> + */
> + WARN(!intel_fuzzy_clock_check(fdi_dotclock,
> dotclock),
> + "FDI dotclock and encoder dotclock mismatch,
> fdi: %i, encoder: %i\n",
> + fdi_dotclock, dotclock);
> + }
> +}
> +
> static void check_wm_state(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -12961,6 +12976,8 @@ check_crtc_state(struct drm_device *dev,
> struct drm_atomic_state *old_state)
> if (!crtc->state->active)
> continue;
>
> + intel_pipe_config_sanity_check(dev_priv,
> pipe_config);
> +
> sw_config = to_intel_crtc_state(crtc->state);
> if (!intel_pipe_config_compare(dev, sw_config,
> pipe_config, false))
> {
> @@ -13033,18 +13050,6 @@ intel_modeset_check_state(struct drm_device
> *dev,
> check_shared_dpll_state(dev);
> }
>
> -void ironlake_check_encoder_dotclock(const struct intel_crtc_state
> *pipe_config,
> - int dotclock)
> -{
> - /*
> - * FDI already provided one idea for the dotclock.
> - * Yell if the encoder disagrees.
> - */
> - WARN(!intel_fuzzy_clock_check(pipe_config-
> >base.adjusted_mode.crtc_clock, dotclock),
> - "FDI dotclock and encoder dotclock mismatch, fdi: %i,
> encoder: %i\n",
> - pipe_config->base.adjusted_mode.crtc_clock, dotclock);
> -}
> -
> static void update_scanline_offset(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> @@ -15847,6 +15852,8 @@ static void
> intel_modeset_readout_hw_state(struct drm_device *dev)
> drm_calc_timestamping_constants(&crtc->base,
> &crtc->base.hwmode);
> update_scanline_offset(crtc);
> }
> +
> + intel_pipe_config_sanity_check(dev_priv, crtc-
> >config);
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index cbc06596659a..f272b3541e00 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2409,7 +2409,6 @@ static void intel_dp_get_config(struct
> intel_encoder *encoder,
> struct drm_i915_private *dev_priv = dev->dev_private;
> enum port port = dp_to_dig_port(intel_dp)->port;
> struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> - int dotclock;
>
> tmp = I915_READ(intel_dp->output_reg);
>
> @@ -2459,13 +2458,9 @@ static void intel_dp_get_config(struct
> intel_encoder *encoder,
> pipe_config->port_clock = 270000;
> }
>
> - dotclock = intel_dotclock_calculate(pipe_config->port_clock,
> - &pipe_config->dp_m_n);
> -
> - if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
> - ironlake_check_encoder_dotclock(pipe_config,
> dotclock);
> -
> - pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> + pipe_config->base.adjusted_mode.crtc_clock =
> + intel_dotclock_calculate(pipe_config->port_clock,
> + &pipe_config->dp_m_n);
>
> if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
> pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index f95f8b22939f..c25a8880b4e8 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1197,9 +1197,6 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config);
> void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set
> m_n);
> int intel_dotclock_calculate(int link_freq, const struct
> intel_link_m_n *m_n);
> -void
> -ironlake_check_encoder_dotclock(const struct intel_crtc_state
> *pipe_config,
> - int dotclock);
> bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int
> target_clock,
> intel_clock_t *best_clock);
> int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 80b44c054087..d8060e6251f8 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -952,9 +952,6 @@ static void intel_hdmi_get_config(struct
> intel_encoder *encoder,
> if (pipe_config->pixel_multiplier)
> dotclock /= pipe_config->pixel_multiplier;
>
> - if (HAS_PCH_SPLIT(dev_priv->dev))
> - ironlake_check_encoder_dotclock(pipe_config,
> dotclock);
> -
> pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c
> b/drivers/gpu/drm/i915/intel_lvds.c
> index 30a8403a8f4f..b35342f7b969 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -109,7 +109,6 @@ static void intel_lvds_get_config(struct
> intel_encoder *encoder,
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_lvds_encoder *lvds_encoder =
> to_lvds_encoder(&encoder->base);
> u32 tmp, flags = 0;
> - int dotclock;
>
> tmp = I915_READ(lvds_encoder->reg);
> if (tmp & LVDS_HSYNC_POLARITY)
> @@ -130,12 +129,7 @@ static void intel_lvds_get_config(struct
> intel_encoder *encoder,
> pipe_config->gmch_pfit.control |= tmp &
> PANEL_8TO6_DITHER_ENABLE;
> }
>
> - dotclock = pipe_config->port_clock;
> -
> - if (HAS_PCH_SPLIT(dev_priv->dev))
> - ironlake_check_encoder_dotclock(pipe_config,
> dotclock);
> -
> - pipe_config->base.adjusted_mode.crtc_clock = dotclock;
> + pipe_config->base.adjusted_mode.crtc_clock = pipe_config-
> >port_clock;
> }
>
> static void intel_pre_enable_lvds(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c
> b/drivers/gpu/drm/i915/intel_sdvo.c
> index 4ecc076c4041..fae64bc93c1b 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -1398,12 +1398,10 @@ static void intel_sdvo_get_config(struct
> intel_encoder *encoder,
> }
>
> dotclock = pipe_config->port_clock;
> +
> if (pipe_config->pixel_multiplier)
> dotclock /= pipe_config->pixel_multiplier;
>
> - if (HAS_PCH_SPLIT(dev))
> - ironlake_check_encoder_dotclock(pipe_config,
> dotclock);
> -
> pipe_config->base.adjusted_mode.crtc_clock = dotclock;
>
> /* Cross check the port pixel multiplier with the sdvo
> encoder state. */
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/6] drm/i915: Remove the SPLL==270Mhz assumption from intel_fdi_link_freq()
2016-02-17 19:41 [PATCH 0/6] drm/i915: Some FDI related dotclock stuff ville.syrjala
2016-02-17 19:41 ` [PATCH 1/6] drm/i915: Dump ddi_pll_sel in hex instead of decimal on HSW/BDW ville.syrjala
2016-02-17 19:41 ` [PATCH 2/6] drm/i915: Move the encoder vs. FDI dotclock check out from encoder .get_config() ville.syrjala
@ 2016-02-17 19:41 ` ville.syrjala
2016-02-18 18:28 ` Imre Deak
2016-02-17 19:41 ` [PATCH 4/6] drm/i915: Make the LPT iclkip 20MHz case more generic ville.syrjala
` (4 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: ville.syrjala @ 2016-02-17 19:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Instead of assuming we've correctly set up SPLL to run at 270Mhz for
FDI, let's use the port_clock from pipe_config which should be what
we want. This would catch problems if someone misconfigures SPLL for
whatever reason.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 99001e117517..a3c959cd8b3b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -224,12 +224,15 @@ static void intel_update_czclk(struct drm_i915_private *dev_priv)
}
static inline u32 /* units of 100MHz */
-intel_fdi_link_freq(struct drm_i915_private *dev_priv)
+intel_fdi_link_freq(struct drm_i915_private *dev_priv,
+ const struct intel_crtc_state *pipe_config)
{
- if (IS_GEN5(dev_priv))
- return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
+ if (HAS_DDI(dev_priv))
+ return pipe_config->port_clock; /* SPLL */
+ else if (IS_GEN5(dev_priv))
+ return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
else
- return 27;
+ return 270000;
}
static const intel_limit_t intel_limits_i8xx_dac = {
@@ -6588,7 +6591,7 @@ retry:
* Hence the bw of each lane in terms of the mode signal
* is:
*/
- link_bw = intel_fdi_link_freq(to_i915(dev)) * MHz(100)/KHz(1)/10;
+ link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
fdi_dotclock = adjusted_mode->crtc_clock;
@@ -10774,7 +10777,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
* Calculate one based on the FDI configuration.
*/
pipe_config->base.adjusted_mode.crtc_clock =
- intel_dotclock_calculate(intel_fdi_link_freq(dev_priv) * 10000,
+ intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
&pipe_config->fdi_m_n);
}
@@ -12789,7 +12792,7 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *pipe_config)
{
if (pipe_config->has_pch_encoder) {
- int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv) * 10000,
+ int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
&pipe_config->fdi_m_n);
int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
--
2.4.10
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 3/6] drm/i915: Remove the SPLL==270Mhz assumption from intel_fdi_link_freq()
2016-02-17 19:41 ` [PATCH 3/6] drm/i915: Remove the SPLL==270Mhz assumption from intel_fdi_link_freq() ville.syrjala
@ 2016-02-18 18:28 ` Imre Deak
0 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2016-02-18 18:28 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On ke, 2016-02-17 at 21:41 +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Instead of assuming we've correctly set up SPLL to run at 270Mhz for
> FDI, let's use the port_clock from pipe_config which should be what
> we want. This would catch problems if someone misconfigures SPLL for
> whatever reason.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 17 ++++++++++-------
> 1 file changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 99001e117517..a3c959cd8b3b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -224,12 +224,15 @@ static void intel_update_czclk(struct
> drm_i915_private *dev_priv)
> }
>
> static inline u32 /* units of 100MHz */
> -intel_fdi_link_freq(struct drm_i915_private *dev_priv)
> +intel_fdi_link_freq(struct drm_i915_private *dev_priv,
> + const struct intel_crtc_state *pipe_config)
> {
> - if (IS_GEN5(dev_priv))
> - return (I915_READ(FDI_PLL_BIOS_0) &
> FDI_PLL_FB_CLOCK_MASK) + 2;
> + if (HAS_DDI(dev_priv))
> + return pipe_config->port_clock; /* SPLL */
> + else if (IS_GEN5(dev_priv))
> + return ((I915_READ(FDI_PLL_BIOS_0) &
> FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
> else
> - return 27;
> + return 270000;
> }
>
> static const intel_limit_t intel_limits_i8xx_dac = {
> @@ -6588,7 +6591,7 @@ retry:
> * Hence the bw of each lane in terms of the mode signal
> * is:
> */
> - link_bw = intel_fdi_link_freq(to_i915(dev)) *
> MHz(100)/KHz(1)/10;
> + link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
>
> fdi_dotclock = adjusted_mode->crtc_clock;
>
> @@ -10774,7 +10777,7 @@ static void ironlake_pch_clock_get(struct
> intel_crtc *crtc,
> * Calculate one based on the FDI configuration.
> */
> pipe_config->base.adjusted_mode.crtc_clock =
> - intel_dotclock_calculate(intel_fdi_link_freq(dev_pri
> v) * 10000,
> + intel_dotclock_calculate(intel_fdi_link_freq(dev_pri
> v, pipe_config),
> &pipe_config->fdi_m_n);
> }
>
> @@ -12789,7 +12792,7 @@ static void
> intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
> const struct
> intel_crtc_state *pipe_config)
> {
> if (pipe_config->has_pch_encoder) {
> - int fdi_dotclock =
> intel_dotclock_calculate(intel_fdi_link_freq(dev_priv) * 10000,
> + int fdi_dotclock =
> intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
> &pipe_co
> nfig->fdi_m_n);
> int dotclock = pipe_config-
> >base.adjusted_mode.crtc_clock;
>
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/6] drm/i915: Make the LPT iclkip 20MHz case more generic
2016-02-17 19:41 [PATCH 0/6] drm/i915: Some FDI related dotclock stuff ville.syrjala
` (2 preceding siblings ...)
2016-02-17 19:41 ` [PATCH 3/6] drm/i915: Remove the SPLL==270Mhz assumption from intel_fdi_link_freq() ville.syrjala
@ 2016-02-17 19:41 ` ville.syrjala
2016-02-19 13:54 ` Zanoni, Paulo R
2016-02-19 14:04 ` Imre Deak
2016-02-17 19:41 ` [PATCH 5/6] drm/i915: Read out VGA dotclock properly on LPT ville.syrjala
` (3 subsequent siblings)
7 siblings, 2 replies; 17+ messages in thread
From: ville.syrjala @ 2016-02-17 19:41 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The reason for spcial casing 20MHz in the iclkip calculations is that
it would overflow the 7 bit divisor value. Let's rewrite the special
case to check for just that, and bump up auxdiv when needed. This makes
the code work for freqeuencies close to but not exactly 20MHz. The real
lower limit for auxdiv=0 is actually:
172800000/(0x7f+2)*64)=~20930 kHz, and below that we must resort to
auxdiv=1.
Actually this is all very theoretical since we limit the dotclock to
min 25MHz with CRT on all platforms. 25Mhz is actually the documented
limit in Bspec, so it seems we ought to never need to worry about the
auxdiv=1 case. But no harm in having it.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 40 +++++++++++++++++-------------------
1 file changed, 19 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a3c959cd8b3b..5e7b22a31098 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3957,37 +3957,35 @@ static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
/* Program iCLKIP clock to the desired frequency */
static void lpt_program_iclkip(struct drm_crtc *crtc)
{
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
u32 divsel, phaseinc, auxdiv, phasedir = 0;
u32 temp;
lpt_disable_iclkip(dev_priv);
- /* 20MHz is a corner case which is out of range for the 7-bit divisor */
- if (clock == 20000) {
- auxdiv = 1;
- divsel = 0x41;
- phaseinc = 0x20;
- } else {
- /* The iCLK virtual clock root frequency is in MHz,
- * but the adjusted_mode->crtc_clock in in KHz. To get the
- * divisors, it is necessary to divide one by another, so we
- * convert the virtual clock precision to KHz here for higher
- * precision.
- */
+ /* The iCLK virtual clock root frequency is in MHz,
+ * but the adjusted_mode->crtc_clock in in KHz. To get the
+ * divisors, it is necessary to divide one by another, so we
+ * convert the virtual clock precision to KHz here for higher
+ * precision.
+ */
+ for (auxdiv = 0; auxdiv < 2; auxdiv++) {
u32 iclk_virtual_root_freq = 172800 * 1000;
u32 iclk_pi_range = 64;
- u32 desired_divisor, msb_divisor_value, pi_value;
+ u32 desired_divisor;
- desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
- msb_divisor_value = desired_divisor / iclk_pi_range;
- pi_value = desired_divisor % iclk_pi_range;
+ desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
+ clock << auxdiv);
+ divsel = (desired_divisor / iclk_pi_range) - 2;
+ phaseinc = desired_divisor % iclk_pi_range;
- auxdiv = 0;
- divsel = msb_divisor_value - 2;
- phaseinc = pi_value;
+ /*
+ * Near 20MHz is a corner case which is
+ * out of range for the 7-bit divisor
+ */
+ if (divsel <= 0x7f)
+ break;
}
/* This should not happen with any sane values */
--
2.4.10
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 4/6] drm/i915: Make the LPT iclkip 20MHz case more generic
2016-02-17 19:41 ` [PATCH 4/6] drm/i915: Make the LPT iclkip 20MHz case more generic ville.syrjala
@ 2016-02-19 13:54 ` Zanoni, Paulo R
2016-02-19 14:04 ` Imre Deak
1 sibling, 0 replies; 17+ messages in thread
From: Zanoni, Paulo R @ 2016-02-19 13:54 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Em Qua, 2016-02-17 às 21:41 +0200, ville.syrjala@linux.intel.com
escreveu:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The reason for spcial casing 20MHz in the iclkip calculations is that
> it would overflow the 7 bit divisor value. Let's rewrite the special
> case to check for just that, and bump up auxdiv when needed. This
> makes
> the code work for freqeuencies close to but not exactly 20MHz. The
> real
> lower limit for auxdiv=0 is actually:
> 172800000/(0x7f+2)*64)=~20930 kHz, and below that we must resort to
> auxdiv=1.
>
> Actually this is all very theoretical since we limit the dotclock to
> min 25MHz with CRT on all platforms. 25Mhz is actually the documented
> limit in Bspec, so it seems we ought to never need to worry about the
> auxdiv=1 case. But no harm in having it.
I like the patch and it looks correct. The main "advantage" of the
previous version is that it matched the spec exactly, so future code
readers may be confused now. Maybe a little comment more explicitly
explaining why it doesn't match the spec now would help: possibly some
shorter version of your commit message, with the typos fixed.
Anyway, git-bisect should be enough and I'm fine even without the
comment:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 40 +++++++++++++++++---------
> ----------
> 1 file changed, 19 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a3c959cd8b3b..5e7b22a31098 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3957,37 +3957,35 @@ static void lpt_disable_iclkip(struct
> drm_i915_private *dev_priv)
> /* Program iCLKIP clock to the desired frequency */
> static void lpt_program_iclkip(struct drm_crtc *crtc)
> {
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> int clock = to_intel_crtc(crtc)->config-
> >base.adjusted_mode.crtc_clock;
> u32 divsel, phaseinc, auxdiv, phasedir = 0;
> u32 temp;
>
> lpt_disable_iclkip(dev_priv);
>
> - /* 20MHz is a corner case which is out of range for the 7-
> bit divisor */
> - if (clock == 20000) {
> - auxdiv = 1;
> - divsel = 0x41;
> - phaseinc = 0x20;
> - } else {
> - /* The iCLK virtual clock root frequency is in MHz,
> - * but the adjusted_mode->crtc_clock in in KHz. To
> get the
> - * divisors, it is necessary to divide one by
> another, so we
> - * convert the virtual clock precision to KHz here
> for higher
> - * precision.
> - */
> + /* The iCLK virtual clock root frequency is in MHz,
> + * but the adjusted_mode->crtc_clock in in KHz. To get the
> + * divisors, it is necessary to divide one by another, so we
> + * convert the virtual clock precision to KHz here for
> higher
> + * precision.
> + */
> + for (auxdiv = 0; auxdiv < 2; auxdiv++) {
> u32 iclk_virtual_root_freq = 172800 * 1000;
> u32 iclk_pi_range = 64;
> - u32 desired_divisor, msb_divisor_value, pi_value;
> + u32 desired_divisor;
>
> - desired_divisor =
> DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
> - msb_divisor_value = desired_divisor / iclk_pi_range;
> - pi_value = desired_divisor % iclk_pi_range;
> + desired_divisor =
> DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
> + clock <<
> auxdiv);
> + divsel = (desired_divisor / iclk_pi_range) - 2;
> + phaseinc = desired_divisor % iclk_pi_range;
>
> - auxdiv = 0;
> - divsel = msb_divisor_value - 2;
> - phaseinc = pi_value;
> + /*
> + * Near 20MHz is a corner case which is
> + * out of range for the 7-bit divisor
> + */
> + if (divsel <= 0x7f)
> + break;
> }
>
> /* This should not happen with any sane values */
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 4/6] drm/i915: Make the LPT iclkip 20MHz case more generic
2016-02-17 19:41 ` [PATCH 4/6] drm/i915: Make the LPT iclkip 20MHz case more generic ville.syrjala
2016-02-19 13:54 ` Zanoni, Paulo R
@ 2016-02-19 14:04 ` Imre Deak
1 sibling, 0 replies; 17+ messages in thread
From: Imre Deak @ 2016-02-19 14:04 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Paulo Zanoni
On ke, 2016-02-17 at 21:41 +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The reason for spcial casing 20MHz in the iclkip calculations is that
> it would overflow the 7 bit divisor value. Let's rewrite the special
> case to check for just that, and bump up auxdiv when needed. This
> makes
> the code work for freqeuencies close to but not exactly 20MHz. The
> real
> lower limit for auxdiv=0 is actually:
> 172800000/(0x7f+2)*64)=~20930 kHz, and below that we must resort to
> auxdiv=1.
>
> Actually this is all very theoretical since we limit the dotclock to
> min 25MHz with CRT on all platforms. 25Mhz is actually the documented
> limit in Bspec, so it seems we ought to never need to worry about the
> auxdiv=1 case. But no harm in having it.
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Yep, fewer special casing is better. Btw, the spec could have just as
well describe how to calculate aux_div instead of providing special
cases and tables, I wonder why this is done at places. The patch looks
good:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 40 +++++++++++++++++---------
> ----------
> 1 file changed, 19 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a3c959cd8b3b..5e7b22a31098 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3957,37 +3957,35 @@ static void lpt_disable_iclkip(struct
> drm_i915_private *dev_priv)
> /* Program iCLKIP clock to the desired frequency */
> static void lpt_program_iclkip(struct drm_crtc *crtc)
> {
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> int clock = to_intel_crtc(crtc)->config-
> >base.adjusted_mode.crtc_clock;
> u32 divsel, phaseinc, auxdiv, phasedir = 0;
> u32 temp;
>
> lpt_disable_iclkip(dev_priv);
>
> - /* 20MHz is a corner case which is out of range for the 7-
> bit divisor */
> - if (clock == 20000) {
> - auxdiv = 1;
> - divsel = 0x41;
> - phaseinc = 0x20;
> - } else {
> - /* The iCLK virtual clock root frequency is in MHz,
> - * but the adjusted_mode->crtc_clock in in KHz. To
> get the
> - * divisors, it is necessary to divide one by
> another, so we
> - * convert the virtual clock precision to KHz here
> for higher
> - * precision.
> - */
> + /* The iCLK virtual clock root frequency is in MHz,
> + * but the adjusted_mode->crtc_clock in in KHz. To get the
> + * divisors, it is necessary to divide one by another, so we
> + * convert the virtual clock precision to KHz here for
> higher
> + * precision.
> + */
> + for (auxdiv = 0; auxdiv < 2; auxdiv++) {
> u32 iclk_virtual_root_freq = 172800 * 1000;
> u32 iclk_pi_range = 64;
> - u32 desired_divisor, msb_divisor_value, pi_value;
> + u32 desired_divisor;
>
> - desired_divisor =
> DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
> - msb_divisor_value = desired_divisor / iclk_pi_range;
> - pi_value = desired_divisor % iclk_pi_range;
> + desired_divisor =
> DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
> + clock <<
> auxdiv);
> + divsel = (desired_divisor / iclk_pi_range) - 2;
> + phaseinc = desired_divisor % iclk_pi_range;
>
> - auxdiv = 0;
> - divsel = msb_divisor_value - 2;
> - phaseinc = pi_value;
> + /*
> + * Near 20MHz is a corner case which is
> + * out of range for the 7-bit divisor
> + */
> + if (divsel <= 0x7f)
> + break;
> }
>
> /* This should not happen with any sane values */
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/6] drm/i915: Read out VGA dotclock properly on LPT
2016-02-17 19:41 [PATCH 0/6] drm/i915: Some FDI related dotclock stuff ville.syrjala
` (3 preceding siblings ...)
2016-02-17 19:41 ` [PATCH 4/6] drm/i915: Make the LPT iclkip 20MHz case more generic ville.syrjala
@ 2016-02-17 19:41 ` ville.syrjala
2016-02-19 14:17 ` Imre Deak
2016-02-17 19:41 ` [PATCH 6/6] drm/i915: Try to fix CRT port clock limits ville.syrjala
` (2 subsequent siblings)
7 siblings, 1 reply; 17+ messages in thread
From: ville.syrjala @ 2016-02-17 19:41 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rather than assume the VGA dotclock is really the FDI based thing,
let's read out the real thing via iclkip, and after readout it'll
get to compare it with the FDI based number to make sure they're
in sync.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
drivers/gpu/drm/i915/intel_crt.c | 4 ++++
drivers/gpu/drm/i915/intel_display.c | 37 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 1 +
4 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3774870477c1..a5f2c6e2edb2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7362,9 +7362,11 @@ enum skl_disp_power_wells {
/* SBI offsets */
#define SBI_SSCDIVINTPHASE 0x0200
#define SBI_SSCDIVINTPHASE6 0x0600
-#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
+#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
+#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f<<1)
#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
-#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
+#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
+#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f<<8)
#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
@@ -7374,6 +7376,8 @@ enum skl_disp_power_wells {
#define SBI_SSCCTL_PATHALT (1<<3)
#define SBI_SSCCTL_DISABLE (1<<0)
#define SBI_SSCAUXDIV6 0x0610
+#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
+#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1<<4)
#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
#define SBI_DBUFF0 0x2a00
#define SBI_GEN0 0x1f00
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index f4c88d93a164..08964bbd7c82 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -128,6 +128,8 @@ static void intel_crt_get_config(struct intel_encoder *encoder,
static void hsw_crt_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
intel_ddi_get_config(encoder, pipe_config);
pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
@@ -135,6 +137,8 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_NVSYNC);
pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
+
+ pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
}
/* Note: The caller is required to filter out dpms modes not supported by the
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5e7b22a31098..43cae2f8016d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4032,6 +4032,43 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
}
+int lpt_get_iclkip(struct drm_i915_private *dev_priv)
+{
+ u32 divsel, phaseinc, auxdiv;
+ u32 iclk_virtual_root_freq = 172800 * 1000;
+ u32 iclk_pi_range = 64;
+ u32 desired_divisor;
+ u32 temp;
+
+ if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
+ return 0;
+
+ mutex_lock(&dev_priv->sb_lock);
+
+ temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
+ if (temp & SBI_SSCCTL_DISABLE) {
+ mutex_unlock(&dev_priv->sb_lock);
+ return 0;
+ }
+
+ temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
+ divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
+ SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
+ phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
+ SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
+
+ temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
+ auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
+ SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
+
+ mutex_unlock(&dev_priv->sb_lock);
+
+ desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
+
+ return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
+ desired_divisor << auxdiv);
+}
+
static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
enum pipe pch_transcoder)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c25a8880b4e8..3b64c9b002a8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1158,6 +1158,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
const struct dpll *dpll);
void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
+int lpt_get_iclkip(struct drm_i915_private *dev_priv);
/* modesetting asserts */
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
--
2.4.10
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 5/6] drm/i915: Read out VGA dotclock properly on LPT
2016-02-17 19:41 ` [PATCH 5/6] drm/i915: Read out VGA dotclock properly on LPT ville.syrjala
@ 2016-02-19 14:17 ` Imre Deak
0 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2016-02-19 14:17 UTC (permalink / raw)
To: ville.syrjala, intel-gfx; +Cc: Paulo Zanoni
On ke, 2016-02-17 at 21:41 +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rather than assume the VGA dotclock is really the FDI based thing,
> let's read out the real thing via iclkip, and after readout it'll
> get to compare it with the FDI based number to make sure they're
> in sync.
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
> drivers/gpu/drm/i915/intel_crt.c | 4 ++++
> drivers/gpu/drm/i915/intel_display.c | 37
> ++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 4 files changed, 48 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 3774870477c1..a5f2c6e2edb2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7362,9 +7362,11 @@ enum skl_disp_power_wells {
> /* SBI offsets */
> #define SBI_SSCDIVINTPHASE 0x0200
> #define SBI_SSCDIVINTPHASE6 0x0600
> -#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
> +#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
> +#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f<<1)
> #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
> -#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
> +#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
> +#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f<<8)
> #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
> #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
> #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
> @@ -7374,6 +7376,8 @@ enum skl_disp_power_wells {
> #define SBI_SSCCTL_PATHALT (1<<3)
> #define SBI_SSCCTL_DISABLE (1<<0)
> #define SBI_SSCAUXDIV6 0x0610
> +#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
> +#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1<<4)
> #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
> #define SBI_DBUFF0 0x2a00
> #define SBI_GEN0 0x1f00
> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> b/drivers/gpu/drm/i915/intel_crt.c
> index f4c88d93a164..08964bbd7c82 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -128,6 +128,8 @@ static void intel_crt_get_config(struct
> intel_encoder *encoder,
> static void hsw_crt_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> +
> intel_ddi_get_config(encoder, pipe_config);
>
> pipe_config->base.adjusted_mode.flags &=
> ~(DRM_MODE_FLAG_PHSYNC |
> @@ -135,6 +137,8 @@ static void hsw_crt_get_config(struct
> intel_encoder *encoder,
> DRM_MODE_FLAG_PVSYNC |
> DRM_MODE_FLAG_NVSYNC);
> pipe_config->base.adjusted_mode.flags |=
> intel_crt_get_flags(encoder);
> +
> + pipe_config->base.adjusted_mode.crtc_clock =
> lpt_get_iclkip(dev_priv);
> }
>
> /* Note: The caller is required to filter out dpms modes not
> supported by the
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 5e7b22a31098..43cae2f8016d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4032,6 +4032,43 @@ static void lpt_program_iclkip(struct drm_crtc
> *crtc)
> I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
> }
>
> +int lpt_get_iclkip(struct drm_i915_private *dev_priv)
> +{
> + u32 divsel, phaseinc, auxdiv;
> + u32 iclk_virtual_root_freq = 172800 * 1000;
> + u32 iclk_pi_range = 64;
> + u32 desired_divisor;
> + u32 temp;
> +
> + if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
> + return 0;
> +
> + mutex_lock(&dev_priv->sb_lock);
> +
> + temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
> + if (temp & SBI_SSCCTL_DISABLE) {
> + mutex_unlock(&dev_priv->sb_lock);
> + return 0;
> + }
> +
> + temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6,
> SBI_ICLK);
> + divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
> + SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
> + phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
> + SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
> +
> + temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
> + auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
> + SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
> +
> + mutex_unlock(&dev_priv->sb_lock);
> +
> + desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
> +
> + return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
> + desired_divisor << auxdiv);
> +}
> +
> static void ironlake_pch_transcoder_set_timings(struct intel_crtc
> *crtc,
> enum pipe
> pch_transcoder)
> {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index c25a8880b4e8..3b64c9b002a8 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1158,6 +1158,7 @@ struct intel_shared_dpll
> *intel_get_shared_dpll(struct intel_crtc *crtc,
> int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
> const struct dpll *dpll);
> void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
> +int lpt_get_iclkip(struct drm_i915_private *dev_priv);
>
> /* modesetting asserts */
> void assert_panel_unlocked(struct drm_i915_private *dev_priv,
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 6/6] drm/i915: Try to fix CRT port clock limits
2016-02-17 19:41 [PATCH 0/6] drm/i915: Some FDI related dotclock stuff ville.syrjala
` (4 preceding siblings ...)
2016-02-17 19:41 ` [PATCH 5/6] drm/i915: Read out VGA dotclock properly on LPT ville.syrjala
@ 2016-02-17 19:41 ` ville.syrjala
2016-02-19 14:58 ` Imre Deak
2016-02-19 13:45 ` ✗ Fi.CI.BAT: failure for drm/i915: Some FDI related dotclock stuff Patchwork
2016-03-01 11:13 ` [PATCH 0/6] " Ville Syrjälä
7 siblings, 1 reply; 17+ messages in thread
From: ville.syrjala @ 2016-02-17 19:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
LPT/WPT-H are limited to max 180 MHz CRT dotclock. Most other platforms
have a limit of 350 MHz. Supposedly gen3 and gen4 go up to 400 MHz.
VLV is a bit special since the docs are poor. Supposedly the DAC
would be good up to 355 MHz, but currently we limit the DPLL to
270 MHz, so we'll have to limit the port clock to the same unless
we change the DPLL limits.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_crt.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 08964bbd7c82..6bdd4f4310f1 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -220,18 +220,26 @@ intel_crt_mode_valid(struct drm_connector *connector,
{
struct drm_device *dev = connector->dev;
int max_dotclk = to_i915(dev)->max_dotclk_freq;
+ int max_clock;
- int max_clock = 0;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
return MODE_NO_DBLESCAN;
if (mode->clock < 25000)
return MODE_CLOCK_LOW;
- if (IS_GEN2(dev))
- max_clock = 350000;
- else
+ if (HAS_PCH_LPT(dev))
+ max_clock = 180000;
+ else if (IS_VALLEYVIEW(dev))
+ /*
+ * 270 MHz due to current DPLL limits,
+ * DAC limit supposedly 355 MHz.
+ */
+ max_clock = 270000;
+ else if (IS_GEN3(dev) || IS_GEN4(dev))
max_clock = 400000;
+ else
+ max_clock = 350000;
if (mode->clock > max_clock)
return MODE_CLOCK_HIGH;
--
2.4.10
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 6/6] drm/i915: Try to fix CRT port clock limits
2016-02-17 19:41 ` [PATCH 6/6] drm/i915: Try to fix CRT port clock limits ville.syrjala
@ 2016-02-19 14:58 ` Imre Deak
0 siblings, 0 replies; 17+ messages in thread
From: Imre Deak @ 2016-02-19 14:58 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On ke, 2016-02-17 at 21:41 +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> LPT/WPT-H are limited to max 180 MHz CRT dotclock. Most other
> platforms
> have a limit of 350 MHz. Supposedly gen3 and gen4 go up to 400 MHz.
>
> VLV is a bit special since the docs are poor. Supposedly the DAC
> would be good up to 355 MHz, but currently we limit the DPLL to
> 270 MHz, so we'll have to limit the port clock to the same unless
> we change the DPLL limits.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_crt.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_crt.c
> b/drivers/gpu/drm/i915/intel_crt.c
> index 08964bbd7c82..6bdd4f4310f1 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -220,18 +220,26 @@ intel_crt_mode_valid(struct drm_connector
> *connector,
> {
> struct drm_device *dev = connector->dev;
> int max_dotclk = to_i915(dev)->max_dotclk_freq;
> + int max_clock;
>
> - int max_clock = 0;
> if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return MODE_NO_DBLESCAN;
>
> if (mode->clock < 25000)
> return MODE_CLOCK_LOW;
>
> - if (IS_GEN2(dev))
> - max_clock = 350000;
> - else
> + if (HAS_PCH_LPT(dev))
> + max_clock = 180000;
> + else if (IS_VALLEYVIEW(dev))
> + /*
> + * 270 MHz due to current DPLL limits,
> + * DAC limit supposedly 355 MHz.
> + */
> + max_clock = 270000;
> + else if (IS_GEN3(dev) || IS_GEN4(dev))
> max_clock = 400000;
> + else
> + max_clock = 350000;
> if (mode->clock > max_clock)
> return MODE_CLOCK_HIGH;
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Some FDI related dotclock stuff
2016-02-17 19:41 [PATCH 0/6] drm/i915: Some FDI related dotclock stuff ville.syrjala
` (5 preceding siblings ...)
2016-02-17 19:41 ` [PATCH 6/6] drm/i915: Try to fix CRT port clock limits ville.syrjala
@ 2016-02-19 13:45 ` Patchwork
2016-02-25 18:15 ` Ville Syrjälä
2016-03-01 11:13 ` [PATCH 0/6] " Ville Syrjälä
7 siblings, 1 reply; 17+ messages in thread
From: Patchwork @ 2016-02-19 13:45 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Summary ==
Series 3541v1 drm/i915: Some FDI related dotclock stuff
http://patchwork.freedesktop.org/api/1.0/series/3541/revisions/1/mbox/
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (ilk-hp8440p) UNSTABLE
Subgroup basic-flip-vs-wf_vblank:
pass -> FAIL (snb-x220t)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b:
pass -> INCOMPLETE (ilk-hp8440p)
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (skl-i5k-2) UNSTABLE
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS (bsw-nuc-2)
Test pm_rpm:
Subgroup basic-pci-d3-state:
dmesg-warn -> PASS (bsw-nuc-2)
pass -> DMESG-WARN (byt-nuc)
Subgroup basic-rte:
pass -> DMESG-WARN (bsw-nuc-2)
pass -> FAIL (bdw-ultra)
dmesg-warn -> PASS (byt-nuc) UNSTABLE
bdw-nuci7 total:164 pass:153 dwarn:0 dfail:0 fail:0 skip:11
bdw-ultra total:167 pass:152 dwarn:0 dfail:0 fail:1 skip:14
bsw-nuc-2 total:167 pass:136 dwarn:1 dfail:0 fail:0 skip:30
byt-nuc total:167 pass:141 dwarn:1 dfail:0 fail:0 skip:25
hsw-gt2 total:167 pass:156 dwarn:0 dfail:0 fail:1 skip:10
ilk-hp8440p total:163 pass:114 dwarn:0 dfail:0 fail:1 skip:47
ivb-t430s total:167 pass:152 dwarn:0 dfail:0 fail:1 skip:14
skl-i5k-2 total:167 pass:150 dwarn:1 dfail:0 fail:0 skip:16
snb-dellxps total:167 pass:144 dwarn:0 dfail:0 fail:1 skip:22
snb-x220t total:167 pass:143 dwarn:0 dfail:0 fail:3 skip:21
Results at /archive/results/CI_IGT_test/Patchwork_1429/
631053ba117c294f0cdfe704718a040b4406a240 drm-intel-nightly: 2016y-02m-17d-21h-05m-38s UTC integration manifest
beb6d5046d6b0eafd0aa4bc15a87e534e3e0aa8e drm/i915: Try to fix CRT port clock limits
c7f53fb3c57d5a91216c037d757876e3a692ae0e drm/i915: Read out VGA dotclock properly on LPT
3c2e8606fb856686e2fa84b10f1c22ef2d209e17 drm/i915: Make the LPT iclkip 20MHz case more generic
6bb0fff788112afbb60391b5a77e4f62745ba0f7 drm/i915: Remove the SPLL==270Mhz assumption from intel_fdi_link_freq()
f8260170eff5e4763d1c99e1baa3246f19c294d5 drm/i915: Move the encoder vs. FDI dotclock check out from encoder .get_config()
865134f99bff4ba3a91d2703282aa16c83d8ce52 drm/i915: Dump ddi_pll_sel in hex instead of decimal on HSW/BDW
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: ✗ Fi.CI.BAT: failure for drm/i915: Some FDI related dotclock stuff
2016-02-19 13:45 ` ✗ Fi.CI.BAT: failure for drm/i915: Some FDI related dotclock stuff Patchwork
@ 2016-02-25 18:15 ` Ville Syrjälä
0 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2016-02-25 18:15 UTC (permalink / raw)
To: intel-gfx
On Fri, Feb 19, 2016 at 01:45:03PM -0000, Patchwork wrote:
> == Summary ==
>
> Series 3541v1 drm/i915: Some FDI related dotclock stuff
> http://patchwork.freedesktop.org/api/1.0/series/3541/revisions/1/mbox/
>
> Test kms_flip:
> Subgroup basic-flip-vs-dpms:
> dmesg-warn -> PASS (ilk-hp8440p) UNSTABLE
> Subgroup basic-flip-vs-wf_vblank:
> pass -> FAIL (snb-x220t)
(kms_flip:6443) DEBUG: name = vblank
last_ts = 594.687318 usec
last_received_ts = 594.687142 usec
last_seq = 24682
current_ts = 594.870400 usec
current_received_ts = 594.870267 usec
current_seq = 24692
count = 44
seq_step = 10
(kms_flip:6443) CRITICAL: Test assertion failure function check_state, file kms_flip.c:692:
(kms_flip:6443) CRITICAL: Failed assertion: fabs((((double) diff.tv_usec) - usec_interflip) / usec_interflip) <= 0.005
(kms_flip:6443) CRITICAL: Last errno: 25, Inappropriate ioctl for device
(kms_flip:6443) CRITICAL: inter-vblank ts jitter: 0s, 183082usec
Hmm. So here it looks like the seq number says 10, but the timestamp
difference says 11. I found a few more of the same in the CI results.
This could be due to the race with even numbered vblank seq increments
that could be fixed by:
https://lists.freedesktop.org/archives/dri-devel/2015-September/090288.html
Filed a bug:
https://bugs.freedesktop.org/show_bug.cgi?id=94294
> Test kms_pipe_crc_basic:
> Subgroup read-crc-pipe-b:
> pass -> INCOMPLETE (ilk-hp8440p)
> Subgroup suspend-read-crc-pipe-a:
> dmesg-warn -> PASS (skl-i5k-2) UNSTABLE
> Subgroup suspend-read-crc-pipe-b:
> pass -> DMESG-WARN (skl-i5k-2) UNSTABLE
> Subgroup suspend-read-crc-pipe-c:
> dmesg-warn -> PASS (bsw-nuc-2)
> Test pm_rpm:
> Subgroup basic-pci-d3-state:
> dmesg-warn -> PASS (bsw-nuc-2)
> pass -> DMESG-WARN (byt-nuc)
[ 126.296996] [drm:intel_runtime_suspend [i915]] *ERROR* Unclaimed access detected prior to suspending
https://bugs.freedesktop.org/show_bug.cgi?id=94164
> Subgroup basic-rte:
> pass -> DMESG-WARN (bsw-nuc-2)
> pass -> FAIL (bdw-ultra)
https://bugs.freedesktop.org/show_bug.cgi?id=94163
> dmesg-warn -> PASS (byt-nuc) UNSTABLE
>
> bdw-nuci7 total:164 pass:153 dwarn:0 dfail:0 fail:0 skip:11
> bdw-ultra total:167 pass:152 dwarn:0 dfail:0 fail:1 skip:14
> bsw-nuc-2 total:167 pass:136 dwarn:1 dfail:0 fail:0 skip:30
> byt-nuc total:167 pass:141 dwarn:1 dfail:0 fail:0 skip:25
> hsw-gt2 total:167 pass:156 dwarn:0 dfail:0 fail:1 skip:10
> ilk-hp8440p total:163 pass:114 dwarn:0 dfail:0 fail:1 skip:47
> ivb-t430s total:167 pass:152 dwarn:0 dfail:0 fail:1 skip:14
> skl-i5k-2 total:167 pass:150 dwarn:1 dfail:0 fail:0 skip:16
> snb-dellxps total:167 pass:144 dwarn:0 dfail:0 fail:1 skip:22
> snb-x220t total:167 pass:143 dwarn:0 dfail:0 fail:3 skip:21
>
> Results at /archive/results/CI_IGT_test/Patchwork_1429/
>
> 631053ba117c294f0cdfe704718a040b4406a240 drm-intel-nightly: 2016y-02m-17d-21h-05m-38s UTC integration manifest
> beb6d5046d6b0eafd0aa4bc15a87e534e3e0aa8e drm/i915: Try to fix CRT port clock limits
> c7f53fb3c57d5a91216c037d757876e3a692ae0e drm/i915: Read out VGA dotclock properly on LPT
> 3c2e8606fb856686e2fa84b10f1c22ef2d209e17 drm/i915: Make the LPT iclkip 20MHz case more generic
> 6bb0fff788112afbb60391b5a77e4f62745ba0f7 drm/i915: Remove the SPLL==270Mhz assumption from intel_fdi_link_freq()
> f8260170eff5e4763d1c99e1baa3246f19c294d5 drm/i915: Move the encoder vs. FDI dotclock check out from encoder .get_config()
> 865134f99bff4ba3a91d2703282aa16c83d8ce52 drm/i915: Dump ddi_pll_sel in hex instead of decimal on HSW/BDW
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/6] drm/i915: Some FDI related dotclock stuff
2016-02-17 19:41 [PATCH 0/6] drm/i915: Some FDI related dotclock stuff ville.syrjala
` (6 preceding siblings ...)
2016-02-19 13:45 ` ✗ Fi.CI.BAT: failure for drm/i915: Some FDI related dotclock stuff Patchwork
@ 2016-03-01 11:13 ` Ville Syrjälä
7 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2016-03-01 11:13 UTC (permalink / raw)
To: intel-gfx
On Wed, Feb 17, 2016 at 09:41:07PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Imre's SNB had a crappy BIOS that failed to configure the hardware
> correctly when hooked up to a 4K monitor, which then resulted in
> lots of noise from i915 when it was trying to make sense of the bad
> state. That spurred me to reorganize the FDI dotclock vs. encoder
> dotclock sanity check we have in the encoder .get_config() hooks.
> And while doing that I figured we might as well try to read out
> the actual VGA dotclock via sideband on HSW/BDW, which can then
> be compared to the one compute from FDI parameters.
>
> Apparently a BIOS update solved the problem for Imre, but I think
> these patches still have some value by adding more thorough state
> cross checking on HSW/BDW, and just moving out the sanity checks
> from the state readout code makes quite a bit of sense to me,
> especially if we run into more buggy BIOSen. Though if people
> prefer, I could respin these without that particular change,
> ie. just keep the LPT-H dotclock readout and cross checking
> essentially.
>
> I also ended up fixing the port clock limits for CRT for various
> platforms.
>
> Ville Syrjälä (6):
> drm/i915: Dump ddi_pll_sel in hex instead of decimal on HSW/BDW
> drm/i915: Move the encoder vs. FDI dotclock check out from encoder
> .get_config()
> drm/i915: Remove the SPLL==270Mhz assumption from
> intel_fdi_link_freq()
> drm/i915: Make the LPT iclkip 20MHz case more generic
> drm/i915: Read out VGA dotclock properly on LPT
> drm/i915: Try to fix CRT port clock limits
Entire series pushed to dinq. Thanks for the reviews.
>
> drivers/gpu/drm/i915/i915_reg.h | 8 +-
> drivers/gpu/drm/i915/intel_crt.c | 30 ++++----
> drivers/gpu/drm/i915/intel_display.c | 143 +++++++++++++++++++++++------------
> drivers/gpu/drm/i915/intel_dp.c | 11 +--
> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> drivers/gpu/drm/i915/intel_hdmi.c | 3 -
> drivers/gpu/drm/i915/intel_lvds.c | 8 +-
> drivers/gpu/drm/i915/intel_sdvo.c | 4 +-
> 8 files changed, 123 insertions(+), 88 deletions(-)
>
> --
> 2.4.10
--
Ville Syrjälä
Intel OTC
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread