From: Daniel Vetter <daniel@ffwll.ch>
To: Francisco Jerez <currojerez@riseup.net>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 5/5] drm/i915: Bump command parser version for new whitelisted registers
Date: Mon, 21 Mar 2016 10:03:43 +0100 [thread overview]
Message-ID: <20160321090343.GC28483@phenom.ffwll.local> (raw)
In-Reply-To: <87d1r4fwu0.fsf@riseup.net>
On Tue, Mar 08, 2016 at 02:07:03PM -0800, Francisco Jerez wrote:
> Jordan Justen <jordan.l.justen@intel.com> writes:
>
> > Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
>
> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Entire series applied to dinq, thanks for patches&review.
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/i915_cmd_parser.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > index e1608da..f8381be 100644
> > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> > @@ -1287,6 +1287,7 @@ int i915_cmd_parser_get_version(void)
> > * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
> > * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
> > * 5. GPGPU dispatch compute indirect registers.
> > + * 6. TIMESTAMP register and Haswell CS GPR registers
> > */
> > - return 5;
> > + return 6;
> > }
> > --
> > 2.7.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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next prev parent reply other threads:[~2016-03-21 9:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-07 7:30 [PATCH 0/5] Haswell Command Parser updates for Vulkan Jordan Justen
2016-03-07 7:30 ` [PATCH 1/5] drm/i915: Add TIMESTAMP to register whitelist Jordan Justen
2016-03-08 22:06 ` Francisco Jerez
2016-03-07 7:30 ` [PATCH 2/5] drm/i915: Use an array of register tables in command parser Jordan Justen
2016-03-16 23:33 ` Francisco Jerez
2016-03-07 7:30 ` [PATCH 3/5] drm/i915: Move Haswell registers to separate whitelist table Jordan Justen
2016-03-08 22:05 ` Francisco Jerez
2016-03-07 7:30 ` [PATCH 4/5] drm/i915: Add Haswell CS GPR registers to whitelist Jordan Justen
2016-03-08 22:06 ` Francisco Jerez
2016-03-07 7:30 ` [PATCH 5/5] drm/i915: Bump command parser version for new whitelisted registers Jordan Justen
2016-03-08 22:07 ` Francisco Jerez
2016-03-21 9:03 ` Daniel Vetter [this message]
2016-03-07 12:27 ` ✗ Fi.CI.BAT: failure for Haswell Command Parser updates for Vulkan Patchwork
2016-03-21 8:53 ` Daniel Vetter
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