* [PATCH] drm/i915: BXT DDI PHY sequence BUN
@ 2016-03-21 6:42 Vandana Kannan
2016-03-21 10:20 ` Jani Nikula
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Vandana Kannan @ 2016-03-21 6:42 UTC (permalink / raw)
To: intel-gfx
According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be
checked to ensure that the register is in accessible state.
Also, based on a BSpec update, changing the timeout value to
check iphypwrgood, from 10ms to wait for up to 100us.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7dfc400..9a02bfc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1318,6 +1318,7 @@ enum skl_disp_power_wells {
#define _PORT_CL1CM_DW0_A 0x162000
#define _PORT_CL1CM_DW0_BC 0x6C000
#define PHY_POWER_GOOD (1 << 16)
+#define PHY_RESERVED (1 << 7)
#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
_PORT_CL1CM_DW0_A)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 62de9f4..354f949 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
val |= GT_DISPLAY_POWER_ON(phy);
I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
- /* Considering 10ms timeout until BSpec is updated */
- if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
+ /*
+ * HW team confirmed that the time to reach phypowergood status is
+ * anywhere between 50 us and 100us.
+ */
+ if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
+ PHY_RESERVED)) &&
+ ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
+ PHY_POWER_GOOD) == PHY_POWER_GOOD)), 100)) {
DRM_ERROR("timeout during PHY%d power on\n", phy);
+ }
for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915: BXT DDI PHY sequence BUN 2016-03-21 6:42 [PATCH] drm/i915: BXT DDI PHY sequence BUN Vandana Kannan @ 2016-03-21 10:20 ` Jani Nikula 2016-03-21 15:02 ` Jani Nikula 2016-03-21 14:03 ` Ville Syrjälä 2016-03-21 14:33 ` ✗ Fi.CI.BAT: warning for " Patchwork 2 siblings, 1 reply; 8+ messages in thread From: Jani Nikula @ 2016-03-21 10:20 UTC (permalink / raw) To: Vandana Kannan, intel-gfx On Mon, 21 Mar 2016, Vandana Kannan <vandana.kannan@intel.com> wrote: > According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be > checked to ensure that the register is in accessible state. *sigh* the bspec is still not updated, and I didn't get the BUN. > Also, based on a BSpec update, changing the timeout value to > check iphypwrgood, from 10ms to wait for up to 100us. > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com> > Cc: Deak, Imre <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++-- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 7dfc400..9a02bfc 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { > #define _PORT_CL1CM_DW0_A 0x162000 > #define _PORT_CL1CM_DW0_BC 0x6C000 > #define PHY_POWER_GOOD (1 << 16) > +#define PHY_RESERVED (1 << 7) > #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \ > _PORT_CL1CM_DW0_A) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 62de9f4..354f949 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, > val |= GT_DISPLAY_POWER_ON(phy); > I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); > > - /* Considering 10ms timeout until BSpec is updated */ > - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) > + /* > + * HW team confirmed that the time to reach phypowergood status is > + * anywhere between 50 us and 100us. > + */ > + if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > + PHY_RESERVED)) && > + ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > + PHY_POWER_GOOD) == PHY_POWER_GOOD)), 100)) { Is there any reason why you'd need to do the read twice? Why not just write it as: (I915_READ(BXT_PORT_CL1CM_DW0(phy)) & (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD BR, Jani. > DRM_ERROR("timeout during PHY%d power on\n", phy); > + } > > for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); > port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: BXT DDI PHY sequence BUN 2016-03-21 10:20 ` Jani Nikula @ 2016-03-21 15:02 ` Jani Nikula 0 siblings, 0 replies; 8+ messages in thread From: Jani Nikula @ 2016-03-21 15:02 UTC (permalink / raw) To: Vandana Kannan, intel-gfx On Mon, 21 Mar 2016, Jani Nikula <jani.nikula@linux.intel.com> wrote: > [ text/plain ] > On Mon, 21 Mar 2016, Vandana Kannan <vandana.kannan@intel.com> wrote: >> According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be >> checked to ensure that the register is in accessible state. > > *sigh* the bspec is still not updated, and I didn't get the BUN. > >> Also, based on a BSpec update, changing the timeout value to >> check iphypwrgood, from 10ms to wait for up to 100us. >> >> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> >> Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com> >> Cc: Deak, Imre <imre.deak@intel.com> >> --- >> drivers/gpu/drm/i915/i915_reg.h | 1 + >> drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++-- >> 2 files changed, 10 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 7dfc400..9a02bfc 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { >> #define _PORT_CL1CM_DW0_A 0x162000 >> #define _PORT_CL1CM_DW0_BC 0x6C000 >> #define PHY_POWER_GOOD (1 << 16) >> +#define PHY_RESERVED (1 << 7) >> #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \ >> _PORT_CL1CM_DW0_A) >> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >> index 62de9f4..354f949 100644 >> --- a/drivers/gpu/drm/i915/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/intel_ddi.c >> @@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, >> val |= GT_DISPLAY_POWER_ON(phy); >> I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); >> >> - /* Considering 10ms timeout until BSpec is updated */ >> - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) >> + /* >> + * HW team confirmed that the time to reach phypowergood status is >> + * anywhere between 50 us and 100us. >> + */ Interesting, the spec section (now that I found it, thanks again!) says, "recommended poll time interval = 100 us". Interval, not timeout. >> + if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & >> + PHY_RESERVED)) && >> + ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & >> + PHY_POWER_GOOD) == PHY_POWER_GOOD)), 100)) { > > Is there any reason why you'd need to do the read twice? Why not just > write it as: > > (I915_READ(BXT_PORT_CL1CM_DW0(phy)) & (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD AFAICT this should be fine. BR, Jani. > > BR, > Jani. > >> DRM_ERROR("timeout during PHY%d power on\n", phy); >> + } >> >> for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); >> port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: BXT DDI PHY sequence BUN 2016-03-21 6:42 [PATCH] drm/i915: BXT DDI PHY sequence BUN Vandana Kannan 2016-03-21 10:20 ` Jani Nikula @ 2016-03-21 14:03 ` Ville Syrjälä 2016-03-23 4:43 ` Kannan, Vandana 2016-03-21 14:33 ` ✗ Fi.CI.BAT: warning for " Patchwork 2 siblings, 1 reply; 8+ messages in thread From: Ville Syrjälä @ 2016-03-21 14:03 UTC (permalink / raw) To: Vandana Kannan; +Cc: intel-gfx On Mon, Mar 21, 2016 at 12:12:40PM +0530, Vandana Kannan wrote: > According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be > checked to ensure that the register is in accessible state. > Also, based on a BSpec update, changing the timeout value to > check iphypwrgood, from 10ms to wait for up to 100us. > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com> > Cc: Deak, Imre <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++-- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 7dfc400..9a02bfc 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { > #define _PORT_CL1CM_DW0_A 0x162000 > #define _PORT_CL1CM_DW0_BC 0x6C000 > #define PHY_POWER_GOOD (1 << 16) > +#define PHY_RESERVED (1 << 7) > #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \ > _PORT_CL1CM_DW0_A) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 62de9f4..354f949 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, > val |= GT_DISPLAY_POWER_ON(phy); > I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); > > - /* Considering 10ms timeout until BSpec is updated */ > - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) > + /* > + * HW team confirmed that the time to reach phypowergood status is > + * anywhere between 50 us and 100us. > + */ > + if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & Switching to atomic wait seems silly. > + PHY_RESERVED)) && > + ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > + PHY_POWER_GOOD) == PHY_POWER_GOOD)), 100)) { > DRM_ERROR("timeout during PHY%d power on\n", phy); > + } > > for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); > port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: BXT DDI PHY sequence BUN 2016-03-21 14:03 ` Ville Syrjälä @ 2016-03-23 4:43 ` Kannan, Vandana 2016-03-29 12:03 ` Imre Deak 0 siblings, 1 reply; 8+ messages in thread From: Kannan, Vandana @ 2016-03-23 4:43 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx@lists.freedesktop.org > -----Original Message----- > From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] > Sent: Monday, March 21, 2016 7:34 PM > To: Kannan, Vandana <vandana.kannan@intel.com> > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915: BXT DDI PHY sequence BUN > > On Mon, Mar 21, 2016 at 12:12:40PM +0530, Vandana Kannan wrote: > > According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register > needs > > to be checked to ensure that the register is in accessible state. > > Also, based on a BSpec update, changing the timeout value to check > > iphypwrgood, from 10ms to wait for up to 100us. > > > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > > Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com> > > Cc: Deak, Imre <imre.deak@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++-- > > 2 files changed, 10 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h index 7dfc400..9a02bfc 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { > > #define _PORT_CL1CM_DW0_A 0x162000 > > #define _PORT_CL1CM_DW0_BC 0x6C000 > > #define PHY_POWER_GOOD (1 << 16) > > +#define PHY_RESERVED (1 << 7) > > #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), > _PORT_CL1CM_DW0_BC, \ > > _PORT_CL1CM_DW0_A) > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > b/drivers/gpu/drm/i915/intel_ddi.c > > index 62de9f4..354f949 100644 > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > @@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct > drm_i915_private *dev_priv, > > val |= GT_DISPLAY_POWER_ON(phy); > > I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); > > > > - /* Considering 10ms timeout until BSpec is updated */ > > - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > PHY_POWER_GOOD, 10)) > > + /* > > + * HW team confirmed that the time to reach phypowergood status > is > > + * anywhere between 50 us and 100us. > > + */ > > + if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) > & > > Switching to atomic wait seems silly. > [Vandana] You think wait_for_us should suffice here? > > + PHY_RESERVED)) && > > + ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > > + PHY_POWER_GOOD) == > PHY_POWER_GOOD)), 100)) { > > DRM_ERROR("timeout during PHY%d power on\n", phy); > > + } > > > > for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); > > port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { > > -- > > 1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: BXT DDI PHY sequence BUN 2016-03-23 4:43 ` Kannan, Vandana @ 2016-03-29 12:03 ` Imre Deak 2016-03-31 12:38 ` Imre Deak 0 siblings, 1 reply; 8+ messages in thread From: Imre Deak @ 2016-03-29 12:03 UTC (permalink / raw) To: Kannan, Vandana, Ville Syrjälä; +Cc: intel-gfx@lists.freedesktop.org On ke, 2016-03-23 at 04:43 +0000, Kannan, Vandana wrote: > > -----Original Message----- > > From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] > > Sent: Monday, March 21, 2016 7:34 PM > > To: Kannan, Vandana <vandana.kannan@intel.com> > > Cc: intel-gfx@lists.freedesktop.org > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: BXT DDI PHY sequence BUN > > > > On Mon, Mar 21, 2016 at 12:12:40PM +0530, Vandana Kannan wrote: > > > According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register > > needs > > > to be checked to ensure that the register is in accessible state. > > > Also, based on a BSpec update, changing the timeout value to check > > > iphypwrgood, from 10ms to wait for up to 100us. > > > > > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > > > Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com> > > > Cc: Deak, Imre <imre.deak@intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > > drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++-- > > > 2 files changed, 10 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > b/drivers/gpu/drm/i915/i915_reg.h index 7dfc400..9a02bfc 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { > > > #define _PORT_CL1CM_DW0_A 0x162000 > > > #define _PORT_CL1CM_DW0_BC 0x6C000 > > > #define PHY_POWER_GOOD (1 << 16) > > > +#define PHY_RESERVED (1 << 7) > > > #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), > > _PORT_CL1CM_DW0_BC, \ > > > _PORT_CL1CM_DW0_A) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > > b/drivers/gpu/drm/i915/intel_ddi.c > > > index 62de9f4..354f949 100644 > > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > > @@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct > > drm_i915_private *dev_priv, > > > val |= GT_DISPLAY_POWER_ON(phy); > > > I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); > > > > > > - /* Considering 10ms timeout until BSpec is updated */ > > > - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > > PHY_POWER_GOOD, 10)) > > > + /* > > > + * HW team confirmed that the time to reach phypowergood status > > is > > > + * anywhere between 50 us and 100us. > > > + */ > > > + if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) > > & > > > > Switching to atomic wait seems silly. > > > [Vandana] You think wait_for_us should suffice here? Yes. > > > + PHY_RESERVED)) && > > > + ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > > > + PHY_POWER_GOOD) == > > PHY_POWER_GOOD)), 100)) { > > > DRM_ERROR("timeout during PHY%d power on\n", phy); > > > + } Please also add a comment on how the detection magic works: Reading any PHY register while the PHY is powered down will result in all register bits set, while the reserved bit 7 is guaranteed to be 0 when the PHY is powered up. --Imre > > > > > > for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); > > > port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { > > > -- > > > 1.9.1 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Ville Syrjälä > > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: BXT DDI PHY sequence BUN 2016-03-29 12:03 ` Imre Deak @ 2016-03-31 12:38 ` Imre Deak 0 siblings, 0 replies; 8+ messages in thread From: Imre Deak @ 2016-03-31 12:38 UTC (permalink / raw) To: Kannan, Vandana; +Cc: Jani Nikula, intel-gfx@lists.freedesktop.org On ti, 2016-03-29 at 15:03 +0300, Imre Deak wrote: > On ke, 2016-03-23 at 04:43 +0000, Kannan, Vandana wrote: > > > -----Original Message----- > > > From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] > > > Sent: Monday, March 21, 2016 7:34 PM > > > To: Kannan, Vandana <vandana.kannan@intel.com> > > > Cc: intel-gfx@lists.freedesktop.org > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: BXT DDI PHY sequence > > > BUN > > > > > > On Mon, Mar 21, 2016 at 12:12:40PM +0530, Vandana Kannan wrote: > > > > According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register > > > needs > > > > to be checked to ensure that the register is in accessible > > > > state. > > > > Also, based on a BSpec update, changing the timeout value to > > > > check > > > > iphypwrgood, from 10ms to wait for up to 100us. > > > > > > > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > > > > Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com> > > > > Cc: Deak, Imre <imre.deak@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > > > drivers/gpu/drm/i915/intel_ddi.c | 11 +++++++++-- > > > > 2 files changed, 10 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > > b/drivers/gpu/drm/i915/i915_reg.h index 7dfc400..9a02bfc 100644 > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { > > > > #define _PORT_CL1CM_DW0_A 0x162000 > > > > #define _PORT_CL1CM_DW0_BC 0x6C000 > > > > #define PHY_POWER_GOOD (1 << 16) > > > > +#define PHY_RESERVED (1 << 7) > > > > #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), > > > _PORT_CL1CM_DW0_BC, \ > > > > _PORT_ > > > > CL1CM_DW0_A) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > > > b/drivers/gpu/drm/i915/intel_ddi.c > > > > index 62de9f4..354f949 100644 > > > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > > > @@ -2669,9 +2669,16 @@ static void broxton_phy_init(struct > > > drm_i915_private *dev_priv, > > > > val |= GT_DISPLAY_POWER_ON(phy); > > > > I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); > > > > > > > > - /* Considering 10ms timeout until BSpec is updated */ > > > > - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > > > PHY_POWER_GOOD, 10)) > > > > + /* > > > > + * HW team confirmed that the time to reach > > > > phypowergood status > > > is > > > > + * anywhere between 50 us and 100us. > > > > + */ > > > > + if > > > > (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) > > > & > > > > > > Switching to atomic wait seems silly. > > > > > [Vandana] You think wait_for_us should suffice here? > > Yes. > > > > > + PHY_RESERVED)) && > > > > + ((I915_READ(BXT_PORT_CL1CM_DW0 > > > > (phy)) & > > > > + PHY_POWER_GOOD) == > > > PHY_POWER_GOOD)), 100)) { > > > > DRM_ERROR("timeout during PHY%d power on\n", > > > > phy); > > > > + } > > Please also add a comment on how the detection magic works: Reading > any > PHY register while the PHY is powered down will result in all > register > bits set, while the reserved bit 7 is guaranteed to be 0 when the PHY > is powered up. Vandana, could you resend this patch with the comments addressed? --Imre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915: BXT DDI PHY sequence BUN 2016-03-21 6:42 [PATCH] drm/i915: BXT DDI PHY sequence BUN Vandana Kannan 2016-03-21 10:20 ` Jani Nikula 2016-03-21 14:03 ` Ville Syrjälä @ 2016-03-21 14:33 ` Patchwork 2 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2016-03-21 14:33 UTC (permalink / raw) To: Vandana Kannan; +Cc: intel-gfx == Series Details == Series: drm/i915: BXT DDI PHY sequence BUN URL : https://patchwork.freedesktop.org/series/4687/ State : warning == Summary == Series 4687v1 drm/i915: BXT DDI PHY sequence BUN http://patchwork.freedesktop.org/api/1.0/series/4687/revisions/1/mbox/ Test gem_ringfill: Subgroup basic-default-s3: pass -> DMESG-WARN (bsw-nuc-2) Test kms_flip: Subgroup basic-flip-vs-wf_vblank: pass -> DMESG-WARN (hsw-gt2) fail -> PASS (bdw-ultra) Subgroup basic-plain-flip: dmesg-warn -> PASS (hsw-gt2) dmesg-warn -> PASS (hsw-brixbox) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: pass -> DMESG-WARN (snb-x220t) Test pm_rpm: Subgroup basic-pci-d3-state: pass -> DMESG-WARN (bsw-nuc-2) dmesg-warn -> PASS (snb-dellxps) dmesg-warn -> PASS (hsw-brixbox) Subgroup basic-rte: dmesg-warn -> PASS (snb-x220t) pass -> DMESG-WARN (snb-dellxps) pass -> DMESG-WARN (byt-nuc) UNSTABLE bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12 bdw-ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip:21 bsw-nuc-2 total:194 pass:155 dwarn:2 dfail:0 fail:0 skip:37 byt-nuc total:194 pass:158 dwarn:1 dfail:0 fail:0 skip:35 hsw-brixbox total:194 pass:172 dwarn:0 dfail:0 fail:0 skip:22 hsw-gt2 total:194 pass:176 dwarn:1 dfail:0 fail:0 skip:17 ilk-hp8440p total:194 pass:131 dwarn:0 dfail:0 fail:0 skip:63 ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25 skl-i5k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23 skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23 skl-nuci5 total:194 pass:183 dwarn:0 dfail:0 fail:0 skip:11 snb-dellxps total:194 pass:159 dwarn:1 dfail:0 fail:0 skip:34 snb-x220t total:194 pass:159 dwarn:1 dfail:0 fail:1 skip:33 Results at /archive/results/CI_IGT_test/Patchwork_1654/ 3b8b9e2deb9f23e1a841d0f9d80296a9759ff8f8 drm-intel-nightly: 2016y-03m-21d-13h-03m-53s UTC integration manifest 83fc3a466d0f3c0e49f50b665b16f1fa5c3b782a drm/i915: BXT DDI PHY sequence BUN _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-03-31 12:38 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-03-21 6:42 [PATCH] drm/i915: BXT DDI PHY sequence BUN Vandana Kannan 2016-03-21 10:20 ` Jani Nikula 2016-03-21 15:02 ` Jani Nikula 2016-03-21 14:03 ` Ville Syrjälä 2016-03-23 4:43 ` Kannan, Vandana 2016-03-29 12:03 ` Imre Deak 2016-03-31 12:38 ` Imre Deak 2016-03-21 14:33 ` ✗ Fi.CI.BAT: warning for " Patchwork
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