Re: [PATCH 13/15] drm/i915: Split gen2_crtc_compute_clock()

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Mar 21, 2016 at 06:00:14PM +0200, Ander Conselvan de Oliveira wrote:
> Split a GEN2 specific version from i9xx_crtc_compute_clock(). With this
> there is no need for i9xx_get_refclk() anymore, and the differences
> between platforms become more obvious.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Let's call it i8xx shall we. That's the more typical convention in the
modeset code.

Otherwise looks OK, so with that
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 91 +++++++++++++++++++++---------------
>  1 file changed, 53 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index dca5b15..245d6c6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -595,7 +595,7 @@ intel_limit(struct intel_crtc_state *crtc_state, int refclk)
>  	const intel_limit_t *limit;
>  
>  	if (IS_BROXTON(dev) || IS_CHERRYVIEW(dev) || IS_VALLEYVIEW(dev) ||
> -	    HAS_PCH_SPLIT(dev))
> +	    HAS_PCH_SPLIT(dev) || IS_GEN2(dev))
>  		limit = NULL;
>  
>  	if (IS_G4X(dev)) {
> @@ -610,13 +610,6 @@ intel_limit(struct intel_crtc_state *crtc_state, int refclk)
>  			limit = &intel_limits_i9xx_lvds;
>  		else
>  			limit = &intel_limits_i9xx_sdvo;
> -	} else {
> -		if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
> -			limit = &intel_limits_i8xx_lvds;
> -		else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
> -			limit = &intel_limits_i8xx_dvo;
> -		else
> -			limit = &intel_limits_i8xx_dac;
>  	}
>  
>  	WARN_ON(limit == NULL);
> @@ -7102,27 +7095,6 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
>  		&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
>  }
>  
> -static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state)
> -{
> -	struct drm_device *dev = crtc_state->base.crtc->dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int refclk;
> -
> -	WARN_ON(!crtc_state->base.state);
> -
> -	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
> -	    intel_panel_use_ssc(dev_priv)) {
> -		refclk = dev_priv->vbt.lvds_ssc_freq;
> -		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
> -	} else if (!IS_GEN2(dev)) {
> -		refclk = 96000;
> -	} else {
> -		refclk = 48000;
> -	}
> -
> -	return refclk;
> -}
> -
>  static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
>  {
>  	return (1 << dpll->n) << 16 | dpll->m2;
> @@ -7877,14 +7849,50 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>  	POSTING_READ(PIPECONF(intel_crtc->pipe));
>  }
>  
> +static int gen2_crtc_compute_clock(struct intel_crtc *crtc,
> +				   struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	const intel_limit_t *limit;
> +	int refclk = 48000;
> +
> +	memset(&crtc_state->dpll_hw_state, 0,
> +	       sizeof(crtc_state->dpll_hw_state));
> +
> +	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
> +		if (intel_panel_use_ssc(dev_priv)) {
> +			refclk = dev_priv->vbt.lvds_ssc_freq;
> +			DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
> +		}
> +
> +		limit = &intel_limits_i8xx_lvds;
> +	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
> +		limit = &intel_limits_i8xx_dvo;
> +	} else {
> +		limit = &intel_limits_i8xx_dac;
> +	}
> +
> +	if (!crtc_state->clock_set &&
> +	    !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> +				 refclk, NULL, &crtc_state->dpll)) {
> +		DRM_ERROR("Couldn't find PLL settings for mode!\n");
> +		return -EINVAL;
> +	}
> +
> +	i8xx_compute_dpll(crtc, crtc_state, NULL);
> +
> +	return 0;
> +}
> +
>  static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
>  				   struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int refclk;
>  	bool ok;
>  	const intel_limit_t *limit;
> +	int refclk = 96000;
>  
>  	memset(&crtc_state->dpll_hw_state, 0,
>  	       sizeof(crtc_state->dpll_hw_state));
> @@ -7892,9 +7900,13 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
>  	if (crtc_state->has_dsi_encoder)
>  		return 0;
>  
> -	if (!crtc_state->clock_set) {
> -		refclk = i9xx_get_refclk(crtc_state);
> +	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
> +	    intel_panel_use_ssc(dev_priv)) {
> +		refclk = dev_priv->vbt.lvds_ssc_freq;
> +		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
> +	}
>  
> +	if (!crtc_state->clock_set) {
>  		/*
>  		 * Returns a set of divisors for the desired target clock with
>  		 * the given refclk, or FALSE.  The returned values represent
> @@ -7912,11 +7924,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
>  		}
>  	}
>  
> -	if (IS_GEN2(dev)) {
> -		i8xx_compute_dpll(crtc, crtc_state, NULL);
> -	} else {
> -		i9xx_compute_dpll(crtc, crtc_state, NULL);
> -	}
> +	i9xx_compute_dpll(crtc, crtc_state, NULL);
>  
>  	return 0;
>  }
> @@ -14943,13 +14951,20 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>  		dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
>  		dev_priv->display.crtc_enable = valleyview_crtc_enable;
>  		dev_priv->display.crtc_disable = i9xx_crtc_disable;
> -	} else {
> +	} else if (!IS_GEN2(dev_priv)) {
>  		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
>  		dev_priv->display.get_initial_plane_config =
>  			i9xx_get_initial_plane_config;
>  		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
>  		dev_priv->display.crtc_enable = i9xx_crtc_enable;
>  		dev_priv->display.crtc_disable = i9xx_crtc_disable;
> +	} else {
> +		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
> +		dev_priv->display.get_initial_plane_config =
> +			i9xx_get_initial_plane_config;
> +		dev_priv->display.crtc_compute_clock = gen2_crtc_compute_clock;
> +		dev_priv->display.crtc_enable = i9xx_crtc_enable;
> +		dev_priv->display.crtc_disable = i9xx_crtc_disable;
>  	}
>  
>  	/* Returns the core display clock speed */
> -- 
> 2.4.3
> 
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-- 
Ville Syrjälä
Intel OTC
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