From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 02/16] drm/i915/bxt: Fix GRC code register field definitions Date: Fri, 8 Apr 2016 20:22:11 +0300 Message-ID: <20160408172211.GR4329@intel.com> References: <1459515767-29228-1-git-send-email-imre.deak@intel.com> <1459515767-29228-3-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 90B366EA46 for ; Fri, 8 Apr 2016 17:22:21 +0000 (UTC) Content-Disposition: inline In-Reply-To: <1459515767-29228-3-git-send-email-imre.deak@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Imre Deak Cc: intel-gfx@lists.freedesktop.org, Arthur J Runyan List-Id: intel-gfx@lists.freedesktop.org T24gRnJpLCBBcHIgMDEsIDIwMTYgYXQgMDQ6MDI6MzNQTSArMDMwMCwgSW1yZSBEZWFrIHdyb3Rl Ogo+IFRoaXMgaGFzIGJlZW4gY29ycmVjdGVkIGluIEJTcGVjIHF1aXRlIHNvbWUgdGltZSBhZ28s IGJ1dCB3ZSBtaXNzZWQgaXQKPiBzb21laG93LiBUaGUgd3JvbmcgZmllbGQgZGVmaW5pdGlvbnMg cmVzdWx0ZWQgaW4gY29uZmlndXJpbmcgUEhZMCB3aXRoCj4gYW4gaW5jb3JyZWN0IEdSQyB2YWx1 ZS4KPiAKPiBDQzogQXJ0aHVyIEogUnVueWFuIDxhcnRodXIuai5ydW55YW5AaW50ZWwuY29tPgo+ IFNpZ25lZC1vZmYtYnk6IEltcmUgRGVhayA8aW1yZS5kZWFrQGludGVsLmNvbT4KPiAtLS0KPiAg ZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9yZWcuaCB8IDYgKysrLS0tCj4gIDEgZmlsZSBjaGFu Z2VkLCAzIGluc2VydGlvbnMoKyksIDMgZGVsZXRpb25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2Ry aXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmggYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1 X3JlZy5oCj4gaW5kZXggNmRmM2M1OS4uZjRhOTFiYiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dw dS9kcm0vaTkxNS9pOTE1X3JlZy5oCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9y ZWcuaAo+IEBAIC0xMzczLDEwICsxMzczLDEwIEBAIGVudW0gc2tsX2Rpc3BfcG93ZXJfd2VsbHMg ewo+ICAgKiBGSVhNRTogQlNwZWMvQ0hWIENvbmZpZ0RCIGRpc2FncmVlcyBvbiB0aGUgZm9sbG93 aW5nIHR3byBmaWVsZHMsIGZpeCB0aGVtCj4gICAqIGFmdGVyIHRlc3RpbmcuCj4gICAqLwoKVGhl IEZJWE1FIGNhbiBnbywgbm8/CgpNYXRjaGVzIG15IFBIWSBkb2NzIGFzIHdlbGwgYXMgYnNwZWMg bm93LgoKUmV2aWV3ZWQtYnk6IFZpbGxlIFN5cmrDpGzDpCA8dmlsbGUuc3lyamFsYUBsaW51eC5p bnRlbC5jb20+Cgo+IC0jZGVmaW5lICAgR1JDX0NPREVfU0hJRlQJCTIzCj4gLSNkZWZpbmUgICBH UkNfQ09ERV9NQVNLCQkJKDB4MUZGIDw8IEdSQ19DT0RFX1NISUZUKQo+ICsjZGVmaW5lICAgR1JD X0NPREVfU0hJRlQJCTI0Cj4gKyNkZWZpbmUgICBHUkNfQ09ERV9NQVNLCQkJKDB4RkYgPDwgR1JD X0NPREVfU0hJRlQpCj4gICNkZWZpbmUgICBHUkNfQ09ERV9GQVNUX1NISUZUCQkxNgo+IC0jZGVm aW5lICAgR1JDX0NPREVfRkFTVF9NQVNLCQkoMHg3RiA8PCBHUkNfQ09ERV9GQVNUX1NISUZUKQo+ ICsjZGVmaW5lICAgR1JDX0NPREVfRkFTVF9NQVNLCQkoMHhGRiA8PCBHUkNfQ09ERV9GQVNUX1NI SUZUKQo+ICAjZGVmaW5lICAgR1JDX0NPREVfU0xPV19TSElGVAkJOAo+ICAjZGVmaW5lICAgR1JD X0NPREVfU0xPV19NQVNLCQkoMHhGRiA8PCBHUkNfQ09ERV9TTE9XX1NISUZUKQo+ICAjZGVmaW5l ICAgR1JDX0NPREVfTk9NX01BU0sJCTB4RkYKPiAtLSAKPiAyLjUuMAo+IAo+IF9fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4gSW50ZWwtZ2Z4IG1haWxpbmcg bGlzdAo+IEludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKPiBodHRwczovL2xpc3RzLmZy ZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAoKLS0gClZpbGxlIFN5cmrD pGzDpApJbnRlbCBPVEMKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Au b3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwt Z2Z4Cg==