public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 13/16] drm/i915/bxt: Don't reprogram an already enabled DDI PHY
Date: Fri, 8 Apr 2016 21:15:36 +0300	[thread overview]
Message-ID: <20160408181536.GW4329@intel.com> (raw)
In-Reply-To: <1459515767-29228-14-git-send-email-imre.deak@intel.com>

On Fri, Apr 01, 2016 at 04:02:44PM +0300, Imre Deak wrote:
> If BIOS has already programmed and enabled a PHY, don't reprogram it as
> that may interfere with the currently active outputs. A follow-up patch
> will add state verification, so we can catch any misconfiguration on
> BIOS's behalf.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Looks sane.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 40 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index d16effd..8f06d6c 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1722,12 +1722,52 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
>  	}
>  }
>  
> +static bool broxton_phy_is_enabled(struct drm_i915_private *dev_priv,
> +				   enum dpio_phy phy)
> +{
> +	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
> +		return false;
> +
> +	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
> +	     (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
> +		DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
> +				 phy);
> +
> +		return false;
> +	}
> +
> +	if (phy == DPIO_PHY1 &&
> +	   !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
> +		DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
> +
> +		return false;
> +	}
> +
> +	if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
> +		DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
> +				 phy);
> +
> +		return false;
> +	}
> +
> +	return true;
> +}
> +
>  static void broxton_phy_init(struct drm_i915_private *dev_priv,
>  			     enum dpio_phy phy)
>  {
>  	enum port port;
>  	u32 ports, val;
>  
> +	if (broxton_phy_is_enabled(dev_priv, phy)) {
> +		DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
> +				 "won't reprogram it\n", phy);
> +
> +		return;
> +	}
> +
> +	DRM_DEBUG_DRIVER("DDI PHY %d not enabled, enabling it\n", phy);
> +
>  	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
>  	val |= GT_DISPLAY_POWER_ON(phy);
>  	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
> -- 
> 2.5.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2016-04-08 18:15 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-01 13:02 [PATCH 00/16] drm/i915/bxt: Fix/enable display power well support/runtime PM Imre Deak
2016-04-01 13:02 ` [PATCH 01/16] drm/i915/bxt: Reject DMC firmware versions with known bugs Imre Deak
2016-04-11 12:39   ` Mika Kuoppala
2016-04-01 13:02 ` [PATCH 02/16] drm/i915/bxt: Fix GRC code register field definitions Imre Deak
2016-04-08 17:22   ` Ville Syrjälä
2016-04-08 17:27     ` Imre Deak
2016-04-01 13:02 ` [PATCH 03/16] drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only Imre Deak
2016-04-08 18:02   ` Ville Syrjälä
2016-04-08 18:12     ` Imre Deak
2016-04-08 18:16       ` Imre Deak
2016-04-12 15:11   ` David Weinehall
2016-04-01 13:02 ` [PATCH 04/16] drm/i915/bxt: Reset secondary power well requests left on by DMC/KVMR Imre Deak
2016-04-05 10:26   ` [PATCH v2 04/16] drm/i915/gen9: " Imre Deak
2016-04-06 10:59     ` Patrik Jakobsson
2016-04-01 13:02 ` [PATCH 05/16] drm/i915/gen9: Make power well disabling synchronous Imre Deak
2016-04-04 10:34   ` Patrik Jakobsson
2016-04-05  8:26     ` Patrik Jakobsson
2016-04-05  9:30       ` Imre Deak
2016-04-01 13:02 ` [PATCH 06/16] drm/i915/gen9: Fix DMC/DC state asserts Imre Deak
2016-04-04 10:52   ` Patrik Jakobsson
2016-04-01 13:02 ` [PATCH 07/16] drm/i915/bxt: Suspend power domains during suspend-to-idle Imre Deak
2016-04-04 11:28   ` Patrik Jakobsson
2016-04-01 13:02 ` [PATCH 08/16] drm/i915/skl: Unexport skl_pw1_misc_io_init Imre Deak
2016-04-04 12:30   ` Patrik Jakobsson
2016-04-04 12:34     ` Imre Deak
2016-04-04 12:42   ` [PATCH v2 " Imre Deak
2016-04-04 13:01     ` Patrik Jakobsson
2016-04-04 13:54       ` Imre Deak
2016-04-01 13:02 ` [PATCH 09/16] drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers Imre Deak
2016-04-08 18:03   ` Ville Syrjälä
2016-04-12 15:12   ` David Weinehall
2016-04-01 13:02 ` [PATCH 10/16] drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit Imre Deak
2016-04-01 13:29   ` Jani Nikula
2016-04-01 13:40     ` Imre Deak
2016-04-08 18:04   ` Ville Syrjälä
2016-04-01 13:02 ` [PATCH 11/16] drm/i915/bxt: Don't toggle power well 1 on-demand Imre Deak
2016-04-08 18:10   ` Ville Syrjälä
2016-04-01 13:02 ` [PATCH 12/16] drm/i915/bxt: Sanitize the DBUF HW state together with CDCLK Imre Deak
2016-04-11 13:19   ` Mika Kuoppala
2016-04-01 13:02 ` [PATCH 13/16] drm/i915/bxt: Don't reprogram an already enabled DDI PHY Imre Deak
2016-04-08 18:15   ` Ville Syrjälä [this message]
2016-04-01 13:02 ` [PATCH 14/16] drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK Imre Deak
2016-04-01 14:28   ` [PATCH v2 " Imre Deak
2016-04-04 14:27     ` [PATCH v3 " Imre Deak
2016-04-12 15:21       ` David Weinehall
2016-04-01 13:02 ` [PATCH 15/16] Revert "drm/i915/bxt: Disable power well support" Imre Deak
2016-04-12 15:22   ` David Weinehall
2016-04-01 13:02 ` [PATCH 16/16] drm/i915/bxt: Enable runtime PM Imre Deak
2016-04-12 15:21   ` David Weinehall
2016-04-01 13:45 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM Patchwork
2016-04-01 14:35 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev2) Patchwork
2016-04-04 14:07 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev3) Patchwork
2016-04-04 15:56 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev4) Patchwork
2016-04-05 12:19 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev5) Patchwork
2016-04-15 12:06   ` Imre Deak

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20160408181536.GW4329@intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=imre.deak@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox