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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/4] drm/i915: Fix gen8 semaphores id for legacy mode
Date: Mon, 11 Apr 2016 11:26:41 +0300	[thread overview]
Message-ID: <20160411082641.GA4329@intel.com> (raw)
In-Reply-To: <1460196886-15760-2-git-send-email-chris@chris-wilson.co.uk>

On Sat, Apr 09, 2016 at 11:14:43AM +0100, Chris Wilson wrote:
> With the introduction of a distinct engine->id vs the hardware id, we need
> to fix up the value we use for selecting the target engine when signaling
> a semaphore. Note that these values can be merged with engine->guc_id.
> 
> Fixes: de1add360522c876c25ef2bbbbab1c94bdb509ab
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++++--
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 3 ++-
>  2 files changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 6b4952031e30..556924ee47f9 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1307,7 +1307,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
>  		intel_ring_emit(signaller, seqno);
>  		intel_ring_emit(signaller, 0);
>  		intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
> -					   MI_SEMAPHORE_TARGET(waiter->id));
> +					   MI_SEMAPHORE_TARGET(waiter->hw_id));
>  		intel_ring_emit(signaller, 0);
>  	}
>  
> @@ -1347,7 +1347,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
>  		intel_ring_emit(signaller, upper_32_bits(gtt_offset));
>  		intel_ring_emit(signaller, seqno);
>  		intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
> -					   MI_SEMAPHORE_TARGET(waiter->id));
> +					   MI_SEMAPHORE_TARGET(waiter->hw_id));
>  		intel_ring_emit(signaller, 0);
>  	}
>  
> @@ -2793,6 +2793,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
>  	engine->name = "render ring";
>  	engine->id = RCS;
>  	engine->exec_id = I915_EXEC_RENDER;
> +	engine->hw_id = 0;
>  	engine->mmio_base = RENDER_RING_BASE;
>  
>  	if (INTEL_INFO(dev)->gen >= 8) {
> @@ -2942,6 +2943,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
>  	engine->name = "bsd ring";
>  	engine->id = VCS;
>  	engine->exec_id = I915_EXEC_BSD;
> +	engine->hw_id = 1;
>  
>  	engine->write_tail = ring_write_tail;
>  	if (INTEL_INFO(dev)->gen >= 6) {
> @@ -3019,6 +3021,7 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
>  	engine->name = "bsd2 ring";
>  	engine->id = VCS2;
>  	engine->exec_id = I915_EXEC_BSD;
> +	engine->hw_id = 4;
>  
>  	engine->write_tail = ring_write_tail;
>  	engine->mmio_base = GEN8_BSD2_RING_BASE;
> @@ -3050,6 +3053,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
>  	engine->name = "blitter ring";
>  	engine->id = BCS;
>  	engine->exec_id = I915_EXEC_BLT;
> +	engine->hw_id = 2;
>  
>  	engine->mmio_base = BLT_RING_BASE;
>  	engine->write_tail = ring_write_tail;
> @@ -3108,6 +3112,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
>  	engine->name = "video enhancement ring";
>  	engine->id = VECS;
>  	engine->exec_id = I915_EXEC_VEBOX;
> +	engine->hw_id = 3;
>  
>  	engine->mmio_base = VEBOX_RING_BASE;
>  	engine->write_tail = ring_write_tail;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 98eadfa79116..6efa47389276 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -155,7 +155,8 @@ struct  intel_engine_cs {
>  #define I915_NUM_ENGINES 5
>  #define _VCS(n) (VCS + (n))
>  	unsigned int exec_id;
> -	unsigned int guc_id;
> +	unsigned int hw_id;
> +	unsigned int guc_id; /* XXX same as hw_id? */
>  	u32		mmio_base;
>  	struct		drm_device *dev;
>  	struct intel_ringbuffer *buffer;
> -- 
> 2.8.0.rc3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2016-04-11  8:26 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-09 10:14 Finish gen8 legacy semaphores Chris Wilson
2016-04-09 10:14 ` [PATCH 1/4] drm/i915: Fix gen8 semaphores id for legacy mode Chris Wilson
2016-04-11  8:26   ` Ville Syrjälä [this message]
2016-04-09 10:14 ` [PATCH 2/4] drm/i915: Fix serialisation of pipecontrol write vs semaphore signal Chris Wilson
2016-04-11  8:34   ` Ville Syrjälä
2016-04-11  9:06     ` Chris Wilson
2016-04-14 14:29       ` Ville Syrjälä
2016-04-14 14:33         ` Ville Syrjälä
2016-04-14 16:09         ` Chris Wilson
2016-04-09 10:14 ` [PATCH 3/4] drm/i915: Reload PD tables after semaphore wait on gen8 Chris Wilson
2016-04-11  7:34   ` Ville Syrjälä
2016-04-11  8:16     ` Chris Wilson
2016-04-11  8:37       ` Ville Syrjälä
2016-04-09 10:14 ` [PATCH 4/4] drm/i915: Enable semaphores for legacy submission " Chris Wilson
2016-04-09 11:02 ` ✗ Fi.CI.BAT: warning for series starting with [1/4] drm/i915: Fix gen8 semaphores id for legacy mode Patchwork

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