public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: David Weinehall <david.weinehall@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 09/16] drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers
Date: Tue, 12 Apr 2016 18:12:35 +0300	[thread overview]
Message-ID: <20160412151235.GD18193@boom> (raw)
In-Reply-To: <1459515767-29228-10-git-send-email-imre.deak@intel.com>

On Fri, Apr 01, 2016 at 04:02:40PM +0300, Imre Deak wrote:
> For internal APIs passing dev_priv is preferred to reduce indirections,
> so convert over a few DDI PHY, CDCLK helpers.
> 
> No functional change.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: David Weinehall <david.weinehall@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c       | 12 ++++--------
>  drivers/gpu/drm/i915/intel_ddi.c      | 10 ++++------
>  drivers/gpu/drm/i915/intel_display.c  | 18 +++++++-----------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c |  4 ++--
>  drivers/gpu/drm/i915/intel_drv.h      |  8 ++++----
>  5 files changed, 21 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index aa7df10..3998f6a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1070,12 +1070,10 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
>  
>  static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_device *dev = dev_priv->dev;
> -
>  	/* TODO: when DC5 support is added disable DC5 here. */
>  
> -	broxton_ddi_phy_uninit(dev);
> -	broxton_uninit_cdclk(dev);
> +	broxton_ddi_phy_uninit(dev_priv);
> +	broxton_uninit_cdclk(dev_priv);
>  	bxt_enable_dc9(dev_priv);
>  
>  	return 0;
> @@ -1083,8 +1081,6 @@ static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
>  
>  static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_device *dev = dev_priv->dev;
> -
>  	/* TODO: when CSR FW support is added make sure the FW is loaded */
>  
>  	bxt_disable_dc9(dev_priv);
> @@ -1093,8 +1089,8 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
>  	 * TODO: when DC5 support is added enable DC5 here if the CSR FW
>  	 * is available.
>  	 */
> -	broxton_init_cdclk(dev);
> -	broxton_ddi_phy_init(dev);
> +	broxton_init_cdclk(dev_priv);
> +	broxton_ddi_phy_init(dev_priv);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index f91306e..29017a4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1834,11 +1834,11 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
>  	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
>  }
>  
> -void broxton_ddi_phy_init(struct drm_device *dev)
> +void broxton_ddi_phy_init(struct drm_i915_private *dev_priv)
>  {
>  	/* Enable PHY1 first since it provides Rcomp for PHY0 */
> -	broxton_phy_init(dev->dev_private, DPIO_PHY1);
> -	broxton_phy_init(dev->dev_private, DPIO_PHY0);
> +	broxton_phy_init(dev_priv, DPIO_PHY1);
> +	broxton_phy_init(dev_priv, DPIO_PHY0);
>  }
>  
>  static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
> @@ -1851,10 +1851,8 @@ static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
>  	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
>  }
>  
> -void broxton_ddi_phy_uninit(struct drm_device *dev)
> +void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -
>  	broxton_phy_uninit(dev_priv, DPIO_PHY1);
>  	broxton_phy_uninit(dev_priv, DPIO_PHY0);
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e6b5ee5..d9da89d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5322,9 +5322,8 @@ static void intel_update_cdclk(struct drm_device *dev)
>  		intel_update_max_cdclk(dev);
>  }
>  
> -static void broxton_set_cdclk(struct drm_device *dev, int frequency)
> +static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int frequency)
>  {
> -	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t divider;
>  	uint32_t ratio;
>  	uint32_t current_freq;
> @@ -5438,12 +5437,11 @@ static void broxton_set_cdclk(struct drm_device *dev, int frequency)
>  		return;
>  	}
>  
> -	intel_update_cdclk(dev);
> +	intel_update_cdclk(dev_priv->dev);
>  }
>  
> -void broxton_init_cdclk(struct drm_device *dev)
> +void broxton_init_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t val;
>  
>  	/*
> @@ -5472,7 +5470,7 @@ void broxton_init_cdclk(struct drm_device *dev)
>  	 * - check if setting the max (or any) cdclk freq is really necessary
>  	 *   here, it belongs to modeset time
>  	 */
> -	broxton_set_cdclk(dev, 624000);
> +	broxton_set_cdclk(dev_priv, 624000);
>  
>  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
>  	POSTING_READ(DBUF_CTL);
> @@ -5483,10 +5481,8 @@ void broxton_init_cdclk(struct drm_device *dev)
>  		DRM_ERROR("DBuf power enable timeout!\n");
>  }
>  
> -void broxton_uninit_cdclk(struct drm_device *dev)
> +void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -
>  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
>  	POSTING_READ(DBUF_CTL);
>  
> @@ -5496,7 +5492,7 @@ void broxton_uninit_cdclk(struct drm_device *dev)
>  		DRM_ERROR("DBuf power disable timeout!\n");
>  
>  	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
> -	broxton_set_cdclk(dev, 19200);
> +	broxton_set_cdclk(dev_priv, 19200);
>  
>  	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
>  }
> @@ -9532,7 +9528,7 @@ static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>  		to_intel_atomic_state(old_state);
>  	unsigned int req_cdclk = old_intel_state->dev_cdclk;
>  
> -	broxton_set_cdclk(dev, req_cdclk);
> +	broxton_set_cdclk(to_i915(dev), req_cdclk);
>  }
>  
>  /* compute the max rate for new configuration */
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 1175eeb..fbe88b8 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1645,8 +1645,8 @@ static void intel_ddi_pll_init(struct drm_device *dev)
>  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
>  			DRM_ERROR("LCPLL1 is disabled\n");
>  	} else if (IS_BROXTON(dev)) {
> -		broxton_init_cdclk(dev);
> -		broxton_ddi_phy_init(dev);
> +		broxton_init_cdclk(dev_priv);
> +		broxton_ddi_phy_init(dev_priv);
>  	} else {
>  		/*
>  		 * The LCPLL register should be turned on by the BIOS. For now
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 8ba2ac3..e8843a7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1222,10 +1222,10 @@ void intel_prepare_reset(struct drm_device *dev);
>  void intel_finish_reset(struct drm_device *dev);
>  void hsw_enable_pc8(struct drm_i915_private *dev_priv);
>  void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> -void broxton_init_cdclk(struct drm_device *dev);
> -void broxton_uninit_cdclk(struct drm_device *dev);
> -void broxton_ddi_phy_init(struct drm_device *dev);
> -void broxton_ddi_phy_uninit(struct drm_device *dev);
> +void broxton_init_cdclk(struct drm_i915_private *dev_priv);
> +void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
> +void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
> +void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
>  void bxt_enable_dc9(struct drm_i915_private *dev_priv);
>  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>  void skl_init_cdclk(struct drm_i915_private *dev_priv);
> -- 
> 2.5.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2016-04-12 15:14 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-01 13:02 [PATCH 00/16] drm/i915/bxt: Fix/enable display power well support/runtime PM Imre Deak
2016-04-01 13:02 ` [PATCH 01/16] drm/i915/bxt: Reject DMC firmware versions with known bugs Imre Deak
2016-04-11 12:39   ` Mika Kuoppala
2016-04-01 13:02 ` [PATCH 02/16] drm/i915/bxt: Fix GRC code register field definitions Imre Deak
2016-04-08 17:22   ` Ville Syrjälä
2016-04-08 17:27     ` Imre Deak
2016-04-01 13:02 ` [PATCH 03/16] drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only Imre Deak
2016-04-08 18:02   ` Ville Syrjälä
2016-04-08 18:12     ` Imre Deak
2016-04-08 18:16       ` Imre Deak
2016-04-12 15:11   ` David Weinehall
2016-04-01 13:02 ` [PATCH 04/16] drm/i915/bxt: Reset secondary power well requests left on by DMC/KVMR Imre Deak
2016-04-05 10:26   ` [PATCH v2 04/16] drm/i915/gen9: " Imre Deak
2016-04-06 10:59     ` Patrik Jakobsson
2016-04-01 13:02 ` [PATCH 05/16] drm/i915/gen9: Make power well disabling synchronous Imre Deak
2016-04-04 10:34   ` Patrik Jakobsson
2016-04-05  8:26     ` Patrik Jakobsson
2016-04-05  9:30       ` Imre Deak
2016-04-01 13:02 ` [PATCH 06/16] drm/i915/gen9: Fix DMC/DC state asserts Imre Deak
2016-04-04 10:52   ` Patrik Jakobsson
2016-04-01 13:02 ` [PATCH 07/16] drm/i915/bxt: Suspend power domains during suspend-to-idle Imre Deak
2016-04-04 11:28   ` Patrik Jakobsson
2016-04-01 13:02 ` [PATCH 08/16] drm/i915/skl: Unexport skl_pw1_misc_io_init Imre Deak
2016-04-04 12:30   ` Patrik Jakobsson
2016-04-04 12:34     ` Imre Deak
2016-04-04 12:42   ` [PATCH v2 " Imre Deak
2016-04-04 13:01     ` Patrik Jakobsson
2016-04-04 13:54       ` Imre Deak
2016-04-01 13:02 ` [PATCH 09/16] drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpers Imre Deak
2016-04-08 18:03   ` Ville Syrjälä
2016-04-12 15:12   ` David Weinehall [this message]
2016-04-01 13:02 ` [PATCH 10/16] drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninit Imre Deak
2016-04-01 13:29   ` Jani Nikula
2016-04-01 13:40     ` Imre Deak
2016-04-08 18:04   ` Ville Syrjälä
2016-04-01 13:02 ` [PATCH 11/16] drm/i915/bxt: Don't toggle power well 1 on-demand Imre Deak
2016-04-08 18:10   ` Ville Syrjälä
2016-04-01 13:02 ` [PATCH 12/16] drm/i915/bxt: Sanitize the DBUF HW state together with CDCLK Imre Deak
2016-04-11 13:19   ` Mika Kuoppala
2016-04-01 13:02 ` [PATCH 13/16] drm/i915/bxt: Don't reprogram an already enabled DDI PHY Imre Deak
2016-04-08 18:15   ` Ville Syrjälä
2016-04-01 13:02 ` [PATCH 14/16] drm/i915/bxt: Add HW state verification for DDI PHY and CDCLK Imre Deak
2016-04-01 14:28   ` [PATCH v2 " Imre Deak
2016-04-04 14:27     ` [PATCH v3 " Imre Deak
2016-04-12 15:21       ` David Weinehall
2016-04-01 13:02 ` [PATCH 15/16] Revert "drm/i915/bxt: Disable power well support" Imre Deak
2016-04-12 15:22   ` David Weinehall
2016-04-01 13:02 ` [PATCH 16/16] drm/i915/bxt: Enable runtime PM Imre Deak
2016-04-12 15:21   ` David Weinehall
2016-04-01 13:45 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM Patchwork
2016-04-01 14:35 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev2) Patchwork
2016-04-04 14:07 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev3) Patchwork
2016-04-04 15:56 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev4) Patchwork
2016-04-05 12:19 ` ✓ Fi.CI.BAT: success for drm/i915/bxt: Fix/enable display power well support/runtime PM (rev5) Patchwork
2016-04-15 12:06   ` Imre Deak

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20160412151235.GD18193@boom \
    --to=david.weinehall@linux.intel.com \
    --cc=imre.deak@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox