From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>,
intel-gfx@lists.freedesktop.org,
Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Subject: Re: [PATCH 05/12] drm/i915: Clear VLV_IER around irq processing
Date: Thu, 14 Apr 2016 11:49:28 +0300 [thread overview]
Message-ID: <20160414084928.GG4329@intel.com> (raw)
In-Reply-To: <20160414083230.GA5111@nuc-i3427.alporthouse.com>
On Thu, Apr 14, 2016 at 09:32:30AM +0100, Chris Wilson wrote:
> On Thu, Apr 14, 2016 at 11:22:48AM +0300, Ville Syrjälä wrote:
> > On Wed, Apr 13, 2016 at 09:53:38PM +0100, Chris Wilson wrote:
> > > On Wed, Apr 13, 2016 at 09:19:51PM +0300, ville.syrjala@linux.intel.com wrote:
> > > > + /*
> > > > + * Theory on interrupt generation, based on empirical evidence:
> > > > + *
> > > > + * x = ((VLV_IIR & VLV_IER) ||
> > > > + * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
> > > > + * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
> > > > + *
> > > > + * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
> > > > + * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
> > > > + * guarantee the CPU interrupt will be raised again even if we
> > > > + * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
> > > > + * bits this time around.
> > >
> > > Following this logic, we want to enable MASTER_IER before VLV_IER such
> > > that we get an immediate irq if there is a residual VLV_IIR.
> >
> > The order between master irq enable and VLV_IIR shouldn't matter. They
> > are totally independent of each other. Master irq enable is for GT,
> > VLV_IER is for display. We just have to make sure both of them are
> > going to be zero simultaneously, which will guarantee that the CPU
> > interrupt generation logic will see x==0 at that point.
>
> There is no flow from VLV_IER to VLV_MASTER_IER ?
Nope. The master only handles GT interrupts.
>
> Hmm, I guess it only matters if the interrupt is raised on the leading
> edge versus the level. I presumed we had only edge triggered interrupts,
> that is the signal is sent fom VLV_IIR & VLV_IER once and will not
> result in an interrupt unless VLV_MASTER_IER is enabled.
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2016-04-14 8:49 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-13 18:19 [PATCH 00/12] drm/i915: VLV/CHV irq handler fixes ville.syrjala
2016-04-13 18:19 ` [PATCH 01/12] drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistently ville.syrjala
2016-04-13 18:19 ` [PATCH 02/12] drm/i915: Set up VLV_MASTER_IER consistently ville.syrjala
2016-04-13 18:19 ` [PATCH 03/12] drm/i915: Clear VLV_IIR after PIPESTAT ville.syrjala
2016-04-13 18:19 ` [PATCH 04/12] drm/i915: Clear VLV_MASTER_IER around irq processing ville.syrjala
2016-04-13 18:19 ` [PATCH 05/12] drm/i915: Clear VLV_IER " ville.syrjala
2016-04-13 20:53 ` Chris Wilson
2016-04-14 8:22 ` Ville Syrjälä
2016-04-14 8:32 ` Chris Wilson
2016-04-14 8:49 ` Ville Syrjälä [this message]
2016-04-14 9:36 ` Chris Wilson
2016-04-14 12:30 ` Ville Syrjälä
2016-04-14 12:47 ` Mika Kuoppala
2016-04-15 7:32 ` Mika Kuoppala
2016-04-13 18:19 ` [PATCH 06/12] drm/i915: Eliminate loop from VLV irq handler ville.syrjala
2016-04-13 18:19 ` [PATCH 07/12] drm/i915: Move variables to narrower scope in VLV/CHV irq handlers ville.syrjala
2016-04-13 18:19 ` [PATCH 08/12] drm/i915: Split PORT_HOTPLUG_STAT ack out from i9xx_hpd_irq_handler() ville.syrjala
2016-04-13 18:19 ` [PATCH 09/12] drm/i915: Split VLV/CVH PIPESTAT handling into ack+handler ville.syrjala
2016-04-13 18:19 ` [PATCH 10/12] drm/i915: Move gt/pm irq handling out from irq disabled section on VLV ville.syrjala
2016-04-13 18:19 ` [PATCH 11/12] drm/i915: Eliminate passing dev+dev_priv to {snb, ilk}_gt_irq_handler() ville.syrjala
2016-04-13 21:02 ` Daniel Vetter
2016-04-13 18:19 ` [PATCH 12/12] drm/i915: Split gen8_gt_irq_handler into ack+handle ville.syrjala
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