From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915/dsi: fix CHV dsi encoder hardware state readout on port C Date: Fri, 15 Apr 2016 15:54:22 +0300 Message-ID: <20160415125422.GU4329@intel.com> References: <1460724451-13810-1-git-send-email-jani.nikula@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <1460724451-13810-1-git-send-email-jani.nikula@intel.com> Sender: stable-owner@vger.kernel.org To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Apr 15, 2016 at 03:47:31PM +0300, Jani Nikula wrote: > Due to "some hardware limitation" the DPI enable bit in port C contro= l > register does not get set on VLV. As a workaround we check the status= in > pipe B conf register instead. The workaround was added in >=20 > commit c0beefd29fcb1ca998f0f9ba41be8539f8eeba9b > Author: Gaurav K Singh > Date: Tue Dec 9 10:59:20 2014 +0530 >=20 > drm/i915: Software workaround for getting the HW status of DSI Po= rt C on BYT >=20 > Empirical evidence (on Surface 3 with DSI on port C per VBT) shows th= at > this is the case also on CHV, so extend the workaround to CHV. We sti= ll > have the device ready register check in place, so this should not get > confused with e.g. HDMI on pipe B. >=20 > This fixes a number of state checker warnings on CHV DSI port C. >=20 > Cc: stable@vger.kernel.org > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_dsi.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/= intel_dsi.c > index 9ff6435e7d38..f57adb0f0ee4 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -722,11 +722,12 @@ static bool intel_dsi_get_hw_state(struct intel= _encoder *encoder, > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); > bool enabled =3D I915_READ(ctrl_reg) & DPI_ENABLE; > =20 > - /* Due to some hardware limitations on BYT, MIPI Port C DPI > - * Enable bit does not get set. To check whether DSI Port C > - * was enabled in BIOS, check the Pipe B enable bit > + /* > + * Due to some hardware limitations on VLV/CHV, the DPI enable > + * bit in port C control register does not get set. As a > + * workaround, check pipe B conf instead. > */ > - if (IS_VALLEYVIEW(dev) && port =3D=3D PORT_C) > + if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && port =3D=3D PORT= _C) > enabled =3D I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; I saw your register dumps, so I believe it. Reviewed-by: Ville Syrj=E4l=E4 > =20 > /* Try command mode if video mode not enabled */ > --=20 > 2.1.4 --=20 Ville Syrj=E4l=E4 Intel OTC