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From: Jim Bride <jim.bride@linux.intel.com>
To: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 03/10] drm/i915: Unduplicate chv_data_lane_soft_reset()
Date: Wed, 20 Apr 2016 12:24:01 -0700	[thread overview]
Message-ID: <20160420192401.GD13777@shiv> (raw)
In-Reply-To: <1460569673-13694-4-git-send-email-ander.conselvan.de.oliveira@intel.com>

On Wed, Apr 13, 2016 at 08:47:46PM +0300, Ander Conselvan de Oliveira wrote:
> The function chv_data_lane_soft_reset() was duplicated in DP and HDMI
> code. Move it to intel_dpio_phy.c.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  2 ++
>  drivers/gpu/drm/i915/intel_dp.c       | 44 -----------------------------------
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 43 ++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_hdmi.c     | 44 -----------------------------------
>  4 files changed, 45 insertions(+), 88 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 233198d..fe40761 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3558,6 +3558,8 @@ void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>  void chv_set_phy_signal_level(struct intel_encoder *encoder,
>  			      u32 deemph_reg_value, u32 margin_reg_value,
>  			      bool uniq_trans_scale);
> +void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> +			      bool reset);
>  
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c2f774c..4d63071 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2451,50 +2451,6 @@ static void vlv_post_disable_dp(struct intel_encoder *encoder)
>  	intel_dp_link_down(intel_dp);
>  }
>  
> -static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> -				     bool reset)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
> -	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> -	enum pipe pipe = crtc->pipe;
> -	uint32_t val;
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> -	if (reset)
> -		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -	else
> -		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> -
> -	if (crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> -		if (reset)
> -			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -		else
> -			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> -	}
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> -	val |= CHV_PCS_REQ_SOFTRESET_EN;
> -	if (reset)
> -		val &= ~DPIO_PCS_CLK_SOFT_RESET;
> -	else
> -		val |= DPIO_PCS_CLK_SOFT_RESET;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> -
> -	if (crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> -		val |= CHV_PCS_REQ_SOFTRESET_EN;
> -		if (reset)
> -			val &= ~DPIO_PCS_CLK_SOFT_RESET;
> -		else
> -			val |= DPIO_PCS_CLK_SOFT_RESET;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> -	}
> -}
> -
>  static void chv_post_disable_dp(struct intel_encoder *encoder)
>  {
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index cbe1703d..9854c93 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -120,3 +120,46 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
>  
>  }
>  
> +void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> +			      bool reset)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
> +	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> +	enum pipe pipe = crtc->pipe;
> +	uint32_t val;
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> +	if (reset)
> +		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +	else
> +		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> +
> +	if (crtc->config->lane_count > 2) {
> +		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> +		if (reset)
> +			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> +		else
> +			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> +		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> +	}
> +
> +	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> +	val |= CHV_PCS_REQ_SOFTRESET_EN;
> +	if (reset)
> +		val &= ~DPIO_PCS_CLK_SOFT_RESET;
> +	else
> +		val |= DPIO_PCS_CLK_SOFT_RESET;
> +	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> +
> +	if (crtc->config->lane_count > 2) {
> +		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> +		val |= CHV_PCS_REQ_SOFTRESET_EN;
> +		if (reset)
> +			val &= ~DPIO_PCS_CLK_SOFT_RESET;
> +		else
> +			val |= DPIO_PCS_CLK_SOFT_RESET;
> +		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> +	}
> +}
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index eed46c2..d1c0be5 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1658,50 +1658,6 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
>  
> -static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> -				     bool reset)
> -{
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
> -	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> -	enum pipe pipe = crtc->pipe;
> -	uint32_t val;
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
> -	if (reset)
> -		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -	else
> -		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
> -
> -	if (crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> -		if (reset)
> -			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> -		else
> -			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> -	}
> -
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> -	val |= CHV_PCS_REQ_SOFTRESET_EN;
> -	if (reset)
> -		val &= ~DPIO_PCS_CLK_SOFT_RESET;
> -	else
> -		val |= DPIO_PCS_CLK_SOFT_RESET;
> -	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
> -
> -	if (crtc->config->lane_count > 2) {
> -		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> -		val |= CHV_PCS_REQ_SOFTRESET_EN;
> -		if (reset)
> -			val &= ~DPIO_PCS_CLK_SOFT_RESET;
> -		else
> -			val |= DPIO_PCS_CLK_SOFT_RESET;
> -		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> -	}
> -}
> -
>  static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  {
>  	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> -- 
> 2.4.11
> 
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  reply	other threads:[~2016-04-20 19:24 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-13 17:47 [PATCH v2 00/10] Unduplicate CHV phy code Ander Conselvan de Oliveira
2016-04-13 17:47 ` [PATCH v2 01/10] drm/i915: Set crtc_state->lane_count for HDMI Ander Conselvan de Oliveira
2016-04-19 20:40   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 02/10] drm/i915: Unduplicate CHV signal level code Ander Conselvan de Oliveira
2016-04-20 19:13   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 03/10] drm/i915: Unduplicate chv_data_lane_soft_reset() Ander Conselvan de Oliveira
2016-04-20 19:24   ` Jim Bride [this message]
2016-04-13 17:47 ` [PATCH v2 04/10] drm/i915: Unduplicate CHV phy-releated pre pll enabling code Ander Conselvan de Oliveira
2016-04-20 19:45   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 05/10] drm/i915: Unduplicate CHV pre-encoder enabling phy logic Ander Conselvan de Oliveira
2016-04-20 19:48   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 06/10] drm/i915: Undiplicate CHV encoders' post pll disable code Ander Conselvan de Oliveira
2016-04-19 20:42   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 07/10] drm/i915: Undiplicate VLV signal level code Ander Conselvan de Oliveira
2016-04-19 20:37   ` Jim Bride
2016-04-19 20:45     ` Jim Bride
2016-04-20  5:23     ` Conselvan De Oliveira, Ander
2016-04-13 17:47 ` [PATCH v2 08/10] drm/i915: Unduplicate VLV phy pre pll enabling code Ander Conselvan de Oliveira
2016-04-20 19:50   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 09/10] drm/i915: Unduplicate pre encoder enabling phy code Ander Conselvan de Oliveira
2016-04-20 19:52   ` Jim Bride
2016-04-13 17:47 ` [PATCH v2 10/10] drm/i915: Move VLV HDMI lane reset work around logic to intel_dpio_phy.c Ander Conselvan de Oliveira
2016-04-20 19:53   ` Jim Bride
2016-04-14 13:03 ` ✗ Fi.CI.BAT: failure for Unduplicate CHV phy code (rev3) Patchwork
2016-04-20  5:20 ` [PATCH v2 06/18] drm/i915: Unduplicate CHV encoders' post pll disable code Ander Conselvan de Oliveira
2016-04-20 17:20   ` Jim Bride
2016-04-20  5:22 ` [PATCH v2 07/18] drm/i915: Undiplicate VLV signal level code Ander Conselvan de Oliveira
2016-04-20 18:01   ` Jim Bride

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