Re: [PATCH v2 4/4] drm/i915/bxt: Tune L3 SQC credits based on actual latencies

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [PATCH v2 4/4] drm/i915/bxt: Tune L3 SQC credits based on actual latencies
Date: Tue, 26 Apr 2016 19:53:44 +0300	[thread overview]
Message-ID: <20160426165344.GY4329@intel.com> (raw)
In-Reply-To: <1461688892-5617-1-git-send-email-imre.deak@intel.com>

On Tue, Apr 26, 2016 at 07:41:32PM +0300, Imre Deak wrote:
> BSpec says we need to fine tune these values, so comply. I checked this
> with random GPU benchmarks and it does seem to improve things.
> 
> Note that I considered to program this from the ring as part of the
> context specific workarounds there, I decided against that for the
> following reasons:
> - It's not a context specific setting, it's part of whatever (power-)
>   context the GPU manages regardless of context scheduling to
>   save/restore things across power transitions. So it's enough to
>   program it once.
> - Atm, we don't apply workarounds for engines other than the render
>   engine from the ring (although this could be added if needed).
> - The same setting is programmed via MMIO for BDW/CHV/VLV and it
>   makes sense to program it the same way on BXT too.
> 
> v2:
> - Specify the actual WA we're implementing. (Ville)
> 
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> CC: Mika Kuoppala <mika.kuoppala@intel.com>
> CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b217c44..6853bf8 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -76,6 +76,17 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>  	if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
>  		I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
>  			   PWM1_GATING_DIS | PWM2_GATING_DIS);
> +
> +	/*
> +	 * WaProgramL3SqcReg1DefaultForPerf:bxt
> +	 * Note that for dynamic reprogramming we'd need to do a stalling flush
> +	 * operation, but we can do away with that here, since the GPU is idle
> +	 * at this point.
> +	 */
> +	if (IS_BXT_REVID(dev_priv, BXT_REVID_A1, REVID_FOREVER))
> +		I915_WRITE(GEN8_L3SQCREG1,
> +			   L3_GENERAL_PRIO_CREDITS(62) |
> +			   L3_HIGH_PRIO_CREDITS(2));
>  }
>  
>  static void i915_pineview_get_mem_freq(struct drm_device *dev)
> -- 
> 2.5.0

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx