[PATCH v5 0/3] drm/i915/dsi: improved gpio element support for vlv/chv/bxt

[PATCH v5 0/3] drm/i915/dsi: improved gpio element support for vlv/chv/bxt

[Jani Nikula]

Series v5 after [1]. I'll call it *series* v5 because the last one was
v4 although the patches are of all sorts of versions and I've lost
track. The bxt patch is still hacky.

BR,
Jani.

[1] http://mid.gmane.org/cover.1460039033.git.jani.nikula@intel.com

Jani Nikula (3):
  drm/i915/dsi: add support for sequence block v3 gpio for VLV
  drm/i915/dsi: add support for gpio elements on CHV
  drm/i915/bxt: add bxt dsi gpio element support

 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 102 ++++++++++++++++++++++++++++-
 1 file changed, 99 insertions(+), 3 deletions(-)

-- 
2.1.4

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[PATCH v5 1/3] drm/i915/dsi: add support for sequence block v3 gpio for VLV

[Jani Nikula]

Only support NC GPIOs for now, and assume the vlv gpio table only has NC
GPIOs for now.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index c7281c391d0f..a1cc8533cff5 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -203,8 +203,8 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
 	map = &vlv_gpio_table[gpio_index];
 
 	if (dev_priv->vbt.dsi.seq_version >= 3) {
-		DRM_DEBUG_KMS("GPIO element v3 not supported\n");
-		return;
+		/* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
+		port = IOSF_PORT_GPIO_NC;
 	} else {
 		if (gpio_source == 0) {
 			port = IOSF_PORT_GPIO_NC;
-- 
2.1.4

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Re: [PATCH v5 1/3] drm/i915/dsi: add support for sequence block v3 gpio for VLV

[Daniel Vetter]

On Tue, Apr 26, 2016 at 01:27:39PM +0300, Jani Nikula wrote:
> Only support NC GPIOs for now, and assume the vlv gpio table only has NC
> GPIOs for now.

What is an "NC"? I think at least the commit message should explain that,
maybe even the code ...
-Daniel

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index c7281c391d0f..a1cc8533cff5 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -203,8 +203,8 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
>  	map = &vlv_gpio_table[gpio_index];
>  
>  	if (dev_priv->vbt.dsi.seq_version >= 3) {
> -		DRM_DEBUG_KMS("GPIO element v3 not supported\n");
> -		return;
> +		/* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
> +		port = IOSF_PORT_GPIO_NC;
>  	} else {
>  		if (gpio_source == 0) {
>  			port = IOSF_PORT_GPIO_NC;
> -- 
> 2.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH v5 1/3] drm/i915/dsi: add support for sequence block v3 gpio for VLV

[Jani Nikula]

On Tue, 26 Apr 2016, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Tue, Apr 26, 2016 at 01:27:39PM +0300, Jani Nikula wrote:
>> Only support NC GPIOs for now, and assume the vlv gpio table only has NC
>> GPIOs for now.
>
> What is an "NC"? I think at least the commit message should explain that,
> maybe even the code ...

The specs refer to both North Complex and Cluster. I updated the commit
message while pushing... but somehow managed to write North Core in
there. *facepalm*. -EDECAF.

Anyway it's just geography, and CHV has intercardinal directions as
well.


BR,
Jani.


> -Daniel
>
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index c7281c391d0f..a1cc8533cff5 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -203,8 +203,8 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
>>  	map = &vlv_gpio_table[gpio_index];
>>  
>>  	if (dev_priv->vbt.dsi.seq_version >= 3) {
>> -		DRM_DEBUG_KMS("GPIO element v3 not supported\n");
>> -		return;
>> +		/* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
>> +		port = IOSF_PORT_GPIO_NC;
>>  	} else {
>>  		if (gpio_source == 0) {
>>  			port = IOSF_PORT_GPIO_NC;
>> -- 
>> 2.1.4
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH v5 1/3] drm/i915/dsi: add support for sequence block v3 gpio for VLV

[Ville Syrjälä]

On Tue, Apr 26, 2016 at 01:27:39PM +0300, Jani Nikula wrote:
> Only support NC GPIOs for now, and assume the vlv gpio table only has NC
> GPIOs for now.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index c7281c391d0f..a1cc8533cff5 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -203,8 +203,8 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
>  	map = &vlv_gpio_table[gpio_index];
>  
>  	if (dev_priv->vbt.dsi.seq_version >= 3) {
> -		DRM_DEBUG_KMS("GPIO element v3 not supported\n");
> -		return;
> +		/* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
> +		port = IOSF_PORT_GPIO_NC;

NC GPIOs start from index 0, and we accept them up to ARRAY_SIZE(vlv_gpio_table)
which only holds NC GPIOs as the comment says. Since SC GPIOs would come after
NC GPIOS in index, they would thus have been rejected already by the earlier
check. Makes sense, but I had to actually read the code to see it.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  	} else {
>  		if (gpio_source == 0) {
>  			port = IOSF_PORT_GPIO_NC;
> -- 
> 2.1.4

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v5 1/3] drm/i915/dsi: add support for sequence block v3 gpio for VLV

[Jani Nikula]

On Tue, 26 Apr 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Apr 26, 2016 at 01:27:39PM +0300, Jani Nikula wrote:
>> Only support NC GPIOs for now, and assume the vlv gpio table only has NC
>> GPIOs for now.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> index c7281c391d0f..a1cc8533cff5 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> @@ -203,8 +203,8 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
>>  	map = &vlv_gpio_table[gpio_index];
>>  
>>  	if (dev_priv->vbt.dsi.seq_version >= 3) {
>> -		DRM_DEBUG_KMS("GPIO element v3 not supported\n");
>> -		return;
>> +		/* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
>> +		port = IOSF_PORT_GPIO_NC;
>
> NC GPIOs start from index 0, and we accept them up to ARRAY_SIZE(vlv_gpio_table)
> which only holds NC GPIOs as the comment says. Since SC GPIOs would come after
> NC GPIOS in index, they would thus have been rejected already by the earlier
> check. Makes sense, but I had to actually read the code to see it.

Hey, at least I left you a breadcrumb in the form of that comment
there. ;)

Pushed 1-2 to drm-intel-next-queued, thanks for the review.

BR,
Jani.



>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>>  	} else {
>>  		if (gpio_source == 0) {
>>  			port = IOSF_PORT_GPIO_NC;
>> -- 
>> 2.1.4

-- 
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[PATCH v5 2/3] drm/i915/dsi: add support for gpio elements on CHV

[Jani Nikula]

Add support for CHV gpio programming in DSI gpio elements.

v2: Overhaul macros according to Ville's review.

v3: Address Ville's review:
 - swap E and SE gpio ranges
 - add a note about max SE index
 - use GPO, not HIZ
 - swap cfg0 and cfg1

v4: fix port for dsi sequence versions 1 and 2

[Rewritten by Jani, based on earlier work by Yogesh and Deepak.]

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 70 ++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index a1cc8533cff5..f122484bedfc 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -95,6 +95,24 @@ static struct gpio_map vlv_gpio_table[] = {
 	{ VLV_GPIO_NC_11_PANEL1_BKLTCTL },
 };
 
+#define CHV_GPIO_IDX_START_N		0
+#define CHV_GPIO_IDX_START_E		73
+#define CHV_GPIO_IDX_START_SW		100
+#define CHV_GPIO_IDX_START_SE		198
+
+#define CHV_VBT_MAX_PINS_PER_FMLY	15
+
+#define CHV_GPIO_PAD_CFG0(f, i)		(0x4400 + (f) * 0x400 + (i) * 8)
+#define  CHV_GPIO_GPIOEN		(1 << 15)
+#define  CHV_GPIO_GPIOCFG_GPIO		(0 << 8)
+#define  CHV_GPIO_GPIOCFG_GPO		(1 << 8)
+#define  CHV_GPIO_GPIOCFG_GPI		(2 << 8)
+#define  CHV_GPIO_GPIOCFG_HIZ		(3 << 8)
+#define  CHV_GPIO_GPIOTXSTATE(state)	((!!(state)) << 1)
+
+#define CHV_GPIO_PAD_CFG1(f, i)		(0x4400 + (f) * 0x400 + (i) * 8 + 4)
+#define  CHV_GPIO_CFGLOCK		(1 << 31)
+
 static inline enum port intel_dsi_seq_port_to_port(u8 port)
 {
 	return port ? PORT_C : PORT_A;
@@ -232,6 +250,56 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
 	mutex_unlock(&dev_priv->sb_lock);
 }
 
+static void chv_exec_gpio(struct drm_i915_private *dev_priv,
+			  u8 gpio_source, u8 gpio_index, bool value)
+{
+	u16 cfg0, cfg1;
+	u16 family_num;
+	u8 port;
+
+	if (dev_priv->vbt.dsi.seq_version >= 3) {
+		if (gpio_index >= CHV_GPIO_IDX_START_SE) {
+			/* XXX: it's unclear whether 255->57 is part of SE. */
+			gpio_index -= CHV_GPIO_IDX_START_SE;
+			port = CHV_IOSF_PORT_GPIO_SE;
+		} else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
+			gpio_index -= CHV_GPIO_IDX_START_SW;
+			port = CHV_IOSF_PORT_GPIO_SW;
+		} else if (gpio_index >= CHV_GPIO_IDX_START_E) {
+			gpio_index -= CHV_GPIO_IDX_START_E;
+			port = CHV_IOSF_PORT_GPIO_E;
+		} else {
+			port = CHV_IOSF_PORT_GPIO_N;
+		}
+	} else {
+		/* XXX: The spec is unclear about CHV GPIO on seq v2 */
+		if (gpio_source != 0) {
+			DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
+			return;
+		}
+
+		if (gpio_index >= CHV_GPIO_IDX_START_E) {
+			DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",
+				      gpio_index);
+			return;
+		}
+
+		port = CHV_IOSF_PORT_GPIO_N;
+	}
+
+	family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
+	gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
+
+	cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
+	cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
+
+	mutex_lock(&dev_priv->sb_lock);
+	vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
+	vlv_iosf_sb_write(dev_priv, port, cfg0,
+			  CHV_GPIO_GPIOCFG_GPO | CHV_GPIO_GPIOTXSTATE(value));
+	mutex_unlock(&dev_priv->sb_lock);
+}
+
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
@@ -255,6 +323,8 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 
 	if (IS_VALLEYVIEW(dev_priv))
 		vlv_exec_gpio(dev_priv, gpio_source, gpio_index, value);
+	else if (IS_CHERRYVIEW(dev_priv))
+		chv_exec_gpio(dev_priv, gpio_source, gpio_index, value);
 	else
 		DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
 
-- 
2.1.4

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Re: [PATCH v5 2/3] drm/i915/dsi: add support for gpio elements on CHV

[Ville Syrjälä]

On Tue, Apr 26, 2016 at 01:27:40PM +0300, Jani Nikula wrote:
> Add support for CHV gpio programming in DSI gpio elements.
> 
> v2: Overhaul macros according to Ville's review.
> 
> v3: Address Ville's review:
>  - swap E and SE gpio ranges
>  - add a note about max SE index
>  - use GPO, not HIZ
>  - swap cfg0 and cfg1
> 
> v4: fix port for dsi sequence versions 1 and 2
> 
> [Rewritten by Jani, based on earlier work by Yogesh and Deepak.]
> 
> Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 70 ++++++++++++++++++++++++++++++
>  1 file changed, 70 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index a1cc8533cff5..f122484bedfc 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -95,6 +95,24 @@ static struct gpio_map vlv_gpio_table[] = {
>  	{ VLV_GPIO_NC_11_PANEL1_BKLTCTL },
>  };
>  
> +#define CHV_GPIO_IDX_START_N		0
> +#define CHV_GPIO_IDX_START_E		73
> +#define CHV_GPIO_IDX_START_SW		100
> +#define CHV_GPIO_IDX_START_SE		198
> +
> +#define CHV_VBT_MAX_PINS_PER_FMLY	15
> +
> +#define CHV_GPIO_PAD_CFG0(f, i)		(0x4400 + (f) * 0x400 + (i) * 8)
> +#define  CHV_GPIO_GPIOEN		(1 << 15)
> +#define  CHV_GPIO_GPIOCFG_GPIO		(0 << 8)
> +#define  CHV_GPIO_GPIOCFG_GPO		(1 << 8)
> +#define  CHV_GPIO_GPIOCFG_GPI		(2 << 8)
> +#define  CHV_GPIO_GPIOCFG_HIZ		(3 << 8)
> +#define  CHV_GPIO_GPIOTXSTATE(state)	((!!(state)) << 1)
> +
> +#define CHV_GPIO_PAD_CFG1(f, i)		(0x4400 + (f) * 0x400 + (i) * 8 + 4)
> +#define  CHV_GPIO_CFGLOCK		(1 << 31)
> +
>  static inline enum port intel_dsi_seq_port_to_port(u8 port)
>  {
>  	return port ? PORT_C : PORT_A;
> @@ -232,6 +250,56 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
>  
> +static void chv_exec_gpio(struct drm_i915_private *dev_priv,
> +			  u8 gpio_source, u8 gpio_index, bool value)
> +{
> +	u16 cfg0, cfg1;
> +	u16 family_num;
> +	u8 port;
> +
> +	if (dev_priv->vbt.dsi.seq_version >= 3) {
> +		if (gpio_index >= CHV_GPIO_IDX_START_SE) {
> +			/* XXX: it's unclear whether 255->57 is part of SE. */
> +			gpio_index -= CHV_GPIO_IDX_START_SE;
> +			port = CHV_IOSF_PORT_GPIO_SE;
> +		} else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
> +			gpio_index -= CHV_GPIO_IDX_START_SW;
> +			port = CHV_IOSF_PORT_GPIO_SW;
> +		} else if (gpio_index >= CHV_GPIO_IDX_START_E) {
> +			gpio_index -= CHV_GPIO_IDX_START_E;
> +			port = CHV_IOSF_PORT_GPIO_E;
> +		} else {
> +			port = CHV_IOSF_PORT_GPIO_N;
> +		}
> +	} else {
> +		/* XXX: The spec is unclear about CHV GPIO on seq v2 */
> +		if (gpio_source != 0) {
> +			DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
> +			return;
> +		}
> +
> +		if (gpio_index >= CHV_GPIO_IDX_START_E) {
> +			DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",
> +				      gpio_index);
> +			return;
> +		}
> +
> +		port = CHV_IOSF_PORT_GPIO_N;
> +	}
> +
> +	family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
> +	gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
> +
> +	cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
> +	cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +	vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
> +	vlv_iosf_sb_write(dev_priv, port, cfg0,
> +			  CHV_GPIO_GPIOCFG_GPO | CHV_GPIO_GPIOTXSTATE(value));
> +	mutex_unlock(&dev_priv->sb_lock);
> +}
> +
>  static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>  {
>  	struct drm_device *dev = intel_dsi->base.base.dev;
> @@ -255,6 +323,8 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>  
>  	if (IS_VALLEYVIEW(dev_priv))
>  		vlv_exec_gpio(dev_priv, gpio_source, gpio_index, value);
> +	else if (IS_CHERRYVIEW(dev_priv))
> +		chv_exec_gpio(dev_priv, gpio_source, gpio_index, value);
>  	else
>  		DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
>  
> -- 
> 2.1.4

-- 
Ville Syrjälä
Intel OTC
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[PATCH v5 3/3] drm/i915/bxt: add bxt dsi gpio element support

[Jani Nikula]

Request the GPIO by index through the consumer API. For now, use a quick
hack to store the already requested ones, simply because I have no idea
whether this actually works or not, and I have no way to test it.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 28 +++++++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f122484bedfc..aefcc19968e0 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -29,6 +29,7 @@
 #include <drm/drm_edid.h>
 #include <drm/i915_drm.h>
 #include <drm/drm_panel.h>
+#include <linux/gpio/consumer.h>
 #include <linux/slab.h>
 #include <video/mipi_display.h>
 #include <asm/intel-mid.h>
@@ -300,6 +301,31 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv,
 	mutex_unlock(&dev_priv->sb_lock);
 }
 
+static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
+			  u8 gpio_source, u8 gpio_index, bool value)
+{
+	/* XXX: this table is a quick ugly hack. */
+	static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
+	struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
+
+	if (!gpio_desc) {
+		gpio_desc = devm_gpiod_get_index(dev_priv->dev->dev,
+						 NULL, gpio_index,
+						 value ? GPIOD_OUT_LOW :
+						 GPIOD_OUT_HIGH);
+
+		if (IS_ERR_OR_NULL(gpio_desc)) {
+			DRM_ERROR("GPIO index %u request failed (%ld)\n",
+				  gpio_index, PTR_ERR(gpio_desc));
+			return;
+		}
+
+		bxt_gpio_table[gpio_index] = gpio_desc;
+	}
+
+	gpiod_set_value(gpio_desc, value);
+}
+
 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 {
 	struct drm_device *dev = intel_dsi->base.base.dev;
@@ -326,7 +352,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 	else if (IS_CHERRYVIEW(dev_priv))
 		chv_exec_gpio(dev_priv, gpio_source, gpio_index, value);
 	else
-		DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
+		bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
 
 	return data;
 }
-- 
2.1.4

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Re: [PATCH v5 3/3] drm/i915/bxt: add bxt dsi gpio element support

[Ville Syrjälä]

On Tue, Apr 26, 2016 at 01:27:41PM +0300, Jani Nikula wrote:
> Request the GPIO by index through the consumer API. For now, use a quick
> hack to store the already requested ones, simply because I have no idea
> whether this actually works or not, and I have no way to test it.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 28 +++++++++++++++++++++++++++-
>  1 file changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index f122484bedfc..aefcc19968e0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -29,6 +29,7 @@
>  #include <drm/drm_edid.h>
>  #include <drm/i915_drm.h>
>  #include <drm/drm_panel.h>
> +#include <linux/gpio/consumer.h>
>  #include <linux/slab.h>
>  #include <video/mipi_display.h>
>  #include <asm/intel-mid.h>
> @@ -300,6 +301,31 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv,
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
>  
> +static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
> +			  u8 gpio_source, u8 gpio_index, bool value)
> +{
> +	/* XXX: this table is a quick ugly hack. */
> +	static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
> +	struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
> +
> +	if (!gpio_desc) {
> +		gpio_desc = devm_gpiod_get_index(dev_priv->dev->dev,
> +						 NULL, gpio_index,

If I'm reading the spec right, I think we should be passing the byte 0
(GPIO Index) here, not byte 1 (GPIO number). I could be wrong though.

> +						 value ? GPIOD_OUT_LOW :
> +						 GPIOD_OUT_HIGH);
> +
> +		if (IS_ERR_OR_NULL(gpio_desc)) {
> +			DRM_ERROR("GPIO index %u request failed (%ld)\n",
> +				  gpio_index, PTR_ERR(gpio_desc));
> +			return;
> +		}
> +
> +		bxt_gpio_table[gpio_index] = gpio_desc;
> +	}
> +
> +	gpiod_set_value(gpio_desc, value);
> +}
> +
>  static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>  {
>  	struct drm_device *dev = intel_dsi->base.base.dev;
> @@ -326,7 +352,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>  	else if (IS_CHERRYVIEW(dev_priv))
>  		chv_exec_gpio(dev_priv, gpio_source, gpio_index, value);
>  	else
> -		DRM_DEBUG_KMS("GPIO element not supported on this platform\n");
> +		bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
>  
>  	return data;
>  }
> -- 
> 2.1.4

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v5 3/3] drm/i915/bxt: add bxt dsi gpio element support

[Mika Kahola]

Tested-by: Mika Kahola <mika.kahola@intel.com>

On Tue, 2016-04-26 at 13:27 +0300, Jani Nikula wrote:
> Request the GPIO by index through the consumer API. For now, use a
> quick
> hack to store the already requested ones, simply because I have no
> idea
> whether this actually works or not, and I have no way to test it.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 28
> +++++++++++++++++++++++++++-
>  1 file changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index f122484bedfc..aefcc19968e0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -29,6 +29,7 @@
>  #include <drm/drm_edid.h>
>  #include <drm/i915_drm.h>
>  #include <drm/drm_panel.h>
> +#include <linux/gpio/consumer.h>
>  #include <linux/slab.h>
>  #include <video/mipi_display.h>
>  #include <asm/intel-mid.h>
> @@ -300,6 +301,31 @@ static void chv_exec_gpio(struct
> drm_i915_private *dev_priv,
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
>  
> +static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
> +			  u8 gpio_source, u8 gpio_index, bool value)
> +{
> +	/* XXX: this table is a quick ugly hack. */
> +	static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
> +	struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
> +
> +	if (!gpio_desc) {
> +		gpio_desc = devm_gpiod_get_index(dev_priv->dev->dev,
> +						 NULL, gpio_index,
> +						 value ?
> GPIOD_OUT_LOW :
> +						 GPIOD_OUT_HIGH);
> +
> +		if (IS_ERR_OR_NULL(gpio_desc)) {
> +			DRM_ERROR("GPIO index %u request failed
> (%ld)\n",
> +				  gpio_index, PTR_ERR(gpio_desc));
> +			return;
> +		}
> +
> +		bxt_gpio_table[gpio_index] = gpio_desc;
> +	}
> +
> +	gpiod_set_value(gpio_desc, value);
> +}
> +
>  static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const
> u8 *data)
>  {
>  	struct drm_device *dev = intel_dsi->base.base.dev;
> @@ -326,7 +352,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi
> *intel_dsi, const u8 *data)
>  	else if (IS_CHERRYVIEW(dev_priv))
>  		chv_exec_gpio(dev_priv, gpio_source, gpio_index,
> value);
>  	else
> -		DRM_DEBUG_KMS("GPIO element not supported on this
> platform\n");
> +		bxt_exec_gpio(dev_priv, gpio_source, gpio_index,
> value);
>  
>  	return data;
>  }
-- 
Mika Kahola - Intel OTC

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✓ Fi.CI.BAT: success for drm/i915/dsi: improved gpio element support for vlv/chv/bxt (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: improved gpio element support for vlv/chv/bxt (rev5)
URL   : https://patchwork.freedesktop.org/series/4625/
State : success

== Summary ==

Series 4625v5 drm/i915/dsi: improved gpio element support for vlv/chv/bxt
http://patchwork.freedesktop.org/api/1.0/series/4625/revisions/5/mbox/

Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-b:
                incomplete -> PASS       (snb-dellxps)

bdw-nuci7        total:200  pass:188  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:200  pass:175  dwarn:0   dfail:0   fail:0   skip:25 
bsw-nuc-2        total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41 
byt-nuc          total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41 
hsw-brixbox      total:200  pass:174  dwarn:0   dfail:0   fail:0   skip:26 
hsw-gt2          total:200  pass:178  dwarn:0   dfail:0   fail:1   skip:21 
ilk-hp8440p      total:200  pass:139  dwarn:0   dfail:0   fail:0   skip:61 
ivb-t430s        total:200  pass:169  dwarn:0   dfail:0   fail:0   skip:31 
skl-i7k-2        total:200  pass:173  dwarn:0   dfail:0   fail:0   skip:27 
skl-nuci5        total:200  pass:189  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:200  pass:158  dwarn:0   dfail:0   fail:0   skip:42 
snb-x220t        total:200  pass:158  dwarn:0   dfail:0   fail:1   skip:41 

Results at /archive/results/CI_IGT_test/Patchwork_2072/

e005db1cb2c60d18abe837ac683d8993ea77b239 drm-intel-nightly: 2016y-04m-26d-12h-51m-57s UTC integration manifest
3f43aa7 drm/i915/bxt: add bxt dsi gpio element support
289a885 drm/i915/dsi: add support for gpio elements on CHV
85f278c drm/i915/dsi: add support for sequence block v3 gpio for VLV

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