[PATCH 0/3] drm/i915: DP branch devices

[PATCH 0/3] drm/i915: DP branch devices

[Mika Kahola]

This series of patches reads either pixel rate or 
TMDS clock rate from DPCD. Pixel rate is defined
for DP to VGA dongles and TMDS clock rate for others
except wireless dongle. The mode that requires either
higher pixel rate or TMDS clock rate are filtered out
during the mode validity check.

Mika Kahola (3):
  drm/i915: Check pixel rate for DP to VGA dongle
  drm: Add DP port types from DP 1.3 specification
  drm/i915: Check HDMI TMDS clock rate from DPCD

 drivers/gpu/drm/i915/intel_dp.c   | 37 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h  | 10 ++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c |  7 ++++---
 include/drm/drm_dp_helper.h       |  2 ++
 4 files changed, 53 insertions(+), 3 deletions(-)

-- 
1.9.1

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[PATCH 1/3] drm/i915: Check pixel rate for DP to VGA dongle

[Mika Kahola]

Prep work to improve DP branch device handling.

Filter out a mode that exceeds the max pixel rate setting
for DP to VGA dongle. This is defined in DPCD register 0x81
if detailed cap info i.e. info field is 4 bytes long and
it is available for DP downstream port.

The register defines the pixel rate divided by 8 in MP/s.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 34 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |  9 +++++++++
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3633002..74a04ce 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -201,6 +201,13 @@ intel_dp_mode_valid(struct drm_connector *connector,
 	int max_rate, mode_rate, max_lanes, max_link_clock;
 	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 
+	/* DP to VGA dongle may define max pixel rate in DPCD */
+	if (intel_dp->dfp.present &&
+	    intel_dp->dfp.detailed_cap_info &&
+	    (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) &&
+	    (intel_dp->dfp.dot_clk > 0))
+		max_dotclk = min(max_dotclk, intel_dp->dfp.dot_clk);
+
 	if (is_edp(intel_dp) && fixed_mode) {
 		if (mode->hdisplay > fixed_mode->hdisplay)
 			return MODE_PANEL;
@@ -4566,6 +4573,28 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = {
 	.destroy = intel_dp_encoder_destroy,
 };
 
+static void intel_dp_get_dfp(struct intel_dp *intel_dp)
+{
+	uint8_t dfp_info[4];
+
+	intel_dp->dfp.detailed_cap_info = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE;
+
+	if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, dfp_info, 4) < 0) {
+		intel_dp->dfp.present = false;
+		intel_dp->dfp.detailed_cap_info = false;
+		return; /* aux transfer failed */
+	}
+
+	intel_dp->dfp.type = dfp_info[0] & DP_DS_PORT_TYPE_MASK;
+
+	if (intel_dp->dfp.detailed_cap_info) {
+		if (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) {
+			intel_dp->dfp.dot_clk = dfp_info[1] * 8 * 1000;
+			DRM_DEBUG_KMS("max pixel rate for VGA is %d kHz\n", intel_dp->dfp.dot_clk);
+		}
+	}
+}
+
 enum irqreturn
 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 {
@@ -4599,6 +4628,11 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 	power_domain = intel_display_port_aux_power_domain(intel_encoder);
 	intel_display_power_get(dev_priv, power_domain);
 
+	intel_dp->dfp.present = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 0x1;
+
+	if (intel_dp->dfp.present)
+		intel_dp_get_dfp(intel_dp);
+
 	if (long_hpd) {
 		/* indicate that we need to restart link training */
 		intel_dp->train_set_valid = false;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 21dee3f..9798a59 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -794,6 +794,13 @@ enum link_m_n_set {
 	M2_N2
 };
 
+struct intel_dp_dfp {
+	bool present;
+	int type;
+	bool detailed_cap_info;
+	int dot_clk; /* pixel rate for VGA dongles */
+};
+
 struct intel_dp {
 	i915_reg_t output_reg;
 	i915_reg_t aux_ch_ctl_reg;
@@ -861,6 +868,8 @@ struct intel_dp {
 
 	bool train_set_valid;
 
+	struct intel_dp_dfp dfp;
+
 	/* Displayport compliance testing */
 	unsigned long compliance_test_type;
 	unsigned long compliance_test_data;
-- 
1.9.1

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Re: [PATCH 1/3] drm/i915: Check pixel rate for DP to VGA dongle

[Ville Syrjälä]

On Tue, May 03, 2016 at 02:46:36PM +0300, Mika Kahola wrote:
> Prep work to improve DP branch device handling.
> 
> Filter out a mode that exceeds the max pixel rate setting
> for DP to VGA dongle. This is defined in DPCD register 0x81
> if detailed cap info i.e. info field is 4 bytes long and
> it is available for DP downstream port.
> 
> The register defines the pixel rate divided by 8 in MP/s.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c  | 34 ++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h |  9 +++++++++
>  2 files changed, 43 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3633002..74a04ce 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -201,6 +201,13 @@ intel_dp_mode_valid(struct drm_connector *connector,
>  	int max_rate, mode_rate, max_lanes, max_link_clock;
>  	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
>  
> +	/* DP to VGA dongle may define max pixel rate in DPCD */
> +	if (intel_dp->dfp.present &&
> +	    intel_dp->dfp.detailed_cap_info &&
> +	    (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) &&
> +	    (intel_dp->dfp.dot_clk > 0))
> +		max_dotclk = min(max_dotclk, intel_dp->dfp.dot_clk);

What's dfp?

Looks like most of this stuff is not really needed. Just storing a max
dotclock per downstream port would seem to suffice.

> +
>  	if (is_edp(intel_dp) && fixed_mode) {
>  		if (mode->hdisplay > fixed_mode->hdisplay)
>  			return MODE_PANEL;
> @@ -4566,6 +4573,28 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = {
>  	.destroy = intel_dp_encoder_destroy,
>  };
>  
> +static void intel_dp_get_dfp(struct intel_dp *intel_dp)
> +{
> +	uint8_t dfp_info[4];
> +
> +	intel_dp->dfp.detailed_cap_info = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE;
> +
> +	if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, dfp_info, 4) < 0) {
> +		intel_dp->dfp.present = false;
> +		intel_dp->dfp.detailed_cap_info = false;
> +		return; /* aux transfer failed */
> +	}
> +
> +	intel_dp->dfp.type = dfp_info[0] & DP_DS_PORT_TYPE_MASK;
> +
> +	if (intel_dp->dfp.detailed_cap_info) {
> +		if (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) {
> +			intel_dp->dfp.dot_clk = dfp_info[1] * 8 * 1000;
> +			DRM_DEBUG_KMS("max pixel rate for VGA is %d kHz\n", intel_dp->dfp.dot_clk);
> +		}

I would suggest putting this sort of stuff into the dp helper. I once
started to hatch something to deal with these downstream port limits,
but never finished it. I pushed my WIP stuff (mostly ideas how to parse
these port caps) to 

git://github.com/vsyrjala/linux.git dp_downstream_ports

maybe you can to see if there's anything useful for you there.

> +	}
> +}
> +
>  enum irqreturn
>  intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
>  {
> @@ -4599,6 +4628,11 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
>  	power_domain = intel_display_port_aux_power_domain(intel_encoder);
>  	intel_display_power_get(dev_priv, power_domain);
>  
> +	intel_dp->dfp.present = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 0x1;
> +
> +	if (intel_dp->dfp.present)
> +		intel_dp_get_dfp(intel_dp);
> +
>  	if (long_hpd) {
>  		/* indicate that we need to restart link training */
>  		intel_dp->train_set_valid = false;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 21dee3f..9798a59 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -794,6 +794,13 @@ enum link_m_n_set {
>  	M2_N2
>  };
>  
> +struct intel_dp_dfp {
> +	bool present;
> +	int type;
> +	bool detailed_cap_info;
> +	int dot_clk; /* pixel rate for VGA dongles */
> +};
> +
>  struct intel_dp {
>  	i915_reg_t output_reg;
>  	i915_reg_t aux_ch_ctl_reg;
> @@ -861,6 +868,8 @@ struct intel_dp {
>  
>  	bool train_set_valid;
>  
> +	struct intel_dp_dfp dfp;
> +
>  	/* Displayport compliance testing */
>  	unsigned long compliance_test_type;
>  	unsigned long compliance_test_data;
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Check pixel rate for DP to VGA dongle

[Daniel Vetter]

On Tue, May 03, 2016 at 04:23:34PM +0300, Ville Syrjälä wrote:
> On Tue, May 03, 2016 at 02:46:36PM +0300, Mika Kahola wrote:
> > Prep work to improve DP branch device handling.
> > 
> > Filter out a mode that exceeds the max pixel rate setting
> > for DP to VGA dongle. This is defined in DPCD register 0x81
> > if detailed cap info i.e. info field is 4 bytes long and
> > it is available for DP downstream port.
> > 
> > The register defines the pixel rate divided by 8 in MP/s.
> > 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c  | 34 ++++++++++++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_drv.h |  9 +++++++++
> >  2 files changed, 43 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 3633002..74a04ce 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -201,6 +201,13 @@ intel_dp_mode_valid(struct drm_connector *connector,
> >  	int max_rate, mode_rate, max_lanes, max_link_clock;
> >  	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
> >  
> > +	/* DP to VGA dongle may define max pixel rate in DPCD */
> > +	if (intel_dp->dfp.present &&
> > +	    intel_dp->dfp.detailed_cap_info &&
> > +	    (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) &&
> > +	    (intel_dp->dfp.dot_clk > 0))
> > +		max_dotclk = min(max_dotclk, intel_dp->dfp.dot_clk);
> 
> What's dfp?
> 
> Looks like most of this stuff is not really needed. Just storing a max
> dotclock per downstream port would seem to suffice.
> 
> > +
> >  	if (is_edp(intel_dp) && fixed_mode) {
> >  		if (mode->hdisplay > fixed_mode->hdisplay)
> >  			return MODE_PANEL;
> > @@ -4566,6 +4573,28 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = {
> >  	.destroy = intel_dp_encoder_destroy,
> >  };
> >  
> > +static void intel_dp_get_dfp(struct intel_dp *intel_dp)
> > +{
> > +	uint8_t dfp_info[4];
> > +
> > +	intel_dp->dfp.detailed_cap_info = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE;
> > +
> > +	if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, dfp_info, 4) < 0) {
> > +		intel_dp->dfp.present = false;
> > +		intel_dp->dfp.detailed_cap_info = false;
> > +		return; /* aux transfer failed */
> > +	}
> > +
> > +	intel_dp->dfp.type = dfp_info[0] & DP_DS_PORT_TYPE_MASK;
> > +
> > +	if (intel_dp->dfp.detailed_cap_info) {
> > +		if (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) {
> > +			intel_dp->dfp.dot_clk = dfp_info[1] * 8 * 1000;
> > +			DRM_DEBUG_KMS("max pixel rate for VGA is %d kHz\n", intel_dp->dfp.dot_clk);
> > +		}
> 
> I would suggest putting this sort of stuff into the dp helper. I once
> started to hatch something to deal with these downstream port limits,
> but never finished it. I pushed my WIP stuff (mostly ideas how to parse
> these port caps) to 
> 
> git://github.com/vsyrjala/linux.git dp_downstream_ports
> 
> maybe you can to see if there's anything useful for you there.

Seconded on at least moving the computation into the dp helpers. i915.ko
really should only ask the helpers for the final result, maybe with an
intermediate step to cache the dp aux register stuff. There's already some
structures in the dp helpers to store sink state, we could start using
those (unfortunately they're not agreeing on what the canonical one should
be).
-Daniel

> 
> > +	}
> > +}
> > +
> >  enum irqreturn
> >  intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
> >  {
> > @@ -4599,6 +4628,11 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
> >  	power_domain = intel_display_port_aux_power_domain(intel_encoder);
> >  	intel_display_power_get(dev_priv, power_domain);
> >  
> > +	intel_dp->dfp.present = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 0x1;
> > +
> > +	if (intel_dp->dfp.present)
> > +		intel_dp_get_dfp(intel_dp);
> > +
> >  	if (long_hpd) {
> >  		/* indicate that we need to restart link training */
> >  		intel_dp->train_set_valid = false;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 21dee3f..9798a59 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -794,6 +794,13 @@ enum link_m_n_set {
> >  	M2_N2
> >  };
> >  
> > +struct intel_dp_dfp {
> > +	bool present;
> > +	int type;
> > +	bool detailed_cap_info;
> > +	int dot_clk; /* pixel rate for VGA dongles */
> > +};
> > +
> >  struct intel_dp {
> >  	i915_reg_t output_reg;
> >  	i915_reg_t aux_ch_ctl_reg;
> > @@ -861,6 +868,8 @@ struct intel_dp {
> >  
> >  	bool train_set_valid;
> >  
> > +	struct intel_dp_dfp dfp;
> > +
> >  	/* Displayport compliance testing */
> >  	unsigned long compliance_test_type;
> >  	unsigned long compliance_test_data;
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 1/3] drm/i915: Check pixel rate for DP to VGA dongle

[Ville Syrjälä]

On Tue, May 03, 2016 at 04:28:00PM +0200, Daniel Vetter wrote:
> On Tue, May 03, 2016 at 04:23:34PM +0300, Ville Syrjälä wrote:
> > On Tue, May 03, 2016 at 02:46:36PM +0300, Mika Kahola wrote:
> > > Prep work to improve DP branch device handling.
> > > 
> > > Filter out a mode that exceeds the max pixel rate setting
> > > for DP to VGA dongle. This is defined in DPCD register 0x81
> > > if detailed cap info i.e. info field is 4 bytes long and
> > > it is available for DP downstream port.
> > > 
> > > The register defines the pixel rate divided by 8 in MP/s.
> > > 
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c  | 34 ++++++++++++++++++++++++++++++++++
> > >  drivers/gpu/drm/i915/intel_drv.h |  9 +++++++++
> > >  2 files changed, 43 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index 3633002..74a04ce 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -201,6 +201,13 @@ intel_dp_mode_valid(struct drm_connector *connector,
> > >  	int max_rate, mode_rate, max_lanes, max_link_clock;
> > >  	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
> > >  
> > > +	/* DP to VGA dongle may define max pixel rate in DPCD */
> > > +	if (intel_dp->dfp.present &&
> > > +	    intel_dp->dfp.detailed_cap_info &&
> > > +	    (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) &&
> > > +	    (intel_dp->dfp.dot_clk > 0))
> > > +		max_dotclk = min(max_dotclk, intel_dp->dfp.dot_clk);
> > 
> > What's dfp?
> > 
> > Looks like most of this stuff is not really needed. Just storing a max
> > dotclock per downstream port would seem to suffice.
> > 
> > > +
> > >  	if (is_edp(intel_dp) && fixed_mode) {
> > >  		if (mode->hdisplay > fixed_mode->hdisplay)
> > >  			return MODE_PANEL;
> > > @@ -4566,6 +4573,28 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = {
> > >  	.destroy = intel_dp_encoder_destroy,
> > >  };
> > >  
> > > +static void intel_dp_get_dfp(struct intel_dp *intel_dp)
> > > +{
> > > +	uint8_t dfp_info[4];
> > > +
> > > +	intel_dp->dfp.detailed_cap_info = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE;
> > > +
> > > +	if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, dfp_info, 4) < 0) {
> > > +		intel_dp->dfp.present = false;
> > > +		intel_dp->dfp.detailed_cap_info = false;
> > > +		return; /* aux transfer failed */
> > > +	}
> > > +
> > > +	intel_dp->dfp.type = dfp_info[0] & DP_DS_PORT_TYPE_MASK;
> > > +
> > > +	if (intel_dp->dfp.detailed_cap_info) {
> > > +		if (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) {
> > > +			intel_dp->dfp.dot_clk = dfp_info[1] * 8 * 1000;
> > > +			DRM_DEBUG_KMS("max pixel rate for VGA is %d kHz\n", intel_dp->dfp.dot_clk);
> > > +		}
> > 
> > I would suggest putting this sort of stuff into the dp helper. I once
> > started to hatch something to deal with these downstream port limits,
> > but never finished it. I pushed my WIP stuff (mostly ideas how to parse
> > these port caps) to 
> > 
> > git://github.com/vsyrjala/linux.git dp_downstream_ports
> > 
> > maybe you can to see if there's anything useful for you there.
> 
> Seconded on at least moving the computation into the dp helpers. i915.ko
> really should only ask the helpers for the final result, maybe with an
> intermediate step to cache the dp aux register stuff. There's already some
> structures in the dp helpers to store sink state, we could start using
> those (unfortunately they're not agreeing on what the canonical one should
> be).

Yeah that thing is a bit of mess right now. As usual, I have a branch to
clean some of it up a bit. Mainly aiming to respect the sink HDMI TMDS
clock limits better. But I need to get the DP++ stuff landed before
I continue with that.

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 1/3] drm/i915: Check pixel rate for DP to VGA dongle

[Mika Kahola]

On Tue, 2016-05-03 at 16:28 +0200, Daniel Vetter wrote:
> On Tue, May 03, 2016 at 04:23:34PM +0300, Ville Syrjälä wrote:
> > On Tue, May 03, 2016 at 02:46:36PM +0300, Mika Kahola wrote:
> > > Prep work to improve DP branch device handling.
> > > 
> > > Filter out a mode that exceeds the max pixel rate setting
> > > for DP to VGA dongle. This is defined in DPCD register 0x81
> > > if detailed cap info i.e. info field is 4 bytes long and
> > > it is available for DP downstream port.
> > > 
> > > The register defines the pixel rate divided by 8 in MP/s.
> > > 
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c  | 34 ++++++++++++++++++++++++++++++++++
> > >  drivers/gpu/drm/i915/intel_drv.h |  9 +++++++++
> > >  2 files changed, 43 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index 3633002..74a04ce 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -201,6 +201,13 @@ intel_dp_mode_valid(struct drm_connector *connector,
> > >  	int max_rate, mode_rate, max_lanes, max_link_clock;
> > >  	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
> > >  
> > > +	/* DP to VGA dongle may define max pixel rate in DPCD */
> > > +	if (intel_dp->dfp.present &&
> > > +	    intel_dp->dfp.detailed_cap_info &&
> > > +	    (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) &&
> > > +	    (intel_dp->dfp.dot_clk > 0))
> > > +		max_dotclk = min(max_dotclk, intel_dp->dfp.dot_clk);
> > 
> > What's dfp?

dfp - Downstream-Facing Port
> > 
> > Looks like most of this stuff is not really needed. Just storing a max
> > dotclock per downstream port would seem to suffice.
> > 
> > > +
> > >  	if (is_edp(intel_dp) && fixed_mode) {
> > >  		if (mode->hdisplay > fixed_mode->hdisplay)
> > >  			return MODE_PANEL;
> > > @@ -4566,6 +4573,28 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = {
> > >  	.destroy = intel_dp_encoder_destroy,
> > >  };
> > >  
> > > +static void intel_dp_get_dfp(struct intel_dp *intel_dp)
> > > +{
> > > +	uint8_t dfp_info[4];
> > > +
> > > +	intel_dp->dfp.detailed_cap_info = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE;
> > > +
> > > +	if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, dfp_info, 4) < 0) {
> > > +		intel_dp->dfp.present = false;
> > > +		intel_dp->dfp.detailed_cap_info = false;
> > > +		return; /* aux transfer failed */
> > > +	}
> > > +
> > > +	intel_dp->dfp.type = dfp_info[0] & DP_DS_PORT_TYPE_MASK;
> > > +
> > > +	if (intel_dp->dfp.detailed_cap_info) {
> > > +		if (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) {
> > > +			intel_dp->dfp.dot_clk = dfp_info[1] * 8 * 1000;
> > > +			DRM_DEBUG_KMS("max pixel rate for VGA is %d kHz\n", intel_dp->dfp.dot_clk);
> > > +		}
> > 
> > I would suggest putting this sort of stuff into the dp helper. I once
> > started to hatch something to deal with these downstream port limits,
> > but never finished it. I pushed my WIP stuff (mostly ideas how to parse
> > these port caps) to 
> > 
> > git://github.com/vsyrjala/linux.git dp_downstream_ports
> > 
> > maybe you can to see if there's anything useful for you there.
> 
> Seconded on at least moving the computation into the dp helpers. i915.ko
> really should only ask the helpers for the final result, maybe with an
> intermediate step to cache the dp aux register stuff. There's already some
> structures in the dp helpers to store sink state, we could start using
> those (unfortunately they're not agreeing on what the canonical one should
> be).
> -Daniel

Ok. Two votes for moving this stuff into the dp helpers. I'll do a
respin with this one. 

Cheers,
Mika

> 
> > 
> > > +	}
> > > +}
> > > +
> > >  enum irqreturn
> > >  intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
> > >  {
> > > @@ -4599,6 +4628,11 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
> > >  	power_domain = intel_display_port_aux_power_domain(intel_encoder);
> > >  	intel_display_power_get(dev_priv, power_domain);
> > >  
> > > +	intel_dp->dfp.present = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 0x1;
> > > +
> > > +	if (intel_dp->dfp.present)
> > > +		intel_dp_get_dfp(intel_dp);
> > > +
> > >  	if (long_hpd) {
> > >  		/* indicate that we need to restart link training */
> > >  		intel_dp->train_set_valid = false;
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > > index 21dee3f..9798a59 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -794,6 +794,13 @@ enum link_m_n_set {
> > >  	M2_N2
> > >  };
> > >  
> > > +struct intel_dp_dfp {
> > > +	bool present;
> > > +	int type;
> > > +	bool detailed_cap_info;
> > > +	int dot_clk; /* pixel rate for VGA dongles */
> > > +};
> > > +
> > >  struct intel_dp {
> > >  	i915_reg_t output_reg;
> > >  	i915_reg_t aux_ch_ctl_reg;
> > > @@ -861,6 +868,8 @@ struct intel_dp {
> > >  
> > >  	bool train_set_valid;
> > >  
> > > +	struct intel_dp_dfp dfp;
> > > +
> > >  	/* Displayport compliance testing */
> > >  	unsigned long compliance_test_type;
> > >  	unsigned long compliance_test_data;
> > > -- 
> > > 1.9.1
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel OTC
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

-- 
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Re: [PATCH 1/3] drm/i915: Check pixel rate for DP to VGA dongle

[Ville Syrjälä]

On Tue, May 10, 2016 at 12:44:22PM +0300, Mika Kahola wrote:
> On Tue, 2016-05-03 at 16:28 +0200, Daniel Vetter wrote:
> > On Tue, May 03, 2016 at 04:23:34PM +0300, Ville Syrjälä wrote:
> > > On Tue, May 03, 2016 at 02:46:36PM +0300, Mika Kahola wrote:
> > > > Prep work to improve DP branch device handling.
> > > > 
> > > > Filter out a mode that exceeds the max pixel rate setting
> > > > for DP to VGA dongle. This is defined in DPCD register 0x81
> > > > if detailed cap info i.e. info field is 4 bytes long and
> > > > it is available for DP downstream port.
> > > > 
> > > > The register defines the pixel rate divided by 8 in MP/s.
> > > > 
> > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_dp.c  | 34 ++++++++++++++++++++++++++++++++++
> > > >  drivers/gpu/drm/i915/intel_drv.h |  9 +++++++++
> > > >  2 files changed, 43 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > > index 3633002..74a04ce 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -201,6 +201,13 @@ intel_dp_mode_valid(struct drm_connector *connector,
> > > >  	int max_rate, mode_rate, max_lanes, max_link_clock;
> > > >  	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
> > > >  
> > > > +	/* DP to VGA dongle may define max pixel rate in DPCD */
> > > > +	if (intel_dp->dfp.present &&
> > > > +	    intel_dp->dfp.detailed_cap_info &&
> > > > +	    (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) &&
> > > > +	    (intel_dp->dfp.dot_clk > 0))
> > > > +		max_dotclk = min(max_dotclk, intel_dp->dfp.dot_clk);
> > > 
> > > What's dfp?
> 
> dfp - Downstream-Facing Port

I thought "digital flat panel" (as in the DFP standard and whatnot),
which was a bit confusing. So a bit of an overloaded TLA that one.
If we need such a substruct I might just call it downstream_port
or something along those lines.

> > > 
> > > Looks like most of this stuff is not really needed. Just storing a max
> > > dotclock per downstream port would seem to suffice.
> > > 
> > > > +
> > > >  	if (is_edp(intel_dp) && fixed_mode) {
> > > >  		if (mode->hdisplay > fixed_mode->hdisplay)
> > > >  			return MODE_PANEL;
> > > > @@ -4566,6 +4573,28 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = {
> > > >  	.destroy = intel_dp_encoder_destroy,
> > > >  };
> > > >  
> > > > +static void intel_dp_get_dfp(struct intel_dp *intel_dp)
> > > > +{
> > > > +	uint8_t dfp_info[4];
> > > > +
> > > > +	intel_dp->dfp.detailed_cap_info = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE;
> > > > +
> > > > +	if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, dfp_info, 4) < 0) {
> > > > +		intel_dp->dfp.present = false;
> > > > +		intel_dp->dfp.detailed_cap_info = false;
> > > > +		return; /* aux transfer failed */
> > > > +	}
> > > > +
> > > > +	intel_dp->dfp.type = dfp_info[0] & DP_DS_PORT_TYPE_MASK;
> > > > +
> > > > +	if (intel_dp->dfp.detailed_cap_info) {
> > > > +		if (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) {
> > > > +			intel_dp->dfp.dot_clk = dfp_info[1] * 8 * 1000;
> > > > +			DRM_DEBUG_KMS("max pixel rate for VGA is %d kHz\n", intel_dp->dfp.dot_clk);
> > > > +		}
> > > 
> > > I would suggest putting this sort of stuff into the dp helper. I once
> > > started to hatch something to deal with these downstream port limits,
> > > but never finished it. I pushed my WIP stuff (mostly ideas how to parse
> > > these port caps) to 
> > > 
> > > git://github.com/vsyrjala/linux.git dp_downstream_ports
> > > 
> > > maybe you can to see if there's anything useful for you there.
> > 
> > Seconded on at least moving the computation into the dp helpers. i915.ko
> > really should only ask the helpers for the final result, maybe with an
> > intermediate step to cache the dp aux register stuff. There's already some
> > structures in the dp helpers to store sink state, we could start using
> > those (unfortunately they're not agreeing on what the canonical one should
> > be).
> > -Daniel
> 
> Ok. Two votes for moving this stuff into the dp helpers. I'll do a
> respin with this one. 
> 
> Cheers,
> Mika
> 
> > 
> > > 
> > > > +	}
> > > > +}
> > > > +
> > > >  enum irqreturn
> > > >  intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
> > > >  {
> > > > @@ -4599,6 +4628,11 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
> > > >  	power_domain = intel_display_port_aux_power_domain(intel_encoder);
> > > >  	intel_display_power_get(dev_priv, power_domain);
> > > >  
> > > > +	intel_dp->dfp.present = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 0x1;
> > > > +
> > > > +	if (intel_dp->dfp.present)
> > > > +		intel_dp_get_dfp(intel_dp);
> > > > +
> > > >  	if (long_hpd) {
> > > >  		/* indicate that we need to restart link training */
> > > >  		intel_dp->train_set_valid = false;
> > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > > > index 21dee3f..9798a59 100644
> > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > @@ -794,6 +794,13 @@ enum link_m_n_set {
> > > >  	M2_N2
> > > >  };
> > > >  
> > > > +struct intel_dp_dfp {
> > > > +	bool present;
> > > > +	int type;
> > > > +	bool detailed_cap_info;
> > > > +	int dot_clk; /* pixel rate for VGA dongles */
> > > > +};
> > > > +
> > > >  struct intel_dp {
> > > >  	i915_reg_t output_reg;
> > > >  	i915_reg_t aux_ch_ctl_reg;
> > > > @@ -861,6 +868,8 @@ struct intel_dp {
> > > >  
> > > >  	bool train_set_valid;
> > > >  
> > > > +	struct intel_dp_dfp dfp;
> > > > +
> > > >  	/* Displayport compliance testing */
> > > >  	unsigned long compliance_test_type;
> > > >  	unsigned long compliance_test_data;
> > > > -- 
> > > > 1.9.1
> > > > 
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > 
> > > -- 
> > > Ville Syrjälä
> > > Intel OTC
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> 
> -- 
> Mika Kahola - Intel OTC

-- 
Ville Syrjälä
Intel OTC
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[PATCH 2/3] drm: Add DP port types from DP 1.3 specification

[Mika Kahola]

DP specification 1.3 defines DP downstream ports for
DP++ and wireless devices. Let's add these to port
definitions.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 include/drm/drm_dp_helper.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 92d9a52..9a15099 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -210,6 +210,8 @@
 # define DP_DS_PORT_TYPE_DVI		    2
 # define DP_DS_PORT_TYPE_HDMI		    3
 # define DP_DS_PORT_TYPE_NON_EDID	    4
+# define DP_DP_PORT_TYPE_DP_DUALMODE        5
+# define DP_DS_PORT_TYPE_WIRELESS           6
 # define DP_DS_PORT_HPD			    (1 << 3)
 /* offset 1 for VGA is maximum megapixels per second / 8 */
 /* offset 2 */
-- 
1.9.1

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Re: [PATCH 2/3] drm: Add DP port types from DP 1.3 specification

[Ilia Mirkin]

[-- Attachment #1.1: Type: text/plain, Size: 1135 bytes --]

On May 3, 2016 9:49 AM, "Mika Kahola" <mika.kahola@intel.com> wrote:
>
> DP specification 1.3 defines DP downstream ports for
> DP++ and wireless devices. Let's add these to port
> definitions.
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  include/drm/drm_dp_helper.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 92d9a52..9a15099 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -210,6 +210,8 @@
>  # define DP_DS_PORT_TYPE_DVI               2
>  # define DP_DS_PORT_TYPE_HDMI              3
>  # define DP_DS_PORT_TYPE_NON_EDID          4
> +# define DP_DP_PORT_TYPE_DP_DUALMODE        5

DP_DS right? (Like all the others)

> +# define DP_DS_PORT_TYPE_WIRELESS           6
>  # define DP_DS_PORT_HPD                            (1 << 3)
>  /* offset 1 for VGA is maximum megapixels per second / 8 */
>  /* offset 2 */
> --
> 1.9.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

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Re: [PATCH 2/3] drm: Add DP port types from DP 1.3 specification

[Mika Kahola]

On Tue, 2016-05-03 at 10:35 -0400, Ilia Mirkin wrote:
> 
> On May 3, 2016 9:49 AM, "Mika Kahola" <mika.kahola@intel.com> wrote:
> >
> > DP specification 1.3 defines DP downstream ports for
> > DP++ and wireless devices. Let's add these to port
> > definitions.
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  include/drm/drm_dp_helper.h | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h
> b/include/drm/drm_dp_helper.h
> > index 92d9a52..9a15099 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -210,6 +210,8 @@
> >  # define DP_DS_PORT_TYPE_DVI               2
> >  # define DP_DS_PORT_TYPE_HDMI              3
> >  # define DP_DS_PORT_TYPE_NON_EDID          4
> > +# define DP_DP_PORT_TYPE_DP_DUALMODE        5
> 
> DP_DS right? (Like all the others)
Indeed, that's a typo. I'll throw another round to fix this. Good catch!

Cheers,
Mika
> 
> > +# define DP_DS_PORT_TYPE_WIRELESS           6
> >  # define DP_DS_PORT_HPD                            (1 << 3)
> >  /* offset 1 for VGA is maximum megapixels per second / 8 */
> >  /* offset 2 */
> > --
> > 1.9.1
> >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
> 
> 

-- 
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[PATCH 3/3] drm/i915: Check HDMI TMDS clock rate from DPCD

[Mika Kahola]

Read TMDS clock rate from DPCD for HDMI to filter out
modes that might require higher TMDS clock rate than
supported.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   | 3 +++
 drivers/gpu/drm/i915/intel_drv.h  | 1 +
 drivers/gpu/drm/i915/intel_hdmi.c | 7 ++++---
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 74a04ce..0fd078c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4591,6 +4591,9 @@ static void intel_dp_get_dfp(struct intel_dp *intel_dp)
 		if (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) {
 			intel_dp->dfp.dot_clk = dfp_info[1] * 8 * 1000;
 			DRM_DEBUG_KMS("max pixel rate for VGA is %d kHz\n", intel_dp->dfp.dot_clk);
+		} else if (!(intel_dp->dfp.type & DP_DS_PORT_TYPE_WIRELESS)) {
+			intel_dp->dfp.tmds_clk = DIV_ROUND_CLOSEST(dfp_info[1] * 25 * 1000, 10);
+			DRM_DEBUG_KMS("max TMDS clock is %d kHz\n", intel_dp->dfp.tmds_clk);
 		}
 	}
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9798a59..8bf97da 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -799,6 +799,7 @@ struct intel_dp_dfp {
 	int type;
 	bool detailed_cap_info;
 	int dot_clk; /* pixel rate for VGA dongles */
+	int tmds_clk;
 };
 
 struct intel_dp {
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index e1012d6..70e8e17 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1170,13 +1170,14 @@ static void pch_post_disable_hdmi(struct intel_encoder *encoder)
 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
 {
 	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
+	int tmds_clock = hdmi_to_dig_port(hdmi)->dp.dfp.tmds_clk;
 
 	if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
-		return 165000;
+		return (tmds_clock > 0 ? min(165000, tmds_clock) : 165000);
 	else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
-		return 300000;
+		return (tmds_clock > 0 ? min(300000, tmds_clock) : 300000);
 	else
-		return 225000;
+		return (tmds_clock > 0 ? min(225000, tmds_clock) : 225000);
 }
 
 static enum drm_mode_status
-- 
1.9.1

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Re: [PATCH 3/3] drm/i915: Check HDMI TMDS clock rate from DPCD

[Ville Syrjälä]

On Tue, May 03, 2016 at 02:46:38PM +0300, Mika Kahola wrote:
> Read TMDS clock rate from DPCD for HDMI to filter out
> modes that might require higher TMDS clock rate than
> supported.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c   | 3 +++
>  drivers/gpu/drm/i915/intel_drv.h  | 1 +
>  drivers/gpu/drm/i915/intel_hdmi.c | 7 ++++---
>  3 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 74a04ce..0fd078c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4591,6 +4591,9 @@ static void intel_dp_get_dfp(struct intel_dp *intel_dp)
>  		if (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) {
>  			intel_dp->dfp.dot_clk = dfp_info[1] * 8 * 1000;
>  			DRM_DEBUG_KMS("max pixel rate for VGA is %d kHz\n", intel_dp->dfp.dot_clk);
> +		} else if (!(intel_dp->dfp.type & DP_DS_PORT_TYPE_WIRELESS)) {
> +			intel_dp->dfp.tmds_clk = DIV_ROUND_CLOSEST(dfp_info[1] * 25 * 1000, 10);
> +			DRM_DEBUG_KMS("max TMDS clock is %d kHz\n", intel_dp->dfp.tmds_clk);
>  		}
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 9798a59..8bf97da 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -799,6 +799,7 @@ struct intel_dp_dfp {
>  	int type;
>  	bool detailed_cap_info;
>  	int dot_clk; /* pixel rate for VGA dongles */
> +	int tmds_clk;
>  };
>  
>  struct intel_dp {
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index e1012d6..70e8e17 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1170,13 +1170,14 @@ static void pch_post_disable_hdmi(struct intel_encoder *encoder)
>  static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
>  {
>  	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
> +	int tmds_clock = hdmi_to_dig_port(hdmi)->dp.dfp.tmds_clk;
>  
>  	if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
> -		return 165000;
> +		return (tmds_clock > 0 ? min(165000, tmds_clock) : 165000);
>  	else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
> -		return 300000;
> +		return (tmds_clock > 0 ? min(300000, tmds_clock) : 300000);
>  	else
> -		return 225000;
> +		return (tmds_clock > 0 ? min(225000, tmds_clock) : 225000);

Changing limits for native HDMI ports isn't going to do much when
dealing with active DP dongles.

>  }
>  
>  static enum drm_mode_status
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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✗ Fi.CI.BAT: warning for drm/i915: DP branch devices

[Patchwork]

== Series Details ==

Series: drm/i915: DP branch devices
URL   : https://patchwork.freedesktop.org/series/6658/
State : warning

== Summary ==

Series 6658v1 drm/i915: DP branch devices
http://patchwork.freedesktop.org/api/1.0/series/6658/revisions/1/mbox/

Test kms_force_connector_basic:
        Subgroup force-load-detect:
                skip       -> PASS       (snb-x220t)
        Subgroup prune-stale-modes:
                skip       -> PASS       (snb-x220t)
Test kms_setmode:
        Subgroup basic-clone-single-crtc:
                pass       -> DMESG-WARN (bdw-ultra)

bdw-nuci7-2      total:221  pass:209  dwarn:0   dfail:0   fail:0   skip:12 
bdw-ultra        total:221  pass:195  dwarn:1   dfail:0   fail:0   skip:25 
byt-nuc          total:220  pass:176  dwarn:0   dfail:0   fail:3   skip:41 
hsw-brixbox      total:221  pass:195  dwarn:0   dfail:0   fail:0   skip:26 
hsw-gt2          total:65   pass:58   dwarn:0   dfail:0   fail:0   skip:6  
ilk-hp8440p      total:221  pass:158  dwarn:0   dfail:0   fail:2   skip:61 
ivb-t430s        total:221  pass:190  dwarn:0   dfail:0   fail:0   skip:31 
skl-i7k-2        total:221  pass:194  dwarn:0   dfail:0   fail:0   skip:27 
skl-nuci5        total:221  pass:210  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:221  pass:179  dwarn:0   dfail:0   fail:0   skip:42 
snb-x220t        total:221  pass:179  dwarn:0   dfail:0   fail:1   skip:41 

Results at /archive/results/CI_IGT_test/Patchwork_2128/

4c6b0d9cea0a81653fc290fe64d5c43e7d5c5762 drm-intel-nightly: 2016y-05m-03d-08h-18m-32s UTC integration manifest
4dec1f4 drm/i915: Check HDMI TMDS clock rate from DPCD
5b968cfc drm: Add DP port types from DP 1.3 specification
edadc83 drm/i915: Check pixel rate for DP to VGA dongle

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