From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>,
Daniel Vetter <daniel@ffwll.ch>,
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
intel-gfx@lists.freedesktop.org,
Dave Gordon <david.s.gordon@intel.com>
Subject: Re: [PATCH v2] drm/i915/execlists: Refactor common engine setup
Date: Mon, 9 May 2016 09:58:20 +0200 [thread overview]
Message-ID: <20160509075820.GT27098@phenom.ffwll.local> (raw)
In-Reply-To: <20160509074516.GB12277@nuc-i3427.alporthouse.com>
On Mon, May 09, 2016 at 08:45:16AM +0100, Chris Wilson wrote:
> On Mon, May 09, 2016 at 09:02:33AM +0200, Daniel Vetter wrote:
> > On Mon, May 02, 2016 at 11:58:38AM +0100, Chris Wilson wrote:
> > > On Mon, May 02, 2016 at 10:51:31AM +0200, Daniel Vetter wrote:
> > > > Imo the low-level irq clearing should all be done in the relevant irq
> > > > setup code in i915_irq.c. Atm we just forgot to do that. I guess you can
> > > > have a bikeshed whether the enginer IMR enable/disable functions should be
> > > > together with the clearing or not, placing them in either file is fine.
> > > > But since we already clear the higher-level IMR registers in i915_irq.c we
> > > > might as well clear the low-level ones too in i915_irq.c.
> > >
> > > That's tricky since that is done before the engines - so how do we get
> > > the various bases to i915_irq.c without duplication? Enabling the irq
> > > for the engines is part of init_hw, so correspondingly putting the
> > > early disable into init looks fine to me.
> >
> > I just don't particularly like that we have hw access in a function that
> > thus far (and at a glance still after this patch) only sets up software
> > state. I'll probably lead to some ugly surprise. That's why I'd like to
> > move this either to engine->init_hw or to i915_irq.c.
>
> This is sanitize. We do enable it in engine->init_hw(), but the point
> raised by Ville earlier in his review of GT irq handling is that nobody
> currently disables the ring IMR before use. Here we have a
> chicken-and-egg problem, do we duplicate knowledge of available engines
> (and their mmio_base) in irq preinstall/sanitize or do we do the engine
> specific mmio in engine initialisation? The problem Turslin was raising
> was that on future enabling, somebody had enabled the engine IRQ before
> the engines were initialised (i.e. had completely disregarded the
> current init_hw sequence). Plonking it in i915_irq.c is not foolproof
> either!
Hm, couldn't we put it into init_hw? i915_irq.c sets up the top-level
interrupts, but for GT stuff all masked. In init_hw we could clear that
then, and before init_hw no one should call ring->get_irq to enable it and
potentially cause havoc. Or still too fragile in your opinion?
Indeed putting it into i915_irq.c seems to not be great since it splits
the gt per-engine mask reg handling too far.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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next prev parent reply other threads:[~2016-05-09 7:58 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-28 13:47 [PATCH] drm/i915/execlists: Refactor common engine setup Chris Wilson
2016-04-28 14:17 ` ✗ Fi.CI.BAT: warning for " Patchwork
2016-04-28 15:10 ` [PATCH] " Tvrtko Ursulin
2016-04-28 15:26 ` Chris Wilson
2016-04-28 16:12 ` Dave Gordon
2016-04-28 17:04 ` Chris Wilson
2016-04-28 17:35 ` [PATCH v2] " Chris Wilson
2016-04-29 9:04 ` Tvrtko Ursulin
2016-04-29 9:15 ` Chris Wilson
2016-04-29 9:25 ` Tvrtko Ursulin
2016-04-29 9:39 ` Chris Wilson
2016-04-29 9:50 ` Tvrtko Ursulin
2016-04-29 10:00 ` Chris Wilson
2016-04-29 10:11 ` Tvrtko Ursulin
2016-04-29 10:22 ` Chris Wilson
2016-05-02 8:51 ` Daniel Vetter
2016-05-02 10:58 ` Chris Wilson
2016-05-09 7:02 ` Daniel Vetter
2016-05-09 7:45 ` Chris Wilson
2016-05-09 7:58 ` Daniel Vetter [this message]
2016-05-09 10:41 ` Chris Wilson
2016-05-10 7:46 ` Daniel Vetter
2016-05-10 7:50 ` Chris Wilson
2016-04-29 9:42 ` Chris Wilson
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