From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [Intel-gfx] [PATCH 2/7] drm/i915/psr: Try to program link training times correctly Date: Wed, 18 May 2016 20:39:22 +0300 Message-ID: <20160518173922.GX4329@intel.com> References: <1463590036-17824-1-git-send-email-daniel.vetter@ffwll.ch> <1463590036-17824-2-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <1463590036-17824-2-git-send-email-daniel.vetter@ffwll.ch> Sender: stable-owner@vger.kernel.org To: Daniel Vetter Cc: Intel Graphics Development , Daniel Vetter , stable@vger.kernel.org, "Pandiyan, Dhinakaran" , Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org On Wed, May 18, 2016 at 06:47:11PM +0200, Daniel Vetter wrote: > Oops. Hw default for programming these fields to 0 is "skip link > training". Display won't take that too well usually. s/skip/500 usec/ >=20 > v2: Unbotch the math a bit. >=20 > v3: Drop debug hunk. >=20 > Tested-by: Lyude > Cc: Lyude > Cc: stable@vger.kernel.org > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=3D95176 > Cc: Rodrigo Vivi > Cc: Sonika Jindal > Cc: Durgadoss R > Cc: "Pandiyan, Dhinakaran" > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/intel_psr.c | 55 ++++++++++++++++++++++++++++++= ++++------ > 1 file changed, 47 insertions(+), 8 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/= intel_psr.c > index c3abae4bc596..a788d1e9589b 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -280,7 +280,10 @@ static void hsw_psr_enable_source(struct intel_d= p *intel_dp) > * with the 5 or 6 idle patterns. > */ > uint32_t idle_frames =3D max(6, dev_priv->vbt.psr.idle_frames); > - uint32_t val =3D 0x0; > + uint32_t val =3D EDP_PSR_ENABLE; > + > + val |=3D max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; > + val |=3D idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; > =20 > if (IS_HASWELL(dev)) > val |=3D EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; > @@ -288,14 +291,50 @@ static void hsw_psr_enable_source(struct intel_= dp *intel_dp) > if (dev_priv->psr.link_standby) > val |=3D EDP_PSR_LINK_STANDBY; > =20 > - I915_WRITE(EDP_PSR_CTL, val | > - max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | > - idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | > - EDP_PSR_ENABLE); > + if (dev_priv->vbt.psr.tp1_wakeup_time > 5) > + val |=3D EDP_PSR_TP1_TIME_2500us; > + else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) > + val |=3D EDP_PSR_TP1_TIME_500us; > + else if (dev_priv->vbt.psr.tp1_wakeup_time > 0) > + val |=3D EDP_PSR_TP1_TIME_100us; > + else > + val |=3D EDP_PSR_TP1_TIME_0us; > + > + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) > + val |=3D EDP_PSR_TP2_TP3_TIME_2500us; > + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) > + val |=3D EDP_PSR_TP2_TP3_TIME_500us; > + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) > + val |=3D EDP_PSR_TP2_TP3_TIME_100us; > + else > + val |=3D EDP_PSR_TP2_TP3_TIME_0us; The current vbt spec is confusing. But after some head scratching this does look correct. Reviewed-by: Ville Syrj=E4l=E4 > + > + if (intel_dp_source_supports_hbr2(intel_dp) && > + drm_dp_tps3_supported(intel_dp->dpcd)) > + val |=3D EDP_PSR_TP1_TP3_SEL; > + else > + val |=3D EDP_PSR_TP1_TP2_SEL; > + > + I915_WRITE(EDP_PSR_CTL, val); > + > + if (!dev_priv->psr.psr2_support) > + return; > + > + /* FIXME: selective update is probably totally broken because it do= esn't > + * mesh at all with our frontbuffer tracking. And the hw alone isn'= t > + * good enough. */ > + val =3D EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; > + > + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) > + val |=3D EDP_PSR2_TP2_TIME_2500; > + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) > + val |=3D EDP_PSR2_TP2_TIME_500; > + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) > + val |=3D EDP_PSR2_TP2_TIME_100; > + else > + val |=3D EDP_PSR2_TP2_TIME_50; > =20 > - if (dev_priv->psr.psr2_support) > - I915_WRITE(EDP_PSR2_CTL, EDP_PSR2_ENABLE | > - EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100); > + I915_WRITE(EDP_PSR2_CTL, val); > } > =20 > static bool intel_psr_match_conditions(struct intel_dp *intel_dp) > --=20 > 2.8.1 >=20 > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx --=20 Ville Syrj=E4l=E4 Intel OTC