From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [Intel-gfx] [PATCH 2/7] drm/i915/psr: Try to program link training times correctly Date: Wed, 18 May 2016 21:09:49 +0300 Message-ID: <20160518180949.GC4329@intel.com> References: <1463590036-17824-1-git-send-email-daniel.vetter@ffwll.ch> <1463590036-17824-2-git-send-email-daniel.vetter@ffwll.ch> <20160518173922.GX4329@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: Sender: stable-owner@vger.kernel.org To: Daniel Vetter Cc: Intel Graphics Development , Daniel Vetter , stable , "Pandiyan, Dhinakaran" , Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org On Wed, May 18, 2016 at 08:04:02PM +0200, Daniel Vetter wrote: > On Wed, May 18, 2016 at 7:39 PM, Ville Syrj=E4l=E4 > wrote: > > On Wed, May 18, 2016 at 06:47:11PM +0200, Daniel Vetter wrote: > >> Oops. Hw default for programming these fields to 0 is "skip link > >> training". Display won't take that too well usually. > > > > s/skip/500 usec/ >=20 > Yeah, my reading skills have reached an all time low ;-) But we > confirmed on irc that the hardcoded 500usec was indeed wrong, since > the fixed machines now run on 2.5ms of link training time. I'll updat= e > the commit message when merging to reflect that. Also >=20 > Tested-by: Ville Syrj=E4l=E4 That can be slapped onto the entire series. > Tested-by: fritsch@kodi.tv > --=20 > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch --=20 Ville Syrj=E4l=E4 Intel OTC