[PATCH 00/21] drm/i915: SKL/KBL/BXT cdclk stuff

[PATCH 00/21] drm/i915: SKL/KBL/BXT cdclk stuff

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Here's my second installment of SKL+ cdclk stuff. I've picked up Clint's latest
SKL/KBL cdclk patch and expanded on it quite a bit. After this series we're
capable of actually changing the DPLL0 VCO frequency dynamically, and a lot of
the code gets a much more uniform feel to it between SKL/KBL vs. BXT. This
should make it possible to land some future hardware work on top as well,
without making the code an awful mess.

Series available here:
git://github.com/vsyrjala/linux.git skl_bxt_cdclk_part_2

Clint Taylor (1):
  drm/i915/skl: SKL CDCLK change on modeset tracking VCO

Ville Syrjälä (20):
  drm/i915: Fix BXT min_pixclk after state readout
  drm/i915: Move the SKL DPLL0 VCO computation into
    intel_dp_compute_config()
  drm/i915: Extract skl_calc_cdclk()
  drm/i915: Actually read out DPLL0 vco on skl from hardware
  drm/i915: Report the current DPLL0 vco on SKL/KBL
  drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL
  drm/i915: Keep track of preferred cdclk vco frequency on SKL
  drm/i915: Beef up skl_sanitize_cdclk() a bit
  drm/i915: Unify SKL cdclk init paths
  drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit
  drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL
  drm/i915: Rename skl_vco_freq to cdclk_pll.vco
  drm/i915: Store cdclk PLL reference clock under dev_priv
  drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk()
  drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv
  drm/i915: Update cached cdclk state from broxton_init_cdclk()
  drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE
    PLL vco/refclk
  drm/i915: Make bxt_set_cdclk() operate in terms of the current vs
    target DE PLL vco
  drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk
    check
  drm/i915: Set BXT cdclk to minimum initially

 drivers/gpu/drm/i915/i915_drv.h         |   6 +-
 drivers/gpu/drm/i915/intel_display.c    | 623 +++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_dp.c         |  21 ++
 drivers/gpu/drm/i915/intel_dpll_mgr.c   |  19 +-
 drivers/gpu/drm/i915/intel_drv.h        |   7 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c |  45 ++-
 6 files changed, 443 insertions(+), 278 deletions(-)

-- 
2.7.4

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[PATCH 01/21] drm/i915: Fix BXT min_pixclk after state readout

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

commit 4e5ca60fd35a ("drm/i915: Use ilk_max_pixel_rate() for BXT cdclk calculation")
tried to change BXT to use ilk_max_pixel_rate() to compute the
pipe pixel rate. I failed to notice that there was another place
in the state readout code that needs the same treatment. So let's
change that one too.

Should probably just change things to always compuyte the pipe pixel
rates, instead of just doing on platforms that can change cdclk
dynamically. But for now let's just move BXT fully over to the
side that uses ilk_pipe_pixel_rate().

Cc: Jani Nikula <jani.nikula@intel.com>
Fixes: 4e5ca60fd35a ("drm/i915: Use ilk_max_pixel_rate() for BXT cdclk calculation")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c5f0a6f30879..cc9a8b42fbc6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15748,18 +15748,16 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 		if (crtc_state->base.active) {
 			dev_priv->active_crtcs |= 1 << crtc->pipe;
 
-			if (IS_BROADWELL(dev_priv)) {
+			if (IS_BROXTON(dev_priv) || IS_BROADWELL(dev_priv))
 				pixclk = ilk_pipe_pixel_rate(crtc_state);
-
-				/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-				if (crtc_state->ips_enabled)
-					pixclk = DIV_ROUND_UP(pixclk * 100, 95);
-			} else if (IS_VALLEYVIEW(dev_priv) ||
-				   IS_CHERRYVIEW(dev_priv) ||
-				   IS_BROXTON(dev_priv))
+			else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 				pixclk = crtc_state->base.adjusted_mode.crtc_clock;
 			else
 				WARN_ON(dev_priv->display.modeset_calc_cdclk);
+
+			/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
+			if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
+				pixclk = DIV_ROUND_UP(pixclk * 100, 95);
 		}
 
 		dev_priv->min_pixclk[crtc->pipe] = pixclk;
-- 
2.7.4

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[PATCH 02/21] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[ville.syrjala]

From: Clint Taylor <clinton.a.taylor@intel.com>

WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the cdclk is less then required. DP connected to DDI2
and HPD on either port works correctly.

Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.

The vco is now tracked at the atomic level and all CRTCs updated if
the required vco is changed. Not tested with eDP v1.4 panels that
require 8640 vco due to availability.

V1: initial version
V2: add vco tracking in intel_dp_compute_config(), rename
skl_boot_cdclk.
V3: rebase, V2 feedback not possible as encoders are not aware of
atomic.
V4: track target vco is atomic state. modeset all CRTCs if vco changes
V5: rename atomic variable, cleaner if/else logic, use existing vco if
      encoder does not return a new vco value. check_patch.pl cleanup
V6: simplify logic in intel_modeset_checks.
V7: reorder an IF for readability and whitespace fix.
V8: use dev_cdclk for tracking new cdclk during atomic
V9: correctly handle vco 8640 when crtcs==0
V10: Clean up if else in crtcs==0
V11: Rebase for new intel_dpll_mgr.c

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
[vsyrjala: rebased due to churn]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |   2 +-
 drivers/gpu/drm/i915/intel_display.c  | 109 +++++++++++++++++++++++++++++-----
 drivers/gpu/drm/i915/intel_dpll_mgr.c |   9 +--
 drivers/gpu/drm/i915/intel_drv.h      |   4 ++
 4 files changed, 104 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1ba614193cc9..b319da970c8a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1820,7 +1820,7 @@ struct drm_i915_private {
 	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
 	unsigned int fsb_freq, mem_freq, is_ddr3;
-	unsigned int skl_boot_cdclk;
+	unsigned int skl_vco_freq;
 	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
 	unsigned int max_dotclk_freq;
 	unsigned int rawclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cc9a8b42fbc6..41fe18c4b761 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5540,7 +5540,7 @@ static const struct skl_cdclk_entry {
 	{ .freq = 675000, .vco = 8100 },
 };
 
-static unsigned int skl_cdclk_get_vco(unsigned int freq)
+unsigned int skl_cdclk_get_vco(unsigned int freq)
 {
 	unsigned int i;
 
@@ -5698,17 +5698,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
 {
-	unsigned int vco;
+	unsigned int cdclk;
 
 	/* DPLL0 not enabled (happens on early BIOS versions) */
 	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
 		/* enable DPLL0 */
-		vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
-		skl_dpll0_enable(dev_priv, vco);
+		if (dev_priv->skl_vco_freq != 8640)
+			dev_priv->skl_vco_freq = 8100;
+		skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
+		cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+	} else {
+		cdclk = dev_priv->cdclk_freq;
 	}
 
-	/* set CDCLK to the frequency the BIOS chose */
-	skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
+	/* set CDCLK to the lowest frequency, Modeset follows */
+	skl_set_cdclk(dev_priv, cdclk);
 
 	/* enable DBUF power */
 	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -5724,7 +5728,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
 	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
 	uint32_t cdctl = I915_READ(CDCLK_CTL);
-	int freq = dev_priv->skl_boot_cdclk;
+	int freq = dev_priv->cdclk_freq;
 
 	/*
 	 * check if the pre-os intialized the display
@@ -5748,11 +5752,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 		/* All well; nothing to sanitize */
 		return false;
 sanitize:
-	/*
-	 * As of now initialize with max cdclk till
-	 * we get dynamic cdclk support
-	 * */
-	dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
+
 	skl_init_cdclk(dev_priv);
 
 	/* we did have to sanitize */
@@ -9719,6 +9719,73 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
 	broadwell_set_cdclk(dev, req_cdclk);
 }
 
+static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
+{
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+	struct drm_i915_private *dev_priv = to_i915(state->dev);
+	const int max_pixclk = ilk_max_pixel_rate(state);
+	int cdclk;
+
+	/*
+	 * FIXME should also account for plane ratio
+	 * once 64bpp pixel formats are supported.
+	 */
+
+	if (intel_state->cdclk_pll_vco == 8640) {
+		/* vco 8640 */
+		if (max_pixclk > 540000)
+			cdclk = 617140;
+		else if (max_pixclk > 432000)
+			cdclk = 540000;
+		else if (max_pixclk > 308570)
+			cdclk = 432000;
+		else
+			cdclk = 308570;
+	} else {
+		/* VCO 8100 */
+		if (max_pixclk > 540000)
+			cdclk = 675000;
+		else if (max_pixclk > 450000)
+			cdclk = 540000;
+		else if (max_pixclk > 337500)
+			cdclk = 450000;
+		else
+			cdclk = 337500;
+	}
+
+	/*
+	 * FIXME move the cdclk caclulation to
+	 * compute_config() so we can fail gracegully.
+	 */
+	if (cdclk > dev_priv->max_cdclk_freq) {
+		DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
+			  cdclk, dev_priv->max_cdclk_freq);
+		cdclk = dev_priv->max_cdclk_freq;
+	}
+
+	intel_state->cdclk = intel_state->dev_cdclk = cdclk;
+	if (!intel_state->active_crtcs)
+		intel_state->dev_cdclk = ((intel_state->cdclk_pll_vco == 8640) ?
+					   308570 : 337500);
+
+
+	return 0;
+}
+
+static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
+{
+	struct drm_device *dev = old_state->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
+
+	/*
+	 * FIXME disable/enable PLL should wrap set_cdclk()
+	 */
+	skl_set_cdclk(dev_priv, req_cdclk);
+
+	dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
+}
+
 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
 				      struct intel_crtc_state *crtc_state)
 {
@@ -13283,9 +13350,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
 	 * adjusted_mode bits in the crtc directly.
 	 */
 	if (dev_priv->display.modeset_calc_cdclk) {
+		if (!intel_state->cdclk_pll_vco)
+			intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
+
 		ret = dev_priv->display.modeset_calc_cdclk(state);
+		if (ret < 0)
+			return ret;
 
-		if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
+		if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
+		    intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
 			ret = intel_modeset_all_pipes(state);
 
 		if (ret < 0)
@@ -13626,7 +13699,8 @@ static int intel_atomic_commit(struct drm_device *dev,
 		drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
 
 		if (dev_priv->display.modeset_commit_cdclk &&
-		    intel_state->dev_cdclk != dev_priv->cdclk_freq)
+		    (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
+		     intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
 			dev_priv->display.modeset_commit_cdclk(state);
 
 		intel_modeset_verify_disabled(dev);
@@ -15041,6 +15115,11 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
 			broxton_modeset_commit_cdclk;
 		dev_priv->display.modeset_calc_cdclk =
 			broxton_modeset_calc_cdclk;
+	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
+		dev_priv->display.modeset_commit_cdclk =
+			skl_modeset_commit_cdclk;
+		dev_priv->display.modeset_calc_cdclk =
+			skl_modeset_calc_cdclk;
 	}
 
 	switch (INTEL_INFO(dev_priv)->gen) {
@@ -15748,7 +15827,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 		if (crtc_state->base.active) {
 			dev_priv->active_crtcs |= 1 << crtc->pipe;
 
-			if (IS_BROXTON(dev_priv) || IS_BROADWELL(dev_priv))
+			if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
 				pixclk = ilk_pipe_pixel_rate(crtc_state);
 			else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 				pixclk = crtc_state->base.adjusted_mode.crtc_clock;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index c283ba4babe8..e99e306e8743 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1194,6 +1194,7 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
 	struct intel_shared_dpll *pll;
 	uint32_t ctrl1, cfgcr1, cfgcr2;
 	int clock = crtc_state->port_clock;
+	uint32_t vco = 8100;
 
 	/*
 	 * See comment in intel_dpll_hw_state to understand why we always use 0
@@ -1236,17 +1237,17 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
 		case 162000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
 			break;
-		/* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
-		results in CDCLK change. Need to handle the change of CDCLK by
-		disabling pipes and re-enabling them */
 		case 108000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
+			vco = 8640;
 			break;
 		case 216000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
+			vco = 8640;
 			break;
 		}
 
+		to_intel_atomic_state(crtc_state->base.state)->cdclk_pll_vco = vco;
 		cfgcr1 = cfgcr2 = 0;
 	} else {
 		return NULL;
@@ -1639,7 +1640,7 @@ static void intel_ddi_pll_init(struct drm_device *dev)
 		int cdclk_freq;
 
 		cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-		dev_priv->skl_boot_cdclk = cdclk_freq;
+		dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
 		if (skl_sanitize_cdclk(dev_priv))
 			DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
 		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0dc2bc9c65cf..c7cb9829547e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -304,6 +304,9 @@ struct intel_atomic_state {
 	unsigned int active_crtcs;
 	unsigned int min_pixclk[I915_MAX_PIPES];
 
+	/* SKL/KBL Only */
+	unsigned int cdclk_pll_vco;
+
 	struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 
 	/*
@@ -1277,6 +1280,7 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv);
 void skl_init_cdclk(struct drm_i915_private *dev_priv);
 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+unsigned int skl_cdclk_get_vco(unsigned int freq);
 void skl_enable_dc6(struct drm_i915_private *dev_priv);
 void skl_disable_dc6(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
-- 
2.7.4

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[PATCH 03/21] drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Shared plls won't get assigned until the .compute_clocks() hook gets
called, which happens from the crtc .atomic_check hook. That's too late
as the cdclk computation has already happened. So let's move the DPLL0
VCO computation into intel_dp_compute_config() so that it's done when
the cdclk computation happens. Also only do it for eDP since we only
pick DPLL0 for eDP.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c       | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  4 ----
 2 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 36330026ceff..908c6f0f7feb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1577,6 +1577,27 @@ found:
 				&pipe_config->dp_m2_n2);
 	}
 
+	/*
+	 * DPLL0 VCO may need to be adjusted to get the correct
+	 * clock for eDP. This will affect cdclk as well.
+	 */
+	if (is_edp(intel_dp) &&
+	    (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
+		int vco;
+
+		switch (pipe_config->port_clock / 2) {
+		case 108000:
+		case 216000:
+			vco = 8640;
+			break;
+		default:
+			vco = 8100;
+			break;
+		}
+
+		to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
+	}
+
 	if (!HAS_DDI(dev))
 		intel_dp_set_clock(encoder, pipe_config);
 
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e99e306e8743..43ba60b3662e 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1194,7 +1194,6 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
 	struct intel_shared_dpll *pll;
 	uint32_t ctrl1, cfgcr1, cfgcr2;
 	int clock = crtc_state->port_clock;
-	uint32_t vco = 8100;
 
 	/*
 	 * See comment in intel_dpll_hw_state to understand why we always use 0
@@ -1239,15 +1238,12 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
 			break;
 		case 108000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
-			vco = 8640;
 			break;
 		case 216000:
 			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
-			vco = 8640;
 			break;
 		}
 
-		to_intel_atomic_state(crtc_state->base.state)->cdclk_pll_vco = vco;
 		cfgcr1 = cfgcr2 = 0;
 	} else {
 		return NULL;
-- 
2.7.4

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[PATCH 04/21] drm/i915: Extract skl_calc_cdclk()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have many places where we want to pick a suitable cdclk frequency for
skl based on the dotclock and lcpll vco. Split that code into a small
helper and call it from all over.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 63 +++++++++++++++++-------------------
 1 file changed, 30 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 41fe18c4b761..c1b1632664a1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5527,6 +5527,30 @@ void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
 	broxton_set_cdclk(dev_priv, 19200);
 }
 
+static int skl_calc_cdclk(int max_pixclk, int vco)
+{
+	if (vco == 8640) {
+		if (max_pixclk > 540000)
+			return 617140;
+		else if (max_pixclk > 432000)
+			return 540000;
+		else if (max_pixclk > 308570)
+			return 432000;
+		else
+			return 308570;
+	} else {
+		/* VCO 8100 */
+		if (max_pixclk > 540000)
+			return 675000;
+		else if (max_pixclk > 450000)
+			return 540000;
+		else if (max_pixclk > 337500)
+			return 450000;
+		else
+			return 337500;
+	}
+}
+
 static const struct skl_cdclk_entry {
 	unsigned int freq;
 	unsigned int vco;
@@ -5557,15 +5581,10 @@ unsigned int skl_cdclk_get_vco(unsigned int freq)
 static void
 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 {
-	int min_cdclk;
+	int min_cdclk = skl_calc_cdclk(0, vco);
 	u32 val;
 
 	/* select the minimum CDCLK before enabling DPLL 0 */
-	if (vco == 8640)
-		min_cdclk = 308570;
-	else
-		min_cdclk = 337500;
-
 	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
 	I915_WRITE(CDCLK_CTL, val);
 	POSTING_READ(CDCLK_CTL);
@@ -5577,7 +5596,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 	 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 	 * The modeset code is responsible for the selection of the exact link
 	 * rate later on, with the constraint of choosing a frequency that
-	 * works with required_vco.
+	 * works with vco.
 	 */
 	val = I915_READ(DPLL_CTRL1);
 
@@ -5706,7 +5725,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
 		if (dev_priv->skl_vco_freq != 8640)
 			dev_priv->skl_vco_freq = 8100;
 		skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
-		cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+		cdclk = skl_calc_cdclk(0, dev_priv->skl_vco_freq);
 	} else {
 		cdclk = dev_priv->cdclk_freq;
 	}
@@ -9724,34 +9743,14 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
 	struct drm_i915_private *dev_priv = to_i915(state->dev);
 	const int max_pixclk = ilk_max_pixel_rate(state);
+	int vco = intel_state->cdclk_pll_vco;
 	int cdclk;
 
 	/*
 	 * FIXME should also account for plane ratio
 	 * once 64bpp pixel formats are supported.
 	 */
-
-	if (intel_state->cdclk_pll_vco == 8640) {
-		/* vco 8640 */
-		if (max_pixclk > 540000)
-			cdclk = 617140;
-		else if (max_pixclk > 432000)
-			cdclk = 540000;
-		else if (max_pixclk > 308570)
-			cdclk = 432000;
-		else
-			cdclk = 308570;
-	} else {
-		/* VCO 8100 */
-		if (max_pixclk > 540000)
-			cdclk = 675000;
-		else if (max_pixclk > 450000)
-			cdclk = 540000;
-		else if (max_pixclk > 337500)
-			cdclk = 450000;
-		else
-			cdclk = 337500;
-	}
+	cdclk = skl_calc_cdclk(max_pixclk, vco);
 
 	/*
 	 * FIXME move the cdclk caclulation to
@@ -9765,9 +9764,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
 
 	intel_state->cdclk = intel_state->dev_cdclk = cdclk;
 	if (!intel_state->active_crtcs)
-		intel_state->dev_cdclk = ((intel_state->cdclk_pll_vco == 8640) ?
-					   308570 : 337500);
-
+		intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
 
 	return 0;
 }
-- 
2.7.4

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[PATCH 05/21] drm/i915: Actually read out DPLL0 vco on skl from hardware

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we're trying to guess which lcpll vco frequency is used
use based on the cdclk. That doesn't work for cdclk==540 since
both vco frequencies can generate a 540 Mhz output. Let's stop
guessing and just read the actual vco frequency from the
hardware.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c  | 73 ++++++++++++++++++-----------------
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  6 ---
 2 files changed, 37 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c1b1632664a1..e65c3da744b0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5551,31 +5551,35 @@ static int skl_calc_cdclk(int max_pixclk, int vco)
 	}
 }
 
-static const struct skl_cdclk_entry {
-	unsigned int freq;
-	unsigned int vco;
-} skl_cdclk_frequencies[] = {
-	{ .freq = 308570, .vco = 8640 },
-	{ .freq = 337500, .vco = 8100 },
-	{ .freq = 432000, .vco = 8640 },
-	{ .freq = 450000, .vco = 8100 },
-	{ .freq = 540000, .vco = 8100 },
-	{ .freq = 617140, .vco = 8640 },
-	{ .freq = 675000, .vco = 8100 },
-};
-
-unsigned int skl_cdclk_get_vco(unsigned int freq)
+static void
+skl_dpll0_update(struct drm_i915_private *dev_priv)
 {
-	unsigned int i;
-
-	for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
-		const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
+	u32 val;
 
-		if (e->freq == freq)
-			return e->vco;
+	val = I915_READ(LCPLL1_CTL);
+	if ((val & LCPLL_PLL_ENABLE) == 0) {
+		dev_priv->skl_vco_freq = 0;
+		return;
 	}
 
-	return 8100;
+	val = I915_READ(DPLL_CTRL1);
+
+	switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
+	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
+	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
+	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
+	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
+		dev_priv->skl_vco_freq = 8100;
+		break;
+	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
+	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
+		dev_priv->skl_vco_freq = 8640;
+		break;
+	default:
+		MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
+		dev_priv->skl_vco_freq = 0;
+		break;
+	}
 }
 
 static void
@@ -6614,43 +6618,40 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
 static int skylake_get_display_clock_speed(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
-	uint32_t cdctl = I915_READ(CDCLK_CTL);
-	uint32_t linkrate;
+	uint32_t cdctl;
 
-	if (!(lcpll1 & LCPLL_PLL_ENABLE))
-		return 24000; /* 24MHz is the cd freq with NSSC ref */
+	skl_dpll0_update(dev_priv);
 
-	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
-		return 540000;
+	if (dev_priv->skl_vco_freq == 0)
+		return 24000; /* 24MHz is the cd freq with NSSC ref */
 
-	linkrate = (I915_READ(DPLL_CTRL1) &
-		    DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
+	cdctl = I915_READ(CDCLK_CTL);
 
-	if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
-	    linkrate == DPLL_CTRL1_LINK_RATE_1080) {
-		/* vco 8640 */
+	if (dev_priv->skl_vco_freq == 8640) {
 		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 		case CDCLK_FREQ_450_432:
 			return 432000;
 		case CDCLK_FREQ_337_308:
 			return 308570;
+		case CDCLK_FREQ_540:
+			return 540000;
 		case CDCLK_FREQ_675_617:
 			return 617140;
 		default:
-			WARN(1, "Unknown cd freq selection\n");
+			MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 		}
 	} else {
-		/* vco 8100 */
 		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 		case CDCLK_FREQ_450_432:
 			return 450000;
 		case CDCLK_FREQ_337_308:
 			return 337500;
+		case CDCLK_FREQ_540:
+			return 540000;
 		case CDCLK_FREQ_675_617:
 			return 675000;
 		default:
-			WARN(1, "Unknown cd freq selection\n");
+			MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 43ba60b3662e..5391ab66b64d 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1633,14 +1633,8 @@ static void intel_ddi_pll_init(struct drm_device *dev)
 	uint32_t val = I915_READ(LCPLL_CTL);
 
 	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
-		int cdclk_freq;
-
-		cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-		dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
 		if (skl_sanitize_cdclk(dev_priv))
 			DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
-		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
-			DRM_ERROR("LCPLL1 is disabled\n");
 	} else if (!IS_BROXTON(dev_priv)) {
 		/*
 		 * The LCPLL register should be turned on by the BIOS. For now
-- 
2.7.4

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[PATCH 06/21] drm/i915: Report the current DPLL0 vco on SKL/KBL

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e65c3da744b0..95997eed9dd6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5320,8 +5320,13 @@ static void intel_update_cdclk(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
-	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
-			 dev_priv->cdclk_freq);
+
+	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
+		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d MHz\n",
+				 dev_priv->cdclk_freq, dev_priv->skl_vco_freq);
+	else
+		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
+				 dev_priv->cdclk_freq);
 
 	/*
 	 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
-- 
2.7.4

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[PATCH 07/21] drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In case we originally guessed wrong which lcpll vco frequency to use,
we will need to shut down the pll and restart it when reprogamming the
cdclk.

This also allows us to track the actual vco frequency in dev_priv
instead of just a guess.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 54 +++++++++++++++++++-----------------
 1 file changed, 29 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 95997eed9dd6..cd2809179042 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5626,6 +5626,8 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 
 	if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
 		DRM_ERROR("DPLL0 not locked\n");
+
+	dev_priv->skl_vco_freq = vco;
 }
 
 static void
@@ -5634,6 +5636,8 @@ skl_dpll0_disable(struct drm_i915_private *dev_priv)
 	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 	if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
 		DRM_ERROR("Couldn't disable DPLL0\n");
+
+	dev_priv->skl_vco_freq = 0;
 }
 
 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
@@ -5663,12 +5667,14 @@ static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
 	return false;
 }
 
-static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
+static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
 {
 	struct drm_device *dev = dev_priv->dev;
 	u32 freq_select, pcu_ack;
 
-	DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", cdclk);
+	WARN_ON((cdclk == 24000) != (vco == 0));
+
+	DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d MHz)\n", cdclk, vco);
 
 	if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
 		DRM_ERROR("failed to inform PCU about cdclk change\n");
@@ -5699,6 +5705,13 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
 		break;
 	}
 
+	if (dev_priv->skl_vco_freq != 0 &&
+	    dev_priv->skl_vco_freq != vco)
+		skl_dpll0_disable(dev_priv);
+
+	if (dev_priv->skl_vco_freq != vco)
+		skl_dpll0_enable(dev_priv, vco);
+
 	I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
 	POSTING_READ(CDCLK_CTL);
 
@@ -5721,26 +5734,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
 		DRM_ERROR("DBuf power disable timeout\n");
 
-	skl_dpll0_disable(dev_priv);
+	skl_set_cdclk(dev_priv, 24000, 0);
 }
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
 {
-	unsigned int cdclk;
-
 	/* DPLL0 not enabled (happens on early BIOS versions) */
-	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
-		/* enable DPLL0 */
-		if (dev_priv->skl_vco_freq != 8640)
-			dev_priv->skl_vco_freq = 8100;
-		skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
-		cdclk = skl_calc_cdclk(0, dev_priv->skl_vco_freq);
-	} else {
-		cdclk = dev_priv->cdclk_freq;
-	}
+	if (dev_priv->skl_vco_freq == 0) {
+		int cdclk, vco;
 
-	/* set CDCLK to the lowest frequency, Modeset follows */
-	skl_set_cdclk(dev_priv, cdclk);
+		/* set CDCLK to the lowest frequency, Modeset follows */
+		vco = 8100;
+		cdclk = skl_calc_cdclk(0, vco);
+
+		skl_set_cdclk(dev_priv, cdclk, vco);
+	}
 
 	/* enable DBUF power */
 	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
@@ -9777,16 +9785,12 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
 
 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
 {
-	struct drm_device *dev = old_state->dev;
-	struct drm_i915_private *dev_priv = dev->dev_private;
-	unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
-
-	/*
-	 * FIXME disable/enable PLL should wrap set_cdclk()
-	 */
-	skl_set_cdclk(dev_priv, req_cdclk);
+	struct drm_i915_private *dev_priv = to_i915(old_state->dev);
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
+	unsigned int req_cdclk = intel_state->dev_cdclk;
+	unsigned int req_vco = intel_state->cdclk_pll_vco;
 
-	dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
+	skl_set_cdclk(dev_priv, req_cdclk, req_vco);
 }
 
 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
-- 
2.7.4

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[PATCH 08/21] drm/i915: Keep track of preferred cdclk vco frequency on SKL

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that skl_vco_freq tracks the actual DPLL0 vco frequency, we'll need
something that keeps track of which vco frequency we want to use in case
the current vco is 0. This would be important across supend/resume since
we'll disable DPLL0 around those parts.

We'll also update our idea of max cdclk/dotclock when the preferred
vco changes. That could happen if out initial guess was wrong, and
later eDP would force us to change it. One issue here could be that
changing the max dotclock could cause our mode list to change during
next time the displays get probed. But I don't see a good way to avoid
that, except perhaps by allowing either vco frequency to be used as
needed. But the docs suggest that such usage wasn't really inteded.

Also need to make sure we don't update our max_cdclk value before we
have a preferred vco value, which means moving that to happen after
the cdclk sanitation.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/intel_display.c  | 48 +++++++++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  5 ++++
 drivers/gpu/drm/i915/intel_drv.h      |  1 +
 4 files changed, 47 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b319da970c8a..46a22732088e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1821,6 +1821,7 @@ struct drm_i915_private {
 
 	unsigned int fsb_freq, mem_freq, is_ddr3;
 	unsigned int skl_vco_freq;
+	unsigned int skl_preferred_vco_freq;
 	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
 	unsigned int max_dotclk_freq;
 	unsigned int rawclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cd2809179042..107a7799bdde 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5265,21 +5265,34 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 		return max_cdclk_freq*90/100;
 }
 
+static int skl_calc_cdclk(int max_pixclk, int vco);
+
 static void intel_update_max_cdclk(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
+		int max_cdclk, vco;
+
+		vco = dev_priv->skl_preferred_vco_freq;
+		WARN_ON(vco != 8100 && vco != 8640);
 
+		/*
+		 * Use the lower (vco 8640) cdclk values as a
+		 * first guess. skl_calc_cdclk() will correct it
+		 * if the preferred vco is 8100 instead.
+		 */
 		if (limit == SKL_DFSM_CDCLK_LIMIT_675)
-			dev_priv->max_cdclk_freq = 675000;
+			max_cdclk = 617140;
 		else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
-			dev_priv->max_cdclk_freq = 540000;
+			max_cdclk = 540000;
 		else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
-			dev_priv->max_cdclk_freq = 450000;
+			max_cdclk = 432000;
 		else
-			dev_priv->max_cdclk_freq = 337500;
+			max_cdclk = 308570;
+
+		dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
 	} else if (IS_BROXTON(dev)) {
 		dev_priv->max_cdclk_freq = 624000;
 	} else if (IS_BROADWELL(dev))  {
@@ -5336,9 +5349,6 @@ static void intel_update_cdclk(struct drm_device *dev)
 	 */
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
-
-	if (dev_priv->max_cdclk_freq == 0)
-		intel_update_max_cdclk(dev);
 }
 
 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
@@ -5587,12 +5597,24 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
 	}
 }
 
+void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
+{
+	bool changed = dev_priv->skl_preferred_vco_freq != vco;
+
+	dev_priv->skl_preferred_vco_freq = vco;
+
+	if (changed)
+		intel_update_max_cdclk(dev_priv->dev);
+}
+
 static void
 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 {
 	int min_cdclk = skl_calc_cdclk(0, vco);
 	u32 val;
 
+	WARN_ON(vco != 8100 && vco != 8640);
+
 	/* select the minimum CDCLK before enabling DPLL 0 */
 	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
 	I915_WRITE(CDCLK_CTL, val);
@@ -5628,6 +5650,9 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 		DRM_ERROR("DPLL0 not locked\n");
 
 	dev_priv->skl_vco_freq = vco;
+
+	/* We'll want to keep using the current vco from now on. */
+	skl_set_preferred_cdclk_vco(dev_priv, vco);
 }
 
 static void
@@ -5744,7 +5769,9 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
 		int cdclk, vco;
 
 		/* set CDCLK to the lowest frequency, Modeset follows */
-		vco = 8100;
+		vco = dev_priv->skl_preferred_vco_freq;
+		if (vco == 0)
+			vco = 8100;
 		cdclk = skl_calc_cdclk(0, vco);
 
 		skl_set_cdclk(dev_priv, cdclk, vco);
@@ -13359,6 +13386,8 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
 	if (dev_priv->display.modeset_calc_cdclk) {
 		if (!intel_state->cdclk_pll_vco)
 			intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
+		if (!intel_state->cdclk_pll_vco)
+			intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
 
 		ret = dev_priv->display.modeset_calc_cdclk(state);
 		if (ret < 0)
@@ -15525,6 +15554,9 @@ void intel_modeset_init(struct drm_device *dev)
 
 	intel_shared_dpll_init(dev);
 
+	if (dev_priv->max_cdclk_freq == 0)
+		intel_update_max_cdclk(dev);
+
 	/* Just disable it once at startup */
 	i915_disable_vga(dev);
 	intel_setup_outputs(dev);
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 5391ab66b64d..34ec149fde85 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1635,6 +1635,11 @@ static void intel_ddi_pll_init(struct drm_device *dev)
 	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 		if (skl_sanitize_cdclk(dev_priv))
 			DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
+
+		/* We'll want to keep using the current vco from now on */
+		if (dev_priv->skl_vco_freq != 0)
+			skl_set_preferred_cdclk_vco(dev_priv,
+						    dev_priv->skl_vco_freq);
 	} else if (!IS_BROXTON(dev_priv)) {
 		/*
 		 * The LCPLL register should be turned on by the BIOS. For now
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c7cb9829547e..8f48a32e991b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1145,6 +1145,7 @@ void i915_audio_component_init(struct drm_i915_private *dev_priv);
 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
 
 /* intel_display.c */
+void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
 void intel_update_rawclk(struct drm_i915_private *dev_priv);
 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 		      const char *name, u32 reg, int ref_freq);
-- 
2.7.4

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[PATCH 09/21] drm/i915: Beef up skl_sanitize_cdclk() a bit

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Also verify the DPLL_CTRL1 register value in skl_sanitize_cdclk(), throw
out a few unneeded variables, and write the CDCLK_CTL check a bit more
legible way.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 107a7799bdde..493160682b2a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5789,9 +5789,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
 
 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
-	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
-	uint32_t cdctl = I915_READ(CDCLK_CTL);
-	int freq = dev_priv->cdclk_freq;
+	uint32_t cdctl, expected;
 
 	/*
 	 * check if the pre-os intialized the display
@@ -5802,7 +5800,14 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 		goto sanitize;
 
 	/* Is PLL enabled and locked ? */
-	if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
+	if ((I915_READ(LCPLL1_CTL) & (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK)) !=
+	    (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK))
+		goto sanitize;
+
+	if ((I915_READ(DPLL_CTRL1) & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
+				      DPLL_CTRL1_SSC(SKL_DPLL0) |
+				      DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
+	    DPLL_CTRL1_OVERRIDE(SKL_DPLL0))
 		goto sanitize;
 
 	/* DPLL okay; verify the cdclock
@@ -5811,7 +5816,10 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	 * decimal part is programmed wrong from BIOS where pre-os does not
 	 * enable display. Verify the same as well.
 	 */
-	if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
+	cdctl = I915_READ(CDCLK_CTL);
+	expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
+		skl_cdclk_decimal(dev_priv->cdclk_freq);
+	if (cdctl == expected)
 		/* All well; nothing to sanitize */
 		return false;
 sanitize:
-- 
2.7.4

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[PATCH 10/21] drm/i915: Unify SKL cdclk init paths

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we initialize cdclk on SKL from two different places,
depending on whether it's during driver init or resume. Let's
unify it to happen from the same place always, and that place will be
the display core init function.

To do this we first run through the cdclk sanitation code, which will
first verify that the PLL is programmed correctly, after which we can
read out the current cdclk frequency, and once the cdclk is known we
verify that the cdclk "decimal" frequency is programmed correctly. If
any of these fail we will force a cdclk change, and to be safe we also
force the PLL to be turned off and on again. If the sanitation step
didn't notice anything amiss, we'll skip the cdclk programming which
will prevent cdclk reprogramming when the displays might be active.

We can also toss in a few WARNs about the register values into
skl_update_dpll0() since we now know that the PLL state should
always be sane when that function is called.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c    | 40 +++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_dpll_mgr.c   | 11 ++-------
 drivers/gpu/drm/i915/intel_drv.h        |  1 -
 drivers/gpu/drm/i915/intel_runtime_pm.c |  5 +----
 4 files changed, 34 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 493160682b2a..da903b718c11 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5577,8 +5577,15 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
 		return;
 	}
 
+	WARN_ON((val & LCPLL_PLL_LOCK) == 0);
+
 	val = I915_READ(DPLL_CTRL1);
 
+	WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
+			DPLL_CTRL1_SSC(SKL_DPLL0) |
+			DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
+		DPLL_CTRL1_OVERRIDE(SKL_DPLL0));
+
 	switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
@@ -5748,6 +5755,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
 	intel_update_cdclk(dev);
 }
 
+static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
+
 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 {
 	/* disable DBUF power */
@@ -5764,10 +5773,19 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
 {
-	/* DPLL0 not enabled (happens on early BIOS versions) */
-	if (dev_priv->skl_vco_freq == 0) {
-		int cdclk, vco;
+	int cdclk, vco;
+
+	skl_sanitize_cdclk(dev_priv);
 
+	if (dev_priv->cdclk_freq != 0 && dev_priv->skl_vco_freq != 0) {
+		/*
+		 * Use the current vco as out initial
+		 * guess as to what the preferred vco is.
+		 */
+		if (dev_priv->skl_preferred_vco_freq == 0)
+			skl_set_preferred_cdclk_vco(dev_priv,
+						    dev_priv->skl_vco_freq);
+	} else {
 		/* set CDCLK to the lowest frequency, Modeset follows */
 		vco = dev_priv->skl_preferred_vco_freq;
 		if (vco == 0)
@@ -5787,7 +5805,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
 		DRM_ERROR("DBuf power enable timeout\n");
 }
 
-int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
+static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 {
 	uint32_t cdctl, expected;
 
@@ -5810,6 +5828,8 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 	    DPLL_CTRL1_OVERRIDE(SKL_DPLL0))
 		goto sanitize;
 
+	intel_update_cdclk(dev_priv->dev);
+
 	/* DPLL okay; verify the cdclock
 	 *
 	 * Noticed in some instances that the freq selection is correct but
@@ -5821,13 +5841,15 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
 		skl_cdclk_decimal(dev_priv->cdclk_freq);
 	if (cdctl == expected)
 		/* All well; nothing to sanitize */
-		return false;
-sanitize:
+		return;
 
-	skl_init_cdclk(dev_priv);
+sanitize:
+	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
 
-	/* we did have to sanitize */
-	return true;
+	/* force cdclk programming */
+	dev_priv->cdclk_freq = 0;
+	/* force full PLL disable + enable */
+	dev_priv->skl_vco_freq = -1;
 }
 
 /* Adjust CDclk dividers to allow high res or save power if possible */
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 34ec149fde85..6b70e1eccb13 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1630,17 +1630,10 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
 static void intel_ddi_pll_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t val = I915_READ(LCPLL_CTL);
 
-	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
-		if (skl_sanitize_cdclk(dev_priv))
-			DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
+	if (INTEL_GEN(dev_priv) < 9) {
+		uint32_t val = I915_READ(LCPLL_CTL);
 
-		/* We'll want to keep using the current vco from now on */
-		if (dev_priv->skl_vco_freq != 0)
-			skl_set_preferred_cdclk_vco(dev_priv,
-						    dev_priv->skl_vco_freq);
-	} else if (!IS_BROXTON(dev_priv)) {
 		/*
 		 * The LCPLL register should be turned on by the BIOS. For now
 		 * let's just check its state and print errors in case
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8f48a32e991b..319e52278d1f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1279,7 +1279,6 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
 void skl_init_cdclk(struct drm_i915_private *dev_priv);
-int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
 unsigned int skl_cdclk_get_vco(unsigned int freq);
 void skl_enable_dc6(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b69b935516fb..fefe22c3c163 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2200,12 +2200,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
 
 	mutex_unlock(&power_domains->lock);
 
-	if (!resume)
-		return;
-
 	skl_init_cdclk(dev_priv);
 
-	if (dev_priv->csr.dmc_payload)
+	if (resume && dev_priv->csr.dmc_payload)
 		intel_csr_load_program(dev_priv);
 }
 
-- 
2.7.4

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[PATCH 11/21] drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

SKL and BXT have the same snippets of code for enabling disabling the
DBUF. Extract those into helpers and move the calls from
init/unit_cdclk() to the display core init/init since this stuff isn't
really about cdclk. Also doing the enable twice shouldn't hurt since
you're just setting the request bit again when it was already set.

We can also toss in a few WARNs about the register values into
skl_get_dpll0_vco() now that we know that things should always be
sane there.

Flatten skl_init_cdclk() while at it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c    | 58 ++++-----------------------------
 drivers/gpu/drm/i915/intel_runtime_pm.c | 32 ++++++++++++++++++
 2 files changed, 38 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index da903b718c11..e908f360da74 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5480,18 +5480,6 @@ static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
 
 	/* TODO: Check for a valid CDCLK rate */
 
-	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
-		DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
-
-		return false;
-	}
-
-	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
-		DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
-
-		return false;
-	}
-
 	return true;
 }
 
@@ -5518,26 +5506,10 @@ void broxton_init_cdclk(struct drm_i915_private *dev_priv)
 	 *   here, it belongs to modeset time
 	 */
 	broxton_set_cdclk(dev_priv, 624000);
-
-	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
-	POSTING_READ(DBUF_CTL);
-
-	udelay(10);
-
-	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
-		DRM_ERROR("DBuf power enable timeout!\n");
 }
 
 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
 {
-	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
-	POSTING_READ(DBUF_CTL);
-
-	udelay(10);
-
-	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
-		DRM_ERROR("DBuf power disable timeout!\n");
-
 	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
 	broxton_set_cdclk(dev_priv, 19200);
 }
@@ -5759,15 +5731,6 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
 
 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 {
-	/* disable DBUF power */
-	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
-	POSTING_READ(DBUF_CTL);
-
-	udelay(10);
-
-	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
-		DRM_ERROR("DBuf power disable timeout\n");
-
 	skl_set_cdclk(dev_priv, 24000, 0);
 }
 
@@ -5785,24 +5748,15 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
 		if (dev_priv->skl_preferred_vco_freq == 0)
 			skl_set_preferred_cdclk_vco(dev_priv,
 						    dev_priv->skl_vco_freq);
-	} else {
-		/* set CDCLK to the lowest frequency, Modeset follows */
-		vco = dev_priv->skl_preferred_vco_freq;
-		if (vco == 0)
-			vco = 8100;
-		cdclk = skl_calc_cdclk(0, vco);
-
-		skl_set_cdclk(dev_priv, cdclk, vco);
+		return;
 	}
 
-	/* enable DBUF power */
-	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
-	POSTING_READ(DBUF_CTL);
-
-	udelay(10);
+	vco = dev_priv->skl_preferred_vco_freq;
+	if (vco == 0)
+		vco = 8100;
+	cdclk = skl_calc_cdclk(0, vco);
 
-	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
-		DRM_ERROR("DBuf power enable timeout\n");
+	skl_set_cdclk(dev_priv, cdclk, vco);
 }
 
 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index fefe22c3c163..6817a3cb5fbc 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2176,6 +2176,28 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
 	mutex_unlock(&power_domains->lock);
 }
 
+static void skl_dbuf_enable(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
+	POSTING_READ(DBUF_CTL);
+
+	udelay(10);
+
+	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
+		DRM_ERROR("DBuf power enable timeout\n");
+}
+
+static void skl_dbuf_disable(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
+	POSTING_READ(DBUF_CTL);
+
+	udelay(10);
+
+	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
+		DRM_ERROR("DBuf power disable timeout!\n");
+}
+
 static void skl_display_core_init(struct drm_i915_private *dev_priv,
 				   bool resume)
 {
@@ -2202,6 +2224,8 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
 
 	skl_init_cdclk(dev_priv);
 
+	skl_dbuf_enable(dev_priv);
+
 	if (resume && dev_priv->csr.dmc_payload)
 		intel_csr_load_program(dev_priv);
 }
@@ -2213,6 +2237,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
+	skl_dbuf_disable(dev_priv);
+
 	skl_uninit_cdclk(dev_priv);
 
 	/* The spec doesn't call for removing the reset handshake flag */
@@ -2257,6 +2283,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
 	mutex_unlock(&power_domains->lock);
 
 	broxton_init_cdclk(dev_priv);
+
+	skl_dbuf_enable(dev_priv);
+
 	broxton_ddi_phy_init(dev_priv);
 
 	broxton_cdclk_verify_state(dev_priv);
@@ -2274,6 +2303,9 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	broxton_ddi_phy_uninit(dev_priv);
+
+	skl_dbuf_disable(dev_priv);
+
 	broxton_uninit_cdclk(dev_priv);
 
 	/* The spec doesn't call for removing the reset handshake flag */
-- 
2.7.4

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[PATCH 12/21] drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The SKL 308.57 MHz cdclk is probably 8640/28 = ~308.571 Mhz.
Similartly the 617.14 MHz cdclk is probably 8640/14 = ~617.143 MHz.
Let's use the slightly more accurate numbers. Potentially we might
change to computing all of these based on dividers, but let's
stick to the current theme for now..

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e908f360da74..c0dbff37e2c3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5284,13 +5284,13 @@ static void intel_update_max_cdclk(struct drm_device *dev)
 		 * if the preferred vco is 8100 instead.
 		 */
 		if (limit == SKL_DFSM_CDCLK_LIMIT_675)
-			max_cdclk = 617140;
+			max_cdclk = 617143;
 		else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
 			max_cdclk = 540000;
 		else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
 			max_cdclk = 432000;
 		else
-			max_cdclk = 308570;
+			max_cdclk = 308571;
 
 		dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
 	} else if (IS_BROXTON(dev)) {
@@ -5518,13 +5518,13 @@ static int skl_calc_cdclk(int max_pixclk, int vco)
 {
 	if (vco == 8640) {
 		if (max_pixclk > 540000)
-			return 617140;
+			return 617143;
 		else if (max_pixclk > 432000)
 			return 540000;
-		else if (max_pixclk > 308570)
+		else if (max_pixclk > 308571)
 			return 432000;
 		else
-			return 308570;
+			return 308571;
 	} else {
 		/* VCO 8100 */
 		if (max_pixclk > 540000)
@@ -5696,13 +5696,13 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
 		freq_select = CDCLK_FREQ_540;
 		pcu_ack = 2;
 		break;
-	case 308570:
+	case 308571:
 	case 337500:
 	default:
 		freq_select = CDCLK_FREQ_337_308;
 		pcu_ack = 0;
 		break;
-	case 617140:
+	case 617143:
 	case 675000:
 		freq_select = CDCLK_FREQ_675_617;
 		pcu_ack = 3;
@@ -6656,11 +6656,11 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
 		case CDCLK_FREQ_450_432:
 			return 432000;
 		case CDCLK_FREQ_337_308:
-			return 308570;
+			return 308571;
 		case CDCLK_FREQ_540:
 			return 540000;
 		case CDCLK_FREQ_675_617:
-			return 617140;
+			return 617143;
 		default:
 			MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 		}
-- 
2.7.4

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[PATCH 13/21] drm/i915: Rename skl_vco_freq to cdclk_pll.vco

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We'll want to store the cdclk PLL (whatever PLL that is in reality) vco
frequency somewhere on other platforms too, so let's rename the
skl_vco_freq to cdclk_pll.vco, and let's store it in kHz instead of MHz
to match most of the other clocks.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  5 +++-
 drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++------------------
 drivers/gpu/drm/i915/intel_dp.c      |  4 +--
 3 files changed, 31 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 46a22732088e..8da787cd2227 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1820,7 +1820,6 @@ struct drm_i915_private {
 	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 
 	unsigned int fsb_freq, mem_freq, is_ddr3;
-	unsigned int skl_vco_freq;
 	unsigned int skl_preferred_vco_freq;
 	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
 	unsigned int max_dotclk_freq;
@@ -1828,6 +1827,10 @@ struct drm_i915_private {
 	unsigned int hpll_freq;
 	unsigned int czclk_freq;
 
+	struct {
+		unsigned int vco;
+	} cdclk_pll;
+
 	/**
 	 * wq - Driver workqueue for GEM.
 	 *
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c0dbff37e2c3..8bde3ae34869 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5276,7 +5276,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
 		int max_cdclk, vco;
 
 		vco = dev_priv->skl_preferred_vco_freq;
-		WARN_ON(vco != 8100 && vco != 8640);
+		WARN_ON(vco != 8100000 && vco != 8640000);
 
 		/*
 		 * Use the lower (vco 8640) cdclk values as a
@@ -5335,8 +5335,8 @@ static void intel_update_cdclk(struct drm_device *dev)
 	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
 
 	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
-		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d MHz\n",
-				 dev_priv->cdclk_freq, dev_priv->skl_vco_freq);
+		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz\n",
+				 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco);
 	else
 		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
 				 dev_priv->cdclk_freq);
@@ -5516,7 +5516,7 @@ void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
 
 static int skl_calc_cdclk(int max_pixclk, int vco)
 {
-	if (vco == 8640) {
+	if (vco == 8640000) {
 		if (max_pixclk > 540000)
 			return 617143;
 		else if (max_pixclk > 432000)
@@ -5526,7 +5526,6 @@ static int skl_calc_cdclk(int max_pixclk, int vco)
 		else
 			return 308571;
 	} else {
-		/* VCO 8100 */
 		if (max_pixclk > 540000)
 			return 675000;
 		else if (max_pixclk > 450000)
@@ -5545,7 +5544,7 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
 
 	val = I915_READ(LCPLL1_CTL);
 	if ((val & LCPLL_PLL_ENABLE) == 0) {
-		dev_priv->skl_vco_freq = 0;
+		dev_priv->cdclk_pll.vco = 0;
 		return;
 	}
 
@@ -5563,15 +5562,15 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
-		dev_priv->skl_vco_freq = 8100;
+		dev_priv->cdclk_pll.vco = 8100000;
 		break;
 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
-		dev_priv->skl_vco_freq = 8640;
+		dev_priv->cdclk_pll.vco = 8640000;
 		break;
 	default:
 		MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
-		dev_priv->skl_vco_freq = 0;
+		dev_priv->cdclk_pll.vco = 0;
 		break;
 	}
 }
@@ -5592,7 +5591,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 	int min_cdclk = skl_calc_cdclk(0, vco);
 	u32 val;
 
-	WARN_ON(vco != 8100 && vco != 8640);
+	WARN_ON(vco != 8100000 && vco != 8640000);
 
 	/* select the minimum CDCLK before enabling DPLL 0 */
 	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
@@ -5613,7 +5612,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 	val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 		 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 	val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
-	if (vco == 8640)
+	if (vco == 8640000)
 		val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 					    SKL_DPLL0);
 	else
@@ -5628,7 +5627,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 	if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
 		DRM_ERROR("DPLL0 not locked\n");
 
-	dev_priv->skl_vco_freq = vco;
+	dev_priv->cdclk_pll.vco = vco;
 
 	/* We'll want to keep using the current vco from now on. */
 	skl_set_preferred_cdclk_vco(dev_priv, vco);
@@ -5641,7 +5640,7 @@ skl_dpll0_disable(struct drm_i915_private *dev_priv)
 	if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
 		DRM_ERROR("Couldn't disable DPLL0\n");
 
-	dev_priv->skl_vco_freq = 0;
+	dev_priv->cdclk_pll.vco = 0;
 }
 
 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
@@ -5678,7 +5677,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
 
 	WARN_ON((cdclk == 24000) != (vco == 0));
 
-	DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d MHz)\n", cdclk, vco);
+	DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
 
 	if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
 		DRM_ERROR("failed to inform PCU about cdclk change\n");
@@ -5709,11 +5708,11 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
 		break;
 	}
 
-	if (dev_priv->skl_vco_freq != 0 &&
-	    dev_priv->skl_vco_freq != vco)
+	if (dev_priv->cdclk_pll.vco != 0 &&
+	    dev_priv->cdclk_pll.vco != vco)
 		skl_dpll0_disable(dev_priv);
 
-	if (dev_priv->skl_vco_freq != vco)
+	if (dev_priv->cdclk_pll.vco != vco)
 		skl_dpll0_enable(dev_priv, vco);
 
 	I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
@@ -5740,20 +5739,20 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
 
 	skl_sanitize_cdclk(dev_priv);
 
-	if (dev_priv->cdclk_freq != 0 && dev_priv->skl_vco_freq != 0) {
+	if (dev_priv->cdclk_freq > 0 && dev_priv->cdclk_pll.vco > 0) {
 		/*
 		 * Use the current vco as out initial
 		 * guess as to what the preferred vco is.
 		 */
 		if (dev_priv->skl_preferred_vco_freq == 0)
 			skl_set_preferred_cdclk_vco(dev_priv,
-						    dev_priv->skl_vco_freq);
+						    dev_priv->cdclk_pll.vco);
 		return;
 	}
 
 	vco = dev_priv->skl_preferred_vco_freq;
 	if (vco == 0)
-		vco = 8100;
+		vco = 8100000;
 	cdclk = skl_calc_cdclk(0, vco);
 
 	skl_set_cdclk(dev_priv, cdclk, vco);
@@ -5803,7 +5802,7 @@ sanitize:
 	/* force cdclk programming */
 	dev_priv->cdclk_freq = 0;
 	/* force full PLL disable + enable */
-	dev_priv->skl_vco_freq = -1;
+	dev_priv->cdclk_pll.vco = -1;
 }
 
 /* Adjust CDclk dividers to allow high res or save power if possible */
@@ -6646,12 +6645,12 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
 
 	skl_dpll0_update(dev_priv);
 
-	if (dev_priv->skl_vco_freq == 0)
+	if (dev_priv->cdclk_pll.vco == 0)
 		return 24000; /* 24MHz is the cd freq with NSSC ref */
 
 	cdctl = I915_READ(CDCLK_CTL);
 
-	if (dev_priv->skl_vco_freq == 8640) {
+	if (dev_priv->cdclk_pll.vco == 8640000) {
 		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 		case CDCLK_FREQ_450_432:
 			return 432000;
@@ -13369,7 +13368,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
 	 */
 	if (dev_priv->display.modeset_calc_cdclk) {
 		if (!intel_state->cdclk_pll_vco)
-			intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
+			intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
 		if (!intel_state->cdclk_pll_vco)
 			intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
 
@@ -13378,7 +13377,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
 			return ret;
 
 		if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
-		    intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
+		    intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
 			ret = intel_modeset_all_pipes(state);
 
 		if (ret < 0)
@@ -13720,7 +13719,7 @@ static int intel_atomic_commit(struct drm_device *dev,
 
 		if (dev_priv->display.modeset_commit_cdclk &&
 		    (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
-		     intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
+		     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
 			dev_priv->display.modeset_commit_cdclk(state);
 
 		intel_modeset_verify_disabled(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 908c6f0f7feb..5f9a03651649 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1588,10 +1588,10 @@ found:
 		switch (pipe_config->port_clock / 2) {
 		case 108000:
 		case 216000:
-			vco = 8640;
+			vco = 8640000;
 			break;
 		default:
-			vco = 8100;
+			vco = 8100000;
 			break;
 		}
 
-- 
2.7.4

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[PATCH 14/21] drm/i915: Store cdclk PLL reference clock under dev_priv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Future platforms will have multiple options for the cdclk PLL reference
clock, so let's start tracking that under dev_priv alreday on SKL,
although on SKL it's always 24 MHz.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  2 +-
 drivers/gpu/drm/i915/intel_display.c | 14 ++++++++------
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8da787cd2227..422f219450c1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1828,7 +1828,7 @@ struct drm_i915_private {
 	unsigned int czclk_freq;
 
 	struct {
-		unsigned int vco;
+		unsigned int vco, ref;
 	} cdclk_pll;
 
 	/**
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8bde3ae34869..11e90863533b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5335,8 +5335,9 @@ static void intel_update_cdclk(struct drm_device *dev)
 	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
 
 	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
-		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz\n",
-				 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco);
+		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
+				 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
+				 dev_priv->cdclk_pll.ref);
 	else
 		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
 				 dev_priv->cdclk_freq);
@@ -5542,6 +5543,8 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
 {
 	u32 val;
 
+	dev_priv->cdclk_pll.ref = 24000;
+
 	val = I915_READ(LCPLL1_CTL);
 	if ((val & LCPLL_PLL_ENABLE) == 0) {
 		dev_priv->cdclk_pll.vco = 0;
@@ -5730,7 +5733,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
 
 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
 {
-	skl_set_cdclk(dev_priv, 24000, 0);
+	skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
 }
 
 void skl_init_cdclk(struct drm_i915_private *dev_priv)
@@ -6646,7 +6649,7 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
 	skl_dpll0_update(dev_priv);
 
 	if (dev_priv->cdclk_pll.vco == 0)
-		return 24000; /* 24MHz is the cd freq with NSSC ref */
+		return dev_priv->cdclk_pll.ref;
 
 	cdctl = I915_READ(CDCLK_CTL);
 
@@ -6678,8 +6681,7 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
 		}
 	}
 
-	/* error case, do as if DPLL0 isn't enabled */
-	return 24000;
+	return dev_priv->cdclk_pll.ref;
 }
 
 static int broxton_get_display_clock_speed(struct drm_device *dev)
-- 
2.7.4

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[PATCH 15/21] drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Enabling and disalbing the DE PLL are two nice self contained
operations, so let's move them into a few small helper functions.
Makes it easier to see the forest from the trees in broxton_set_cdclk().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 41 ++++++++++++++++++++++++------------
 1 file changed, 27 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 11e90863533b..76d59d1214f4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5358,6 +5358,31 @@ static int skl_cdclk_decimal(int cdclk)
 	return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 }
 
+static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE(BXT_DE_PLL_ENABLE, 0);
+
+	/* Timeout 200us */
+	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
+		DRM_ERROR("timeout waiting for DE PLL unlock\n");
+}
+
+static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio)
+{
+	u32 val;
+
+	val = I915_READ(BXT_DE_PLL_CTL);
+	val &= ~BXT_DE_PLL_RATIO_MASK;
+	val |= ratio;
+	I915_WRITE(BXT_DE_PLL_CTL, val);
+
+	I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
+
+	/* Timeout 200us */
+	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
+		DRM_ERROR("timeout waiting for DE PLL lock\n");
+}
+
 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
 {
 	uint32_t divider;
@@ -5425,25 +5450,13 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
 	 */
 	if (cdclk == 19200 || cdclk == 624000 ||
 	    current_cdclk == 624000) {
-		I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
-		/* Timeout 200us */
-		if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
-			     1))
-			DRM_ERROR("timout waiting for DE PLL unlock\n");
+		bxt_de_pll_disable(dev_priv);
 	}
 
 	if (cdclk != 19200) {
 		uint32_t val;
 
-		val = I915_READ(BXT_DE_PLL_CTL);
-		val &= ~BXT_DE_PLL_RATIO_MASK;
-		val |= ratio;
-		I915_WRITE(BXT_DE_PLL_CTL, val);
-
-		I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
-		/* Timeout 200us */
-		if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
-			DRM_ERROR("timeout waiting for DE PLL lock\n");
+		bxt_de_pll_enable(dev_priv, ratio);
 
 		val = divider | skl_cdclk_decimal(cdclk);
 		/*
-- 
2.7.4

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[PATCH 16/21] drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have need to know the DE PLL refclk and output frequency in various
cdclk calculations, so let's store those in dev_priv.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 76d59d1214f4..0d55e8175573 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5334,7 +5334,7 @@ static void intel_update_cdclk(struct drm_device *dev)
 
 	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
 
-	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) >= 9)
 		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
 				 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
 				 dev_priv->cdclk_pll.ref);
@@ -5365,6 +5365,8 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
 	/* Timeout 200us */
 	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
 		DRM_ERROR("timeout waiting for DE PLL unlock\n");
+
+	dev_priv->cdclk_pll.vco = 0;
 }
 
 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio)
@@ -5381,6 +5383,8 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio)
 	/* Timeout 200us */
 	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
 		DRM_ERROR("timeout waiting for DE PLL lock\n");
+
+	dev_priv->cdclk_pll.vco = ratio * dev_priv->cdclk_pll.ref;
 }
 
 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
@@ -6697,6 +6701,25 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
 	return dev_priv->cdclk_pll.ref;
 }
 
+static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+
+	dev_priv->cdclk_pll.ref = 19200;
+
+	val = I915_READ(BXT_DE_PLL_ENABLE);
+	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) {
+		dev_priv->cdclk_pll.vco = 0;
+		return;
+	}
+
+	WARN_ON((val & BXT_DE_PLL_LOCK) == 0);
+
+	val = I915_READ(BXT_DE_PLL_CTL);
+	dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
+		dev_priv->cdclk_pll.ref;
+}
+
 static int broxton_get_display_clock_speed(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -6705,6 +6728,8 @@ static int broxton_get_display_clock_speed(struct drm_device *dev)
 	uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
 	int cdclk;
 
+	bxt_de_pll_update(dev_priv);
+
 	if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
 		return 19200;
 
-- 
2.7.4

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[PATCH 17/21] drm/i915: Update cached cdclk state from broxton_init_cdclk()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's make sure our cached cdclk state is accurate right after
broxton_init_cdclk() whether or not we end up changing the cdclk
frequency.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0d55e8175573..834373503a8d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5508,13 +5508,10 @@ bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
 
 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
 {
-	/* check if cd clock is enabled */
-	if (broxton_cdclk_is_enabled(dev_priv)) {
-		DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
-		return;
-	}
+	intel_update_cdclk(dev_priv->dev);
 
-	DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
+	if (dev_priv->cdclk_pll.vco != 0)
+		return;
 
 	/*
 	 * FIXME:
-- 
2.7.4

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[PATCH 18/21] drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE PLL vco/refclk

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that we've read out the DE PLL vco and refclk, we can just use them
in the cdclk calculation. While at it switch over to
DIV_ROUND_CLOSEST().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++--------------
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 834373503a8d..4542c1f5012f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6720,31 +6720,36 @@ static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
 static int broxton_get_display_clock_speed(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	uint32_t cdctl = I915_READ(CDCLK_CTL);
-	uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
-	uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
-	int cdclk;
+	u32 divider;
+	int div, vco;
 
 	bxt_de_pll_update(dev_priv);
 
-	if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
-		return 19200;
+	vco = dev_priv->cdclk_pll.vco;
+	if (vco == 0)
+		return dev_priv->cdclk_pll.ref;
 
-	cdclk = 19200 * pll_ratio / 2;
+	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
 
-	switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
+	switch (divider) {
 	case BXT_CDCLK_CD2X_DIV_SEL_1:
-		return cdclk;  /* 576MHz or 624MHz */
+		div = 2;
+		break;
 	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
-		return cdclk * 2 / 3; /* 384MHz */
+		div = 3;
+		break;
 	case BXT_CDCLK_CD2X_DIV_SEL_2:
-		return cdclk / 2; /* 288MHz */
+		div = 4;
+		break;
 	case BXT_CDCLK_CD2X_DIV_SEL_4:
-		return cdclk / 4; /* 144MHz */
+		div = 8;
+		break;
+	default:
+		MISSING_CASE(divider);
+		return dev_priv->cdclk_pll.ref;
 	}
 
-	/* error case, do as if DE PLL isn't enabled */
-	return 19200;
+	return DIV_ROUND_CLOSEST(vco, div);
 }
 
 static int broadwell_get_display_clock_speed(struct drm_device *dev)
-- 
2.7.4

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[PATCH 19/21] drm/i915: Make bxt_set_cdclk() operate in terms of the current vs target DE PLL vco

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make bxt_set_cdclk() more readable by looking at current vs. target
DE PLL vco to determine if the DE PLL needs disabling and/or enabling.
We can also calculate the CD2X divider simply as (vco/cdclk) instead of
depending on magic numbers.

The magic numbers are still needed though, but only to map the supported
cdclk frequencies to corresponding DE PLL frequencies.

Note that w'll now program CDCLK_CTL correctly even for the bypass case.
Actually the CD2X divider should not matter in that case since the
hardware will bypass it too, but the "decimal" part should matter (if we
want to do gmbus/aux with the bypass enabled).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 128 +++++++++++++++++------------------
 1 file changed, 63 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4542c1f5012f..14bc14c7827b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5358,6 +5358,30 @@ static int skl_cdclk_decimal(int cdclk)
 	return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 }
 
+static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
+{
+	int ratio;
+
+	if (cdclk == dev_priv->cdclk_pll.ref)
+		return 0;
+
+	switch (cdclk) {
+	default:
+		MISSING_CASE(cdclk);
+	case 144000:
+	case 288000:
+	case 384000:
+	case 576000:
+		ratio = 60;
+		break;
+	case 624000:
+		ratio = 65;
+		break;
+	}
+
+	return dev_priv->cdclk_pll.ref * ratio;
+}
+
 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(BXT_DE_PLL_ENABLE, 0);
@@ -5369,13 +5393,14 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
 	dev_priv->cdclk_pll.vco = 0;
 }
 
-static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio)
+static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
 {
+	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
 	u32 val;
 
 	val = I915_READ(BXT_DE_PLL_CTL);
 	val &= ~BXT_DE_PLL_RATIO_MASK;
-	val |= ratio;
+	val |= BXT_DE_PLL_RATIO(ratio);
 	I915_WRITE(BXT_DE_PLL_CTL, val);
 
 	I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
@@ -5384,54 +5409,42 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio)
 	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
 		DRM_ERROR("timeout waiting for DE PLL lock\n");
 
-	dev_priv->cdclk_pll.vco = ratio * dev_priv->cdclk_pll.ref;
+	dev_priv->cdclk_pll.vco = vco;
 }
 
 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
 {
-	uint32_t divider;
-	uint32_t ratio;
-	uint32_t current_cdclk;
-	int ret;
+	u32 val, divider;
+	int vco, ret;
 
-	/* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
-	switch (cdclk) {
-	case 144000:
+	vco = bxt_de_pll_vco(dev_priv, cdclk);
+
+	DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
+
+	/* cdclk = vco / 2 / div{1,1.5,2,4} */
+	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
+	case 8:
 		divider = BXT_CDCLK_CD2X_DIV_SEL_4;
-		ratio = BXT_DE_PLL_RATIO(60);
 		break;
-	case 288000:
+	case 4:
 		divider = BXT_CDCLK_CD2X_DIV_SEL_2;
-		ratio = BXT_DE_PLL_RATIO(60);
 		break;
-	case 384000:
+	case 3:
 		divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
-		ratio = BXT_DE_PLL_RATIO(60);
-		break;
-	case 576000:
-		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
-		ratio = BXT_DE_PLL_RATIO(60);
 		break;
-	case 624000:
+	case 2:
 		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
-		ratio = BXT_DE_PLL_RATIO(65);
-		break;
-	case 19200:
-		/*
-		 * Bypass frequency with DE PLL disabled. Init ratio, divider
-		 * to suppress GCC warning.
-		 */
-		ratio = 0;
-		divider = 0;
 		break;
 	default:
-		DRM_ERROR("unsupported CDCLK freq %d", cdclk);
+		WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
+		WARN_ON(vco != 0);
 
-		return;
+		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
+		break;
 	}
 
-	mutex_lock(&dev_priv->rps.hw_lock);
 	/* Inform power controller of upcoming frequency change */
+	mutex_lock(&dev_priv->rps.hw_lock);
 	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
 				      0x80000000);
 	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -5442,40 +5455,26 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
 		return;
 	}
 
-	current_cdclk = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
-	/* convert from .1 fixpoint MHz with -1MHz offset to kHz */
-	current_cdclk = current_cdclk * 500 + 1000;
-
-	/*
-	 * DE PLL has to be disabled when
-	 * - setting to 19.2MHz (bypass, PLL isn't used)
-	 * - before setting to 624MHz (PLL needs toggling)
-	 * - before setting to any frequency from 624MHz (PLL needs toggling)
-	 */
-	if (cdclk == 19200 || cdclk == 624000 ||
-	    current_cdclk == 624000) {
+	if (dev_priv->cdclk_pll.vco != 0 &&
+	    dev_priv->cdclk_pll.vco != vco)
 		bxt_de_pll_disable(dev_priv);
-	}
-
-	if (cdclk != 19200) {
-		uint32_t val;
 
-		bxt_de_pll_enable(dev_priv, ratio);
+	if (dev_priv->cdclk_pll.vco != vco)
+		bxt_de_pll_enable(dev_priv, vco);
 
-		val = divider | skl_cdclk_decimal(cdclk);
-		/*
-		 * FIXME if only the cd2x divider needs changing, it could be done
-		 * without shutting off the pipe (if only one pipe is active).
-		 */
-		val |= BXT_CDCLK_CD2X_PIPE_NONE;
-		/*
-		 * Disable SSA Precharge when CD clock frequency < 500 MHz,
-		 * enable otherwise.
-		 */
-		if (cdclk >= 500000)
-			val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
-		I915_WRITE(CDCLK_CTL, val);
-	}
+	val = divider | skl_cdclk_decimal(cdclk);
+	/*
+	 * FIXME if only the cd2x divider needs changing, it could be done
+	 * without shutting off the pipe (if only one pipe is active).
+	 */
+	val |= BXT_CDCLK_CD2X_PIPE_NONE;
+	/*
+	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
+	 * enable otherwise.
+	 */
+	if (cdclk >= 500000)
+		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+	I915_WRITE(CDCLK_CTL, val);
 
 	mutex_lock(&dev_priv->rps.hw_lock);
 	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
@@ -5525,8 +5524,7 @@ void broxton_init_cdclk(struct drm_i915_private *dev_priv)
 
 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
 {
-	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
-	broxton_set_cdclk(dev_priv, 19200);
+	broxton_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
 }
 
 static int skl_calc_cdclk(int max_pixclk, int vco)
-- 
2.7.4

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[PATCH 20/21] drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk check

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rather than having a BXT specific function to make sure the DE PLL is
enabled after disabling DC6, let's just make sure the current cdclk
is the same as what we last programmed.

Having another check in bxt_display_core_init() almost immediately after
the cdclk init seems redundant, so let's just kill that one.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c    | 15 ---------------
 drivers/gpu/drm/i915/intel_drv.h        |  1 -
 drivers/gpu/drm/i915/intel_runtime_pm.c |  8 ++++----
 3 files changed, 4 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 14bc14c7827b..9725ba59716e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5490,21 +5490,6 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
 	intel_update_cdclk(dev_priv->dev);
 }
 
-static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
-{
-	if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
-		return false;
-
-	/* TODO: Check for a valid CDCLK rate */
-
-	return true;
-}
-
-bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
-{
-	return broxton_cdclk_is_enabled(dev_priv);
-}
-
 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
 {
 	intel_update_cdclk(dev_priv->dev);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 319e52278d1f..f1f4bde4108d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1270,7 +1270,6 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void broxton_init_cdclk(struct drm_i915_private *dev_priv);
 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
-bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv);
 void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
 void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
 void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6817a3cb5fbc..b70e123f67ca 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -811,10 +811,11 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 {
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
-	if (IS_BROXTON(dev_priv)) {
-		broxton_cdclk_verify_state(dev_priv);
+	WARN_ON(dev_priv->cdclk_freq !=
+		dev_priv->display.get_display_clock_speed(dev_priv->dev));
+
+	if (IS_BROXTON(dev_priv))
 		broxton_ddi_phy_verify_state(dev_priv);
-	}
 }
 
 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
@@ -2288,7 +2289,6 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
 
 	broxton_ddi_phy_init(dev_priv);
 
-	broxton_cdclk_verify_state(dev_priv);
 	broxton_ddi_phy_verify_state(dev_priv);
 
 	if (resume && dev_priv->csr.dmc_payload)
-- 
2.7.4

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[PATCH 21/21] drm/i915: Set BXT cdclk to minimum initially

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In case the driver is initialized without active displays, we should
just drop the cdclk to the minimum frequency right off the bat. There
might not be a modeset to drop it to the minimum late rafter all.

With DMC supposedly we should always have the cdclk up and running.
The DMC will shut the DE PLL down when appropriate, so let's nuke
the related FIXMEs as well. Trying to do anything different would
go against the expectations of the DMC firmware, and we all know
how fragile the DMC firmware is.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9725ba59716e..ac8d448e96d1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -118,6 +118,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc);
 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
+static int broxton_calc_cdclk(int max_pixclk);
 
 struct intel_limit {
 	struct {
@@ -5501,10 +5502,8 @@ void broxton_init_cdclk(struct drm_i915_private *dev_priv)
 	 * FIXME:
 	 * - The initial CDCLK needs to be read from VBT.
 	 *   Need to make this change after VBT has changes for BXT.
-	 * - check if setting the max (or any) cdclk freq is really necessary
-	 *   here, it belongs to modeset time
 	 */
-	broxton_set_cdclk(dev_priv, 624000);
+	broxton_set_cdclk(dev_priv, broxton_calc_cdclk(0));
 }
 
 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
@@ -5944,10 +5943,6 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
 
 static int broxton_calc_cdclk(int max_pixclk)
 {
-	/*
-	 * FIXME:
-	 * - set 19.2MHz bypass frequency if there are no active pipes
-	 */
 	if (max_pixclk > 576000)
 		return 624000;
 	else if (max_pixclk > 384000)
-- 
2.7.4

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✗ Ro.CI.BAT: failure for drm/i915: SKL/KBL/BXT cdclk stuff

[Patchwork]

== Series Details ==

Series: drm/i915: SKL/KBL/BXT cdclk stuff
URL   : https://patchwork.freedesktop.org/series/7169/
State : failure

== Summary ==

Series 7169v1 drm/i915: SKL/KBL/BXT cdclk stuff
http://patchwork.freedesktop.org/api/1.0/series/7169/revisions/1/mbox

Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-cmd:
                fail       -> PASS       (ro-byt-n2820)
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                pass       -> FAIL       (ro-hsw-i3-4010u)
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-a:
                pass       -> DMESG-WARN (ro-ivb2-i7-3770)

ro-bdw-i5-5250u  total:219  pass:181  dwarn:0   dfail:0   fail:0   skip:38 
ro-bdw-i7-5557U  total:219  pass:206  dwarn:0   dfail:0   fail:0   skip:13 
ro-bdw-i7-5600u  total:219  pass:187  dwarn:0   dfail:0   fail:0   skip:32 
ro-bsw-n3050     total:219  pass:175  dwarn:0   dfail:0   fail:2   skip:42 
ro-byt-n2820     total:218  pass:175  dwarn:0   dfail:0   fail:2   skip:41 
ro-hsw-i3-4010u  total:218  pass:192  dwarn:0   dfail:0   fail:1   skip:25 
ro-hsw-i7-4770r  total:219  pass:194  dwarn:0   dfail:0   fail:0   skip:25 
ro-ilk-i7-620lm  total:219  pass:151  dwarn:0   dfail:0   fail:1   skip:67 
ro-ilk1-i5-650   total:214  pass:152  dwarn:0   dfail:0   fail:1   skip:61 
ro-ivb2-i7-3770  total:219  pass:186  dwarn:1   dfail:0   fail:0   skip:32 
ro-skl-i7-6700hq total:214  pass:190  dwarn:0   dfail:0   fail:0   skip:24 
ro-snb-i7-2620M  total:219  pass:177  dwarn:0   dfail:0   fail:1   skip:41 
ro-ivb-i7-3770 failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_900/

1a536db drm-intel-nightly: 2016y-05m-13d-21h-21m-06s UTC integration manifest
b974b6b drm/i915: Set BXT cdclk to minimum initially
c75fe510 drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk check
ef3fb6c drm/i915: Make bxt_set_cdclk() operate in terms of the current vs target DE PLL vco
b8ee27d drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE PLL vco/refclk
77095f2 drm/i915: Update cached cdclk state from broxton_init_cdclk()
7c27fe0 drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv
351a2e3 drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk()
dabb9dd drm/i915: Store cdclk PLL reference clock under dev_priv
995467c drm/i915: Rename skl_vco_freq to cdclk_pll.vco
19f5564 drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL
3499324 drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit
75083d8 drm/i915: Unify SKL cdclk init paths
0b482fa drm/i915: Beef up skl_sanitize_cdclk() a bit
5fe223b drm/i915: Keep track of preferred cdclk vco frequency on SKL
b878f36 drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL
8fbef2c drm/i915: Report the current DPLL0 vco on SKL/KBL
244d5cc drm/i915: Actually read out DPLL0 vco on skl from hardware
7d03efe drm/i915: Extract skl_calc_cdclk()
e2cd537 drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config()
732fab3 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
e53fa8e drm/i915: Fix BXT min_pixclk after state readout

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[PATCH 22/21] drm/i915: Assert the dbuf is enabled when disabling DC5/6

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Like with cdclk, the DMC is supposed to manage dbuf enabling/disabling.
Let's make sure it has correctly restored the dbuf state to enabled
when we disable the DC states.

Cc: Imre Deak <imre.deak@intel.com>
Suggested-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b70e123f67ca..27cb92c18bb5 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -806,6 +806,15 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 	return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 }
 
+static void skl_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
+{
+	u32 tmp = I915_READ(DBUF_CTL);
+
+	WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
+	     (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
+	     "Unexpected DBuf power power state (0x%08x)\n", tmp);
+}
+
 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 					  struct i915_power_well *power_well)
 {
@@ -814,6 +823,8 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 	WARN_ON(dev_priv->cdclk_freq !=
 		dev_priv->display.get_display_clock_speed(dev_priv->dev));
 
+	skl_assert_dbuf_enabled(dev_priv);
+
 	if (IS_BROXTON(dev_priv))
 		broxton_ddi_phy_verify_state(dev_priv);
 }
-- 
2.7.4

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Re: [PATCH 01/21] drm/i915: Fix BXT min_pixclk after state readout

[Imre Deak]

On Fri, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> commit 4e5ca60fd35a ("drm/i915: Use ilk_max_pixel_rate() for BXT cdclk calculation")
> tried to change BXT to use ilk_max_pixel_rate() to compute the
> pipe pixel rate. I failed to notice that there was another place
> in the state readout code that needs the same treatment. So let's
> change that one too.
> 
> Should probably just change things to always compuyte the pipe pixel
> rates, instead of just doing on platforms that can change cdclk
> dynamically. But for now let's just move BXT fully over to the
> side that uses ilk_pipe_pixel_rate().
> 
> Cc: Jani Nikula <jani.nikula@intel.com>
> Fixes: 4e5ca60fd35a ("drm/i915: Use ilk_max_pixel_rate() for BXT cdclk calculation")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

Btw, there is also skl_pipe_pixel_rate() that needs the same change.

> ---
>  drivers/gpu/drm/i915/intel_display.c | 14 ++++++--------
>  1 file changed, 6 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c5f0a6f30879..cc9a8b42fbc6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15748,18 +15748,16 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  		if (crtc_state->base.active) {
>  			dev_priv->active_crtcs |= 1 << crtc->pipe;
>  
> -			if (IS_BROADWELL(dev_priv)) {
> +			if (IS_BROXTON(dev_priv) || IS_BROADWELL(dev_priv))
>  				pixclk = ilk_pipe_pixel_rate(crtc_state);
> -
> -				/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> -				if (crtc_state->ips_enabled)
> -					pixclk = DIV_ROUND_UP(pixclk * 100, 95);
> -			} else if (IS_VALLEYVIEW(dev_priv) ||
> -				   IS_CHERRYVIEW(dev_priv) ||
> -				   IS_BROXTON(dev_priv))
> +			else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  				pixclk = crtc_state->base.adjusted_mode.crtc_clock;
>  			else
>  				WARN_ON(dev_priv->display.modeset_calc_cdclk);
> +
> +			/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> +			if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
> +				pixclk = DIV_ROUND_UP(pixclk * 100, 95);
>  		}
>  
>  		dev_priv->min_pixclk[crtc->pipe] = pixclk;
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Re: [PATCH 01/21] drm/i915: Fix BXT min_pixclk after state readout

[Ville Syrjälä]

On Tue, May 17, 2016 at 09:09:15PM +0300, Imre Deak wrote:
> On Fri, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > commit 4e5ca60fd35a ("drm/i915: Use ilk_max_pixel_rate() for BXT cdclk calculation")
> > tried to change BXT to use ilk_max_pixel_rate() to compute the
> > pipe pixel rate. I failed to notice that there was another place
> > in the state readout code that needs the same treatment. So let's
> > change that one too.
> > 
> > Should probably just change things to always compuyte the pipe pixel
> > rates, instead of just doing on platforms that can change cdclk
> > dynamically. But for now let's just move BXT fully over to the
> > side that uses ilk_pipe_pixel_rate().
> > 
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Fixes: 4e5ca60fd35a ("drm/i915: Use ilk_max_pixel_rate() for BXT cdclk calculation")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> Btw, there is also skl_pipe_pixel_rate() that needs the same change.

Oh dear. Just how many of these things do we need? I'll send a patch to just
nuke the skl version.

> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 14 ++++++--------
> >  1 file changed, 6 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index c5f0a6f30879..cc9a8b42fbc6 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15748,18 +15748,16 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> >  		if (crtc_state->base.active) {
> >  			dev_priv->active_crtcs |= 1 << crtc->pipe;
> >  
> > -			if (IS_BROADWELL(dev_priv)) {
> > +			if (IS_BROXTON(dev_priv) || IS_BROADWELL(dev_priv))
> >  				pixclk = ilk_pipe_pixel_rate(crtc_state);
> > -
> > -				/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> > -				if (crtc_state->ips_enabled)
> > -					pixclk = DIV_ROUND_UP(pixclk * 100, 95);
> > -			} else if (IS_VALLEYVIEW(dev_priv) ||
> > -				   IS_CHERRYVIEW(dev_priv) ||
> > -				   IS_BROXTON(dev_priv))
> > +			else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> >  				pixclk = crtc_state->base.adjusted_mode.crtc_clock;
> >  			else
> >  				WARN_ON(dev_priv->display.modeset_calc_cdclk);
> > +
> > +			/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> > +			if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
> > +				pixclk = DIV_ROUND_UP(pixclk * 100, 95);
> >  		}
> >  
> >  		dev_priv->min_pixclk[crtc->pipe] = pixclk;

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 01/21] drm/i915: Fix BXT min_pixclk after state readout

[Imre Deak]

On Tue, 2016-05-17 at 21:21 +0300, Ville Syrjälä wrote:
> On Tue, May 17, 2016 at 09:09:15PM +0300, Imre Deak wrote:
> > On Fri, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > commit 4e5ca60fd35a ("drm/i915: Use ilk_max_pixel_rate() for BXT
> > > cdclk calculation")
> > > tried to change BXT to use ilk_max_pixel_rate() to compute the
> > > pipe pixel rate. I failed to notice that there was another place
> > > in the state readout code that needs the same treatment. So let's
> > > change that one too.
> > > 
> > > Should probably just change things to always compuyte the pipe
> > > pixel
> > > rates, instead of just doing on platforms that can change cdclk
> > > dynamically. But for now let's just move BXT fully over to the
> > > side that uses ilk_pipe_pixel_rate().
> > > 
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > Fixes: 4e5ca60fd35a ("drm/i915: Use ilk_max_pixel_rate() for BXT
> > > cdclk calculation")
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > 
> > Btw, there is also skl_pipe_pixel_rate() that needs the same
> > change.
> 
> Oh dear. Just how many of these things do we need? I'll send a patch
> to just
> nuke the skl version.

Ohm, I guess I was wrong. For WM we only need to adjust for pipe
scaling not plane scaling if I read the spec correctly. But removing
duplicate helpers if possible doesn't hurt in any case.

> > 
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c | 14 ++++++--------
> > >  1 file changed, 6 insertions(+), 8 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index c5f0a6f30879..cc9a8b42fbc6 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -15748,18 +15748,16 @@ static void
> > > intel_modeset_readout_hw_state(struct drm_device *dev)
> > >  		if (crtc_state->base.active) {
> > >  			dev_priv->active_crtcs |= 1 << crtc-
> > > >pipe;
> > >  
> > > -			if (IS_BROADWELL(dev_priv)) {
> > > +			if (IS_BROXTON(dev_priv) ||
> > > IS_BROADWELL(dev_priv))
> > >  				pixclk =
> > > ilk_pipe_pixel_rate(crtc_state);
> > > -
> > > -				/* pixel rate mustn't exceed 95%
> > > of cdclk with IPS on BDW */
> > > -				if (crtc_state->ips_enabled)
> > > -					pixclk =
> > > DIV_ROUND_UP(pixclk * 100, 95);
> > > -			} else if (IS_VALLEYVIEW(dev_priv) ||
> > > -				   IS_CHERRYVIEW(dev_priv) ||
> > > -				   IS_BROXTON(dev_priv))
> > > +			else if (IS_VALLEYVIEW(dev_priv) ||
> > > IS_CHERRYVIEW(dev_priv))
> > >  				pixclk = crtc_state-
> > > >base.adjusted_mode.crtc_clock;
> > >  			else
> > >  				WARN_ON(dev_priv-
> > > >display.modeset_calc_cdclk);
> > > +
> > > +			/* pixel rate mustn't exceed 95% of
> > > cdclk with IPS on BDW */
> > > +			if (IS_BROADWELL(dev_priv) &&
> > > crtc_state->ips_enabled)
> > > +				pixclk = DIV_ROUND_UP(pixclk *
> > > 100, 95);
> > >  		}
> > >  
> > >  		dev_priv->min_pixclk[crtc->pipe] = pixclk;
> 
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Re: [PATCH 02/21] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
> 
> WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
> to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
> is enabled when the cdclk is less then required. DP connected to DDI2
> and HPD on either port works correctly.
> 
> Set cdclk based on the max required pixel clock based on VCO
> selected. Track boot vco instead of boot cdclk.
> 
> The vco is now tracked at the atomic level and all CRTCs updated if
> the required vco is changed. Not tested with eDP v1.4 panels that
> require 8640 vco due to availability.
> 
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
> V4: track target vco is atomic state. modeset all CRTCs if vco changes
> V5: rename atomic variable, cleaner if/else logic, use existing vco if
>       encoder does not return a new vco value. check_patch.pl cleanup
> V6: simplify logic in intel_modeset_checks.
> V7: reorder an IF for readability and whitespace fix.
> V8: use dev_cdclk for tracking new cdclk during atomic
> V9: correctly handle vco 8640 when crtcs==0
> V10: Clean up if else in crtcs==0
> V11: Rebase for new intel_dpll_mgr.c
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> [vsyrjala: rebased due to churn]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

It has R-b already, but since I went through it in any case:
Reviewed-by: Imre Deak <imre.deak@intel.com>

A few notes below, none of them are about actual problems.

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |   2 +-
>  drivers/gpu/drm/i915/intel_display.c  | 109 +++++++++++++++++++++++++++++-----
>  drivers/gpu/drm/i915/intel_dpll_mgr.c |   9 +--
>  drivers/gpu/drm/i915/intel_drv.h      |   4 ++
>  4 files changed, 104 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1ba614193cc9..b319da970c8a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1820,7 +1820,7 @@ struct drm_i915_private {
>  	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>  
>  	unsigned int fsb_freq, mem_freq, is_ddr3;
> -	unsigned int skl_boot_cdclk;
> +	unsigned int skl_vco_freq;
>  	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
>  	unsigned int max_dotclk_freq;
>  	unsigned int rawclk_freq;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index cc9a8b42fbc6..41fe18c4b761 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5540,7 +5540,7 @@ static const struct skl_cdclk_entry {
>  	{ .freq = 675000, .vco = 8100 },
>  };
>  
> -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> +unsigned int skl_cdclk_get_vco(unsigned int freq)
>  {
>  	unsigned int i;
>  
> @@ -5698,17 +5698,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>  
>  void skl_init_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	unsigned int vco;
> +	unsigned int cdclk;
>  
>  	/* DPLL0 not enabled (happens on early BIOS versions) */
>  	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
>  		/* enable DPLL0 */
> -		vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> -		skl_dpll0_enable(dev_priv, vco);
> +		if (dev_priv->skl_vco_freq != 8640)
> +			dev_priv->skl_vco_freq = 8100;

This seems redundant, VCO can only be either of the above two, but you
change/fix this later in the series, so it's ok.

> +		skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> +		cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
> +	} else {
> +		cdclk = dev_priv->cdclk_freq;
>  	}
>  
> -	/* set CDCLK to the frequency the BIOS chose */
> -	skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> +	/* set CDCLK to the lowest frequency, Modeset follows */
> +	skl_set_cdclk(dev_priv, cdclk);
>  
>  	/* enable DBUF power */
>  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> @@ -5724,7 +5728,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
>  	uint32_t cdctl = I915_READ(CDCLK_CTL);
> -	int freq = dev_priv->skl_boot_cdclk;
> +	int freq = dev_priv->cdclk_freq;
>  
>  	/*
>  	 * check if the pre-os intialized the display
> @@ -5748,11 +5752,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  		/* All well; nothing to sanitize */
>  		return false;
>  sanitize:
> -	/*
> -	 * As of now initialize with max cdclk till
> -	 * we get dynamic cdclk support
> -	 * */
> -	dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> +
>  	skl_init_cdclk(dev_priv);
>  
>  	/* we did have to sanitize */
> @@ -9719,6 +9719,73 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
>  	broadwell_set_cdclk(dev, req_cdclk);
>  }
>  
> +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> +{
> +	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> +	struct drm_i915_private *dev_priv = to_i915(state->dev);
> +	const int max_pixclk = ilk_max_pixel_rate(state);
> +	int cdclk;
> +
> +	/*
> +	 * FIXME should also account for plane ratio
> +	 * once 64bpp pixel formats are supported.
> +	 */
> +
> +	if (intel_state->cdclk_pll_vco == 8640) {
> +		/* vco 8640 */
> +		if (max_pixclk > 540000)
> +			cdclk = 617140;
> +		else if (max_pixclk > 432000)
> +			cdclk = 540000;
> +		else if (max_pixclk > 308570)
> +			cdclk = 432000;
> +		else
> +			cdclk = 308570;
> +	} else {
> +		/* VCO 8100 */
> +		if (max_pixclk > 540000)
> +			cdclk = 675000;
> +		else if (max_pixclk > 450000)
> +			cdclk = 540000;
> +		else if (max_pixclk > 337500)
> +			cdclk = 450000;
> +		else
> +			cdclk = 337500;
> +	}
> +
> +	/*
> +	 * FIXME move the cdclk caclulation to
> +	 * compute_config() so we can fail gracegully.
> +	 */
> +	if (cdclk > dev_priv->max_cdclk_freq) {
> +		DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> +			  cdclk, dev_priv->max_cdclk_freq);
> +		cdclk = dev_priv->max_cdclk_freq;
> +	}
> +
> +	intel_state->cdclk = intel_state->dev_cdclk = cdclk;
> +	if (!intel_state->active_crtcs)
> +		intel_state->dev_cdclk = ((intel_state->cdclk_pll_vco == 8640) ?
> +					   308570 : 337500);
> +
> +
> +	return 0;
> +}
> +
> +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> +{
> +	struct drm_device *dev = old_state->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
> +
> +	/*
> +	 * FIXME disable/enable PLL should wrap set_cdclk()
> +	 */
> +	skl_set_cdclk(dev_priv, req_cdclk);
> +
> +	dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
> +}
> +
>  static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
>  				      struct intel_crtc_state *crtc_state)
>  {
> @@ -13283,9 +13350,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>  	 * adjusted_mode bits in the crtc directly.
>  	 */
>  	if (dev_priv->display.modeset_calc_cdclk) {
> +		if (!intel_state->cdclk_pll_vco)
> +			intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
> +
>  		ret = dev_priv->display.modeset_calc_cdclk(state);
> +		if (ret < 0)
> +			return ret;
>  
> -		if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
> +		if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> +		    intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
>  			ret = intel_modeset_all_pipes(state);
>  
>  		if (ret < 0)
> @@ -13626,7 +13699,8 @@ static int intel_atomic_commit(struct drm_device *dev,
>  		drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
>  
>  		if (dev_priv->display.modeset_commit_cdclk &&
> -		    intel_state->dev_cdclk != dev_priv->cdclk_freq)
> +		    (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> +		     intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
>  			dev_priv->display.modeset_commit_cdclk(state);
>  
>  		intel_modeset_verify_disabled(dev);
> @@ -15041,6 +15115,11 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>  			broxton_modeset_commit_cdclk;
>  		dev_priv->display.modeset_calc_cdclk =
>  			broxton_modeset_calc_cdclk;
> +	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> +		dev_priv->display.modeset_commit_cdclk =
> +			skl_modeset_commit_cdclk;
> +		dev_priv->display.modeset_calc_cdclk =
> +			skl_modeset_calc_cdclk;
>  	}
>  
>  	switch (INTEL_INFO(dev_priv)->gen) {
> @@ -15748,7 +15827,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
>  		if (crtc_state->base.active) {
>  			dev_priv->active_crtcs |= 1 << crtc->pipe;
>  
> -			if (IS_BROXTON(dev_priv) || IS_BROADWELL(dev_priv))
> +			if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
>  				pixclk = ilk_pipe_pixel_rate(crtc_state);
>  			else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  				pixclk = crtc_state->base.adjusted_mode.crtc_clock;
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index c283ba4babe8..e99e306e8743 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1194,6 +1194,7 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>  	struct intel_shared_dpll *pll;
>  	uint32_t ctrl1, cfgcr1, cfgcr2;
>  	int clock = crtc_state->port_clock;
> +	uint32_t vco = 8100;
>  
>  	/*
>  	 * See comment in intel_dpll_hw_state to understand why we always use 0
> @@ -1236,17 +1237,17 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>  		case 162000:
>  			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
>  			break;
> -		/* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
> -		results in CDCLK change. Need to handle the change of CDCLK by
> -		disabling pipes and re-enabling them */
>  		case 108000:
>  			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
> +			vco = 8640;
>  			break;
>  		case 216000:
>  			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
> +			vco = 8640;
>  			break;
>  		}
>  
> +		to_intel_atomic_state(crtc_state->base.state)->cdclk_pll_vco = vco;

If VCO was previously set to 8640 (for DPLL0) and later we'd set here
the rate for another DPLL with VCO 8100 this would incorrectly change
the CDCLK VCO to 8100. VCO isn't actually changed at this point in the
code though and you later fix this, so it's ok.

>  		cfgcr1 = cfgcr2 = 0;
>  	} else {
>  		return NULL;
> @@ -1639,7 +1640,7 @@ static void intel_ddi_pll_init(struct drm_device *dev)
>  		int cdclk_freq;
>  
>  		cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> -		dev_priv->skl_boot_cdclk = cdclk_freq;
> +		dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
>  		if (skl_sanitize_cdclk(dev_priv))
>  			DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
>  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 0dc2bc9c65cf..c7cb9829547e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -304,6 +304,9 @@ struct intel_atomic_state {
>  	unsigned int active_crtcs;
>  	unsigned int min_pixclk[I915_MAX_PIPES];
>  
> +	/* SKL/KBL Only */
> +	unsigned int cdclk_pll_vco;
> +
>  	struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
>  
>  	/*
> @@ -1277,6 +1280,7 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv);
>  void skl_init_cdclk(struct drm_i915_private *dev_priv);
>  int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
>  void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> +unsigned int skl_cdclk_get_vco(unsigned int freq);
>  void skl_enable_dc6(struct drm_i915_private *dev_priv);
>  void skl_disable_dc6(struct drm_i915_private *dev_priv);
>  void intel_dp_get_m_n(struct intel_crtc *crtc,
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Re: [PATCH 02/21] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[Ville Syrjälä]

On Thu, May 19, 2016 at 12:08:42PM +0300, Imre Deak wrote:
> On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Clint Taylor <clinton.a.taylor@intel.com>
> > 
> > WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
> > to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
> > is enabled when the cdclk is less then required. DP connected to DDI2
> > and HPD on either port works correctly.
> > 
> > Set cdclk based on the max required pixel clock based on VCO
> > selected. Track boot vco instead of boot cdclk.
> > 
> > The vco is now tracked at the atomic level and all CRTCs updated if
> > the required vco is changed. Not tested with eDP v1.4 panels that
> > require 8640 vco due to availability.
> > 
> > V1: initial version
> > V2: add vco tracking in intel_dp_compute_config(), rename
> > skl_boot_cdclk.
> > V3: rebase, V2 feedback not possible as encoders are not aware of
> > atomic.
> > V4: track target vco is atomic state. modeset all CRTCs if vco changes
> > V5: rename atomic variable, cleaner if/else logic, use existing vco if
> >       encoder does not return a new vco value. check_patch.pl cleanup
> > V6: simplify logic in intel_modeset_checks.
> > V7: reorder an IF for readability and whitespace fix.
> > V8: use dev_cdclk for tracking new cdclk during atomic
> > V9: correctly handle vco 8640 when crtcs==0
> > V10: Clean up if else in crtcs==0
> > V11: Rebase for new intel_dpll_mgr.c
> > 
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > [vsyrjala: rebased due to churn]
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> It has R-b already, but since I went through it in any case:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> A few notes below, none of them are about actual problems.
> 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h       |   2 +-
> >  drivers/gpu/drm/i915/intel_display.c  | 109 +++++++++++++++++++++++++++++-----
> >  drivers/gpu/drm/i915/intel_dpll_mgr.c |   9 +--
> >  drivers/gpu/drm/i915/intel_drv.h      |   4 ++
> >  4 files changed, 104 insertions(+), 20 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 1ba614193cc9..b319da970c8a 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1820,7 +1820,7 @@ struct drm_i915_private {
> >  	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
> >  
> >  	unsigned int fsb_freq, mem_freq, is_ddr3;
> > -	unsigned int skl_boot_cdclk;
> > +	unsigned int skl_vco_freq;
> >  	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> >  	unsigned int max_dotclk_freq;
> >  	unsigned int rawclk_freq;
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index cc9a8b42fbc6..41fe18c4b761 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5540,7 +5540,7 @@ static const struct skl_cdclk_entry {
> >  	{ .freq = 675000, .vco = 8100 },
> >  };
> >  
> > -static unsigned int skl_cdclk_get_vco(unsigned int freq)
> > +unsigned int skl_cdclk_get_vco(unsigned int freq)
> >  {
> >  	unsigned int i;
> >  
> > @@ -5698,17 +5698,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> >  
> >  void skl_init_cdclk(struct drm_i915_private *dev_priv)
> >  {
> > -	unsigned int vco;
> > +	unsigned int cdclk;
> >  
> >  	/* DPLL0 not enabled (happens on early BIOS versions) */
> >  	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> >  		/* enable DPLL0 */
> > -		vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
> > -		skl_dpll0_enable(dev_priv, vco);
> > +		if (dev_priv->skl_vco_freq != 8640)
> > +			dev_priv->skl_vco_freq = 8100;
> 
> This seems redundant, VCO can only be either of the above two, but you
> change/fix this later in the series, so it's ok.

It can also be 0 initially. And so we just flip a coin and pick one.

> 
> > +		skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> > +		cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
> > +	} else {
> > +		cdclk = dev_priv->cdclk_freq;
> >  	}
> >  
> > -	/* set CDCLK to the frequency the BIOS chose */
> > -	skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
> > +	/* set CDCLK to the lowest frequency, Modeset follows */
> > +	skl_set_cdclk(dev_priv, cdclk);
> >  
> >  	/* enable DBUF power */
> >  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> > @@ -5724,7 +5728,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> >  {
> >  	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> >  	uint32_t cdctl = I915_READ(CDCLK_CTL);
> > -	int freq = dev_priv->skl_boot_cdclk;
> > +	int freq = dev_priv->cdclk_freq;
> >  
> >  	/*
> >  	 * check if the pre-os intialized the display
> > @@ -5748,11 +5752,7 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> >  		/* All well; nothing to sanitize */
> >  		return false;
> >  sanitize:
> > -	/*
> > -	 * As of now initialize with max cdclk till
> > -	 * we get dynamic cdclk support
> > -	 * */
> > -	dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
> > +
> >  	skl_init_cdclk(dev_priv);
> >  
> >  	/* we did have to sanitize */
> > @@ -9719,6 +9719,73 @@ static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> >  	broadwell_set_cdclk(dev, req_cdclk);
> >  }
> >  
> > +static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> > +{
> > +	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> > +	struct drm_i915_private *dev_priv = to_i915(state->dev);
> > +	const int max_pixclk = ilk_max_pixel_rate(state);
> > +	int cdclk;
> > +
> > +	/*
> > +	 * FIXME should also account for plane ratio
> > +	 * once 64bpp pixel formats are supported.
> > +	 */
> > +
> > +	if (intel_state->cdclk_pll_vco == 8640) {
> > +		/* vco 8640 */
> > +		if (max_pixclk > 540000)
> > +			cdclk = 617140;
> > +		else if (max_pixclk > 432000)
> > +			cdclk = 540000;
> > +		else if (max_pixclk > 308570)
> > +			cdclk = 432000;
> > +		else
> > +			cdclk = 308570;
> > +	} else {
> > +		/* VCO 8100 */
> > +		if (max_pixclk > 540000)
> > +			cdclk = 675000;
> > +		else if (max_pixclk > 450000)
> > +			cdclk = 540000;
> > +		else if (max_pixclk > 337500)
> > +			cdclk = 450000;
> > +		else
> > +			cdclk = 337500;
> > +	}
> > +
> > +	/*
> > +	 * FIXME move the cdclk caclulation to
> > +	 * compute_config() so we can fail gracegully.
> > +	 */
> > +	if (cdclk > dev_priv->max_cdclk_freq) {
> > +		DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> > +			  cdclk, dev_priv->max_cdclk_freq);
> > +		cdclk = dev_priv->max_cdclk_freq;
> > +	}
> > +
> > +	intel_state->cdclk = intel_state->dev_cdclk = cdclk;
> > +	if (!intel_state->active_crtcs)
> > +		intel_state->dev_cdclk = ((intel_state->cdclk_pll_vco == 8640) ?
> > +					   308570 : 337500);
> > +
> > +
> > +	return 0;
> > +}
> > +
> > +static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> > +{
> > +	struct drm_device *dev = old_state->dev;
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
> > +
> > +	/*
> > +	 * FIXME disable/enable PLL should wrap set_cdclk()
> > +	 */
> > +	skl_set_cdclk(dev_priv, req_cdclk);
> > +
> > +	dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
> > +}
> > +
> >  static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> >  				      struct intel_crtc_state *crtc_state)
> >  {
> > @@ -13283,9 +13350,15 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> >  	 * adjusted_mode bits in the crtc directly.
> >  	 */
> >  	if (dev_priv->display.modeset_calc_cdclk) {
> > +		if (!intel_state->cdclk_pll_vco)
> > +			intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
> > +
> >  		ret = dev_priv->display.modeset_calc_cdclk(state);
> > +		if (ret < 0)
> > +			return ret;
> >  
> > -		if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
> > +		if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> > +		    intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
> >  			ret = intel_modeset_all_pipes(state);
> >  
> >  		if (ret < 0)
> > @@ -13626,7 +13699,8 @@ static int intel_atomic_commit(struct drm_device *dev,
> >  		drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
> >  
> >  		if (dev_priv->display.modeset_commit_cdclk &&
> > -		    intel_state->dev_cdclk != dev_priv->cdclk_freq)
> > +		    (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> > +		     intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
> >  			dev_priv->display.modeset_commit_cdclk(state);
> >  
> >  		intel_modeset_verify_disabled(dev);
> > @@ -15041,6 +15115,11 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> >  			broxton_modeset_commit_cdclk;
> >  		dev_priv->display.modeset_calc_cdclk =
> >  			broxton_modeset_calc_cdclk;
> > +	} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> > +		dev_priv->display.modeset_commit_cdclk =
> > +			skl_modeset_commit_cdclk;
> > +		dev_priv->display.modeset_calc_cdclk =
> > +			skl_modeset_calc_cdclk;
> >  	}
> >  
> >  	switch (INTEL_INFO(dev_priv)->gen) {
> > @@ -15748,7 +15827,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> >  		if (crtc_state->base.active) {
> >  			dev_priv->active_crtcs |= 1 << crtc->pipe;
> >  
> > -			if (IS_BROXTON(dev_priv) || IS_BROADWELL(dev_priv))
> > +			if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> >  				pixclk = ilk_pipe_pixel_rate(crtc_state);
> >  			else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> >  				pixclk = crtc_state->base.adjusted_mode.crtc_clock;
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index c283ba4babe8..e99e306e8743 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -1194,6 +1194,7 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
> >  	struct intel_shared_dpll *pll;
> >  	uint32_t ctrl1, cfgcr1, cfgcr2;
> >  	int clock = crtc_state->port_clock;
> > +	uint32_t vco = 8100;
> >  
> >  	/*
> >  	 * See comment in intel_dpll_hw_state to understand why we always use 0
> > @@ -1236,17 +1237,17 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
> >  		case 162000:
> >  			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
> >  			break;
> > -		/* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
> > -		results in CDCLK change. Need to handle the change of CDCLK by
> > -		disabling pipes and re-enabling them */
> >  		case 108000:
> >  			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
> > +			vco = 8640;
> >  			break;
> >  		case 216000:
> >  			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
> > +			vco = 8640;
> >  			break;
> >  		}
> >  
> > +		to_intel_atomic_state(crtc_state->base.state)->cdclk_pll_vco = vco;
> 
> If VCO was previously set to 8640 (for DPLL0) and later we'd set here
> the rate for another DPLL with VCO 8100 this would incorrectly change
> the CDCLK VCO to 8100. VCO isn't actually changed at this point in the
> code though and you later fix this, so it's ok.
> 
> >  		cfgcr1 = cfgcr2 = 0;
> >  	} else {
> >  		return NULL;
> > @@ -1639,7 +1640,7 @@ static void intel_ddi_pll_init(struct drm_device *dev)
> >  		int cdclk_freq;
> >  
> >  		cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> > -		dev_priv->skl_boot_cdclk = cdclk_freq;
> > +		dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
> >  		if (skl_sanitize_cdclk(dev_priv))
> >  			DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> >  		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 0dc2bc9c65cf..c7cb9829547e 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -304,6 +304,9 @@ struct intel_atomic_state {
> >  	unsigned int active_crtcs;
> >  	unsigned int min_pixclk[I915_MAX_PIPES];
> >  
> > +	/* SKL/KBL Only */
> > +	unsigned int cdclk_pll_vco;
> > +
> >  	struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
> >  
> >  	/*
> > @@ -1277,6 +1280,7 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv);
> >  void skl_init_cdclk(struct drm_i915_private *dev_priv);
> >  int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> >  void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> > +unsigned int skl_cdclk_get_vco(unsigned int freq);
> >  void skl_enable_dc6(struct drm_i915_private *dev_priv);
> >  void skl_disable_dc6(struct drm_i915_private *dev_priv);
> >  void intel_dp_get_m_n(struct intel_crtc *crtc,

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 03/21] drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config()

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Shared plls won't get assigned until the .compute_clocks() hook gets
> called, which happens from the crtc .atomic_check hook. That's too late
> as the cdclk computation has already happened. So let's move the DPLL0
> VCO computation into intel_dp_compute_config() so that it's done when
> the cdclk computation happens. Also only do it for eDP since we only
> pick DPLL0 for eDP.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c       | 21 +++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dpll_mgr.c |  4 ----
>  2 files changed, 21 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 36330026ceff..908c6f0f7feb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1577,6 +1577,27 @@ found:
>  				&pipe_config->dp_m2_n2);
>  	}
>  
> +	/*
> +	 * DPLL0 VCO may need to be adjusted to get the correct
> +	 * clock for eDP. This will affect cdclk as well.
> +	 */
> +	if (is_edp(intel_dp) &&
> +	    (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
> +		int vco;
> +
> +		switch (pipe_config->port_clock / 2) {
> +		case 108000:
> +		case 216000:
> +			vco = 8640;
> +			break;
> +		default:
> +			vco = 8100;
> +			break;
> +		}
> +
> +		to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
> +	}
> +
>  	if (!HAS_DDI(dev))
>  		intel_dp_set_clock(encoder, pipe_config);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index e99e306e8743..43ba60b3662e 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1194,7 +1194,6 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>  	struct intel_shared_dpll *pll;
>  	uint32_t ctrl1, cfgcr1, cfgcr2;
>  	int clock = crtc_state->port_clock;
> -	uint32_t vco = 8100;
>  
>  	/*
>  	 * See comment in intel_dpll_hw_state to understand why we always use 0
> @@ -1239,15 +1238,12 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>  			break;
>  		case 108000:
>  			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
> -			vco = 8640;
>  			break;
>  		case 216000:
>  			ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
> -			vco = 8640;
>  			break;
>  		}
>  
> -		to_intel_atomic_state(crtc_state->base.state)->cdclk_pll_vco = vco;
>  		cfgcr1 = cfgcr2 = 0;
>  	} else {
>  		return NULL;
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Re: [PATCH 04/21] drm/i915: Extract skl_calc_cdclk()

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We have many places where we want to pick a suitable cdclk frequency for
> skl based on the dotclock and lcpll vco. Split that code into a small
> helper and call it from all over.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 63 +++++++++++++++++-------------------
>  1 file changed, 30 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 41fe18c4b761..c1b1632664a1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5527,6 +5527,30 @@ void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
>  	broxton_set_cdclk(dev_priv, 19200);
>  }
>  
> +static int skl_calc_cdclk(int max_pixclk, int vco)
> +{
> +	if (vco == 8640) {
> +		if (max_pixclk > 540000)
> +			return 617140;
> +		else if (max_pixclk > 432000)
> +			return 540000;
> +		else if (max_pixclk > 308570)
> +			return 432000;
> +		else
> +			return 308570;
> +	} else {
> +		/* VCO 8100 */
> +		if (max_pixclk > 540000)
> +			return 675000;
> +		else if (max_pixclk > 450000)
> +			return 540000;
> +		else if (max_pixclk > 337500)
> +			return 450000;
> +		else
> +			return 337500;
> +	}
> +}
> +
>  static const struct skl_cdclk_entry {
>  	unsigned int freq;
>  	unsigned int vco;
> @@ -5557,15 +5581,10 @@ unsigned int skl_cdclk_get_vco(unsigned int freq)
>  static void
>  skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
>  {
> -	int min_cdclk;
> +	int min_cdclk = skl_calc_cdclk(0, vco);
>  	u32 val;
>  
>  	/* select the minimum CDCLK before enabling DPLL 0 */
> -	if (vco == 8640)
> -		min_cdclk = 308570;
> -	else
> -		min_cdclk = 337500;
> -
>  	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
>  	I915_WRITE(CDCLK_CTL, val);
>  	POSTING_READ(CDCLK_CTL);
> @@ -5577,7 +5596,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
>  	 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
>  	 * The modeset code is responsible for the selection of the exact link
>  	 * rate later on, with the constraint of choosing a frequency that
> -	 * works with required_vco.
> +	 * works with vco.
>  	 */
>  	val = I915_READ(DPLL_CTRL1);
>  
> @@ -5706,7 +5725,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
>  		if (dev_priv->skl_vco_freq != 8640)
>  			dev_priv->skl_vco_freq = 8100;
>  		skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> -		cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
> +		cdclk = skl_calc_cdclk(0, dev_priv->skl_vco_freq);
>  	} else {
>  		cdclk = dev_priv->cdclk_freq;
>  	}
> @@ -9724,34 +9743,14 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
>  	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>  	struct drm_i915_private *dev_priv = to_i915(state->dev);
>  	const int max_pixclk = ilk_max_pixel_rate(state);
> +	int vco = intel_state->cdclk_pll_vco;
>  	int cdclk;
>  
>  	/*
>  	 * FIXME should also account for plane ratio
>  	 * once 64bpp pixel formats are supported.
>  	 */
> -
> -	if (intel_state->cdclk_pll_vco == 8640) {
> -		/* vco 8640 */
> -		if (max_pixclk > 540000)
> -			cdclk = 617140;
> -		else if (max_pixclk > 432000)
> -			cdclk = 540000;
> -		else if (max_pixclk > 308570)
> -			cdclk = 432000;
> -		else
> -			cdclk = 308570;
> -	} else {
> -		/* VCO 8100 */
> -		if (max_pixclk > 540000)
> -			cdclk = 675000;
> -		else if (max_pixclk > 450000)
> -			cdclk = 540000;
> -		else if (max_pixclk > 337500)
> -			cdclk = 450000;
> -		else
> -			cdclk = 337500;
> -	}
> +	cdclk = skl_calc_cdclk(max_pixclk, vco);
>  
>  	/*
>  	 * FIXME move the cdclk caclulation to
> @@ -9765,9 +9764,7 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
>  
>  	intel_state->cdclk = intel_state->dev_cdclk = cdclk;
>  	if (!intel_state->active_crtcs)
> -		intel_state->dev_cdclk = ((intel_state->cdclk_pll_vco == 8640) ?
> -					   308570 : 337500);
> -
> +		intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
>  
>  	return 0;
>  }
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Re: [PATCH 05/21] drm/i915: Actually read out DPLL0 vco on skl from hardware

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we're trying to guess which lcpll vco frequency is used
> use based on the cdclk. That doesn't work for cdclk==540 since
> both vco frequencies can generate a 540 Mhz output. Let's stop
> guessing and just read the actual vco frequency from the
> hardware.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c  | 73 ++++++++++++++++++-----------------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c |  6 ---
>  2 files changed, 37 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c1b1632664a1..e65c3da744b0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5551,31 +5551,35 @@ static int skl_calc_cdclk(int max_pixclk, int vco)
>  	}
>  }
>  
> -static const struct skl_cdclk_entry {
> -	unsigned int freq;
> -	unsigned int vco;
> -} skl_cdclk_frequencies[] = {
> -	{ .freq = 308570, .vco = 8640 },
> -	{ .freq = 337500, .vco = 8100 },
> -	{ .freq = 432000, .vco = 8640 },
> -	{ .freq = 450000, .vco = 8100 },
> -	{ .freq = 540000, .vco = 8100 },
> -	{ .freq = 617140, .vco = 8640 },
> -	{ .freq = 675000, .vco = 8100 },
> -};
> -
> -unsigned int skl_cdclk_get_vco(unsigned int freq)
> +static void
> +skl_dpll0_update(struct drm_i915_private *dev_priv)
>  {
> -	unsigned int i;
> -
> -	for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
> -		const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
> +	u32 val;
>  
> -		if (e->freq == freq)
> -			return e->vco;
> +	val = I915_READ(LCPLL1_CTL);
> +	if ((val & LCPLL_PLL_ENABLE) == 0) {
> +		dev_priv->skl_vco_freq = 0;
> +		return;
>  	}
>  
> -	return 8100;
> +	val = I915_READ(DPLL_CTRL1);
> +
> +	switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
> +	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
> +	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
> +	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
> +	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
> +		dev_priv->skl_vco_freq = 8100;
> +		break;
> +	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
> +	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
> +		dev_priv->skl_vco_freq = 8640;
> +		break;
> +	default:
> +		MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
> +		dev_priv->skl_vco_freq = 0;
> +		break;
> +	}
>  }
>  
>  static void
> @@ -6614,43 +6618,40 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>  static int skylake_get_display_clock_speed(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> -	uint32_t cdctl = I915_READ(CDCLK_CTL);
> -	uint32_t linkrate;
> +	uint32_t cdctl;
>  
> -	if (!(lcpll1 & LCPLL_PLL_ENABLE))
> -		return 24000; /* 24MHz is the cd freq with NSSC ref */
> +	skl_dpll0_update(dev_priv);
>  
> -	if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
> -		return 540000;
> +	if (dev_priv->skl_vco_freq == 0)
> +		return 24000; /* 24MHz is the cd freq with NSSC ref */
>  
> -	linkrate = (I915_READ(DPLL_CTRL1) &
> -		    DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
> +	cdctl = I915_READ(CDCLK_CTL);
>  
> -	if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
> -	    linkrate == DPLL_CTRL1_LINK_RATE_1080) {
> -		/* vco 8640 */
> +	if (dev_priv->skl_vco_freq == 8640) {
>  		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
>  		case CDCLK_FREQ_450_432:
>  			return 432000;
>  		case CDCLK_FREQ_337_308:
>  			return 308570;
> +		case CDCLK_FREQ_540:
> +			return 540000;
>  		case CDCLK_FREQ_675_617:
>  			return 617140;
>  		default:
> -			WARN(1, "Unknown cd freq selection\n");
> +			MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
>  		}
>  	} else {
> -		/* vco 8100 */
>  		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
>  		case CDCLK_FREQ_450_432:
>  			return 450000;
>  		case CDCLK_FREQ_337_308:
>  			return 337500;
> +		case CDCLK_FREQ_540:
> +			return 540000;
>  		case CDCLK_FREQ_675_617:
>  			return 675000;
>  		default:
> -			WARN(1, "Unknown cd freq selection\n");
> +			MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
>  		}
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 43ba60b3662e..5391ab66b64d 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1633,14 +1633,8 @@ static void intel_ddi_pll_init(struct drm_device *dev)
>  	uint32_t val = I915_READ(LCPLL_CTL);
>  
>  	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> -		int cdclk_freq;
> -
> -		cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> -		dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq);
>  		if (skl_sanitize_cdclk(dev_priv))
>  			DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> -		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> -			DRM_ERROR("LCPLL1 is disabled\n");
>  	} else if (!IS_BROXTON(dev_priv)) {
>  		/*
>  		 * The LCPLL register should be turned on by the BIOS. For now
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Re: [PATCH 06/21] drm/i915: Report the current DPLL0 vco on SKL/KBL

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e65c3da744b0..95997eed9dd6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5320,8 +5320,13 @@ static void intel_update_cdclk(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> -	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
> -			 dev_priv->cdclk_freq);
> +
> +	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> +		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d MHz\n",
> +				 dev_priv->cdclk_freq, dev_priv->skl_vco_freq);
> +	else
> +		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
> +				 dev_priv->cdclk_freq);
>  
>  	/*
>  	 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
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Re: [PATCH 07/21] drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> In case we originally guessed wrong which lcpll vco frequency to use,
> we will need to shut down the pll and restart it when reprogamming the
> cdclk.
> 
> This also allows us to track the actual vco frequency in dev_priv
> instead of just a guess.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 54 +++++++++++++++++++-----------------
>  1 file changed, 29 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 95997eed9dd6..cd2809179042 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5626,6 +5626,8 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
>  
>  	if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
>  		DRM_ERROR("DPLL0 not locked\n");
> +
> +	dev_priv->skl_vco_freq = vco;
>  }
>  
>  static void
> @@ -5634,6 +5636,8 @@ skl_dpll0_disable(struct drm_i915_private *dev_priv)
>  	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
>  	if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
>  		DRM_ERROR("Couldn't disable DPLL0\n");
> +
> +	dev_priv->skl_vco_freq = 0;
>  }
>  
>  static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
> @@ -5663,12 +5667,14 @@ static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
>  	return false;
>  }
>  
> -static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
> +static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
>  {
>  	struct drm_device *dev = dev_priv->dev;
>  	u32 freq_select, pcu_ack;
>  
> -	DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", cdclk);
> +	WARN_ON((cdclk == 24000) != (vco == 0));
> +
> +	DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d MHz)\n", cdclk, vco);
>  
>  	if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
>  		DRM_ERROR("failed to inform PCU about cdclk change\n");
> @@ -5699,6 +5705,13 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
>  		break;
>  	}
>  
> +	if (dev_priv->skl_vco_freq != 0 &&
> +	    dev_priv->skl_vco_freq != vco)
> +		skl_dpll0_disable(dev_priv);
> +
> +	if (dev_priv->skl_vco_freq != vco)
> +		skl_dpll0_enable(dev_priv, vco);
> +
>  	I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
>  	POSTING_READ(CDCLK_CTL);
>  
> @@ -5721,26 +5734,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>  	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
>  		DRM_ERROR("DBuf power disable timeout\n");
>  
> -	skl_dpll0_disable(dev_priv);
> +	skl_set_cdclk(dev_priv, 24000, 0);

The spec doesn't say how to program CDCLK for the bypass case and we'll
program the 'frequency decimal' field to something isn't listed as a
valid value (and not matching the CD frequency select value). But I
think CDCLK is don't-care in that case, so it's fine.

>  }
>  
>  void skl_init_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	unsigned int cdclk;
> -
>  	/* DPLL0 not enabled (happens on early BIOS versions) */
> -	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> -		/* enable DPLL0 */
> -		if (dev_priv->skl_vco_freq != 8640)
> -			dev_priv->skl_vco_freq = 8100;
> -		skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> -		cdclk = skl_calc_cdclk(0, dev_priv->skl_vco_freq);
> -	} else {
> -		cdclk = dev_priv->cdclk_freq;
> -	}
> +	if (dev_priv->skl_vco_freq == 0) {
> +		int cdclk, vco;
>  
> -	/* set CDCLK to the lowest frequency, Modeset follows */
> -	skl_set_cdclk(dev_priv, cdclk);
> +		/* set CDCLK to the lowest frequency, Modeset follows */
> +		vco = 8100;
> +		cdclk = skl_calc_cdclk(0, vco);
> +
> +		skl_set_cdclk(dev_priv, cdclk, vco);
> +	}
>  
>  	/* enable DBUF power */
>  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> @@ -9777,16 +9785,12 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
>  
>  static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)

Why is the above called old_state?

The patch looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>

>  {
> -	struct drm_device *dev = old_state->dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
> -
> -	/*
> -	 * FIXME disable/enable PLL should wrap set_cdclk()
> -	 */
> -	skl_set_cdclk(dev_priv, req_cdclk);
> +	struct drm_i915_private *dev_priv = to_i915(old_state->dev);
> +	struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
> +	unsigned int req_cdclk = intel_state->dev_cdclk;
> +	unsigned int req_vco = intel_state->cdclk_pll_vco;
>  
> -	dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
> +	skl_set_cdclk(dev_priv, req_cdclk, req_vco);
>  }
>  
>  static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
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Re: [PATCH 07/21] drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL

[Ville Syrjälä]

On Thu, May 19, 2016 at 04:04:40PM +0300, Imre Deak wrote:
> On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > In case we originally guessed wrong which lcpll vco frequency to use,
> > we will need to shut down the pll and restart it when reprogamming the
> > cdclk.
> > 
> > This also allows us to track the actual vco frequency in dev_priv
> > instead of just a guess.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 54 +++++++++++++++++++-----------------
> >  1 file changed, 29 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 95997eed9dd6..cd2809179042 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5626,6 +5626,8 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
> >  
> >  	if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
> >  		DRM_ERROR("DPLL0 not locked\n");
> > +
> > +	dev_priv->skl_vco_freq = vco;
> >  }
> >  
> >  static void
> > @@ -5634,6 +5636,8 @@ skl_dpll0_disable(struct drm_i915_private *dev_priv)
> >  	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
> >  	if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
> >  		DRM_ERROR("Couldn't disable DPLL0\n");
> > +
> > +	dev_priv->skl_vco_freq = 0;
> >  }
> >  
> >  static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
> > @@ -5663,12 +5667,14 @@ static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
> >  	return false;
> >  }
> >  
> > -static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
> > +static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
> >  {
> >  	struct drm_device *dev = dev_priv->dev;
> >  	u32 freq_select, pcu_ack;
> >  
> > -	DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", cdclk);
> > +	WARN_ON((cdclk == 24000) != (vco == 0));
> > +
> > +	DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d MHz)\n", cdclk, vco);
> >  
> >  	if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
> >  		DRM_ERROR("failed to inform PCU about cdclk change\n");
> > @@ -5699,6 +5705,13 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
> >  		break;
> >  	}
> >  
> > +	if (dev_priv->skl_vco_freq != 0 &&
> > +	    dev_priv->skl_vco_freq != vco)
> > +		skl_dpll0_disable(dev_priv);
> > +
> > +	if (dev_priv->skl_vco_freq != vco)
> > +		skl_dpll0_enable(dev_priv, vco);
> > +
> >  	I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
> >  	POSTING_READ(CDCLK_CTL);
> >  
> > @@ -5721,26 +5734,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> >  	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
> >  		DRM_ERROR("DBuf power disable timeout\n");
> >  
> > -	skl_dpll0_disable(dev_priv);
> > +	skl_set_cdclk(dev_priv, 24000, 0);
> 
> The spec doesn't say how to program CDCLK for the bypass case and we'll
> program the 'frequency decimal' field to something isn't listed as a
> valid value (and not matching the CD frequency select value). But I
> think CDCLK is don't-care in that case, so it's fine.
> 
> >  }
> >  
> >  void skl_init_cdclk(struct drm_i915_private *dev_priv)
> >  {
> > -	unsigned int cdclk;
> > -
> >  	/* DPLL0 not enabled (happens on early BIOS versions) */
> > -	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> > -		/* enable DPLL0 */
> > -		if (dev_priv->skl_vco_freq != 8640)
> > -			dev_priv->skl_vco_freq = 8100;
> > -		skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> > -		cdclk = skl_calc_cdclk(0, dev_priv->skl_vco_freq);
> > -	} else {
> > -		cdclk = dev_priv->cdclk_freq;
> > -	}
> > +	if (dev_priv->skl_vco_freq == 0) {
> > +		int cdclk, vco;
> >  
> > -	/* set CDCLK to the lowest frequency, Modeset follows */
> > -	skl_set_cdclk(dev_priv, cdclk);
> > +		/* set CDCLK to the lowest frequency, Modeset follows */
> > +		vco = 8100;
> > +		cdclk = skl_calc_cdclk(0, vco);
> > +
> > +		skl_set_cdclk(dev_priv, cdclk, vco);
> > +	}
> >  
> >  	/* enable DBUF power */
> >  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> > @@ -9777,16 +9785,12 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> >  
> >  static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> 
> Why is the above called old_state?

Because atomic is stupid. There's just one top level state which starts
out as the new state, but later we swap the connector/crtc/plane state
pointers around so that the top level state points to the old state
for those things. That's why it's called old_state here. Everything
else stored in that top level state is not swapped though so it's
actually an extremely confusing mix of old and new state.

I think what we should do is pull all the state stored in the top level
atomic state structure into a separate structure and store a pointer to
that in the top level atomic state just like for everything else. We
can then swap that pointer as well. That way all the old vs. new stuff
would be consistent. It migth also clean up the horrible mess with the
atomic_cdclk stuff and whatnot.

> 
> The patch looks ok:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> >  {
> > -	struct drm_device *dev = old_state->dev;
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
> > -
> > -	/*
> > -	 * FIXME disable/enable PLL should wrap set_cdclk()
> > -	 */
> > -	skl_set_cdclk(dev_priv, req_cdclk);
> > +	struct drm_i915_private *dev_priv = to_i915(old_state->dev);
> > +	struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
> > +	unsigned int req_cdclk = intel_state->dev_cdclk;
> > +	unsigned int req_vco = intel_state->cdclk_pll_vco;
> >  
> > -	dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
> > +	skl_set_cdclk(dev_priv, req_cdclk, req_vco);
> >  }
> >  
> >  static int haswell_crtc_compute_clock(struct intel_crtc *crtc,

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 07/21] drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL

[Imre Deak]

On to, 2016-05-19 at 16:18 +0300, Ville Syrjälä wrote:
> On Thu, May 19, 2016 at 04:04:40PM +0300, Imre Deak wrote:
> > On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > In case we originally guessed wrong which lcpll vco frequency to use,
> > > we will need to shut down the pll and restart it when reprogamming the
> > > cdclk.
> > > 
> > > This also allows us to track the actual vco frequency in dev_priv
> > > instead of just a guess.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c | 54 +++++++++++++++++++-----------------
> > >  1 file changed, 29 insertions(+), 25 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 95997eed9dd6..cd2809179042 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -5626,6 +5626,8 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
> > >  
> > >  	if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
> > >  		DRM_ERROR("DPLL0 not locked\n");
> > > +
> > > +	dev_priv->skl_vco_freq = vco;
> > >  }
> > >  
> > >  static void
> > > @@ -5634,6 +5636,8 @@ skl_dpll0_disable(struct drm_i915_private *dev_priv)
> > >  	I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
> > >  	if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
> > >  		DRM_ERROR("Couldn't disable DPLL0\n");
> > > +
> > > +	dev_priv->skl_vco_freq = 0;
> > >  }
> > >  
> > >  static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
> > > @@ -5663,12 +5667,14 @@ static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
> > >  	return false;
> > >  }
> > >  
> > > -static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
> > > +static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
> > >  {
> > >  	struct drm_device *dev = dev_priv->dev;
> > >  	u32 freq_select, pcu_ack;
> > >  
> > > -	DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", cdclk);
> > > +	WARN_ON((cdclk == 24000) != (vco == 0));
> > > +
> > > +	DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d MHz)\n", cdclk, vco);
> > >  
> > >  	if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
> > >  		DRM_ERROR("failed to inform PCU about cdclk change\n");
> > > @@ -5699,6 +5705,13 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
> > >  		break;
> > >  	}
> > >  
> > > +	if (dev_priv->skl_vco_freq != 0 &&
> > > +	    dev_priv->skl_vco_freq != vco)
> > > +		skl_dpll0_disable(dev_priv);
> > > +
> > > +	if (dev_priv->skl_vco_freq != vco)
> > > +		skl_dpll0_enable(dev_priv, vco);
> > > +
> > >  	I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
> > >  	POSTING_READ(CDCLK_CTL);
> > >  
> > > @@ -5721,26 +5734,21 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> > >  	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
> > >  		DRM_ERROR("DBuf power disable timeout\n");
> > >  
> > > -	skl_dpll0_disable(dev_priv);
> > > +	skl_set_cdclk(dev_priv, 24000, 0);
> > 
> > The spec doesn't say how to program CDCLK for the bypass case and we'll
> > program the 'frequency decimal' field to something isn't listed as a
> > valid value (and not matching the CD frequency select value). But I
> > think CDCLK is don't-care in that case, so it's fine.
> > 
> > >  }
> > >  
> > >  void skl_init_cdclk(struct drm_i915_private *dev_priv)
> > >  {
> > > -	unsigned int cdclk;
> > > -
> > >  	/* DPLL0 not enabled (happens on early BIOS versions) */
> > > -	if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
> > > -		/* enable DPLL0 */
> > > -		if (dev_priv->skl_vco_freq != 8640)
> > > -			dev_priv->skl_vco_freq = 8100;
> > > -		skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
> > > -		cdclk = skl_calc_cdclk(0, dev_priv->skl_vco_freq);
> > > -	} else {
> > > -		cdclk = dev_priv->cdclk_freq;
> > > -	}
> > > +	if (dev_priv->skl_vco_freq == 0) {
> > > +		int cdclk, vco;
> > >  
> > > -	/* set CDCLK to the lowest frequency, Modeset follows */
> > > -	skl_set_cdclk(dev_priv, cdclk);
> > > +		/* set CDCLK to the lowest frequency, Modeset follows */
> > > +		vco = 8100;
> > > +		cdclk = skl_calc_cdclk(0, vco);
> > > +
> > > +		skl_set_cdclk(dev_priv, cdclk, vco);
> > > +	}
> > >  
> > >  	/* enable DBUF power */
> > >  	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> > > @@ -9777,16 +9785,12 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> > >  
> > >  static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> > 
> > Why is the above called old_state?
> 
> Because atomic is stupid. There's just one top level state which starts
> out as the new state, but later we swap the connector/crtc/plane state
> pointers around so that the top level state points to the old state
> for those things. That's why it's called old_state here. Everything
> else stored in that top level state is not swapped though so it's
> actually an extremely confusing mix of old and new state.

Ok, separating old and new states better would make sense.

> I think what we should do is pull all the state stored in the top level
> atomic state structure into a separate structure and store a pointer to
> that in the top level atomic state just like for everything else. We
> can then swap that pointer as well. That way all the old vs. new stuff
> would be consistent. It migth also clean up the horrible mess with the
> atomic_cdclk stuff and whatnot.

On that note AFAICS dev_priv->atomic_cdclk_freq is just dev_priv-
>cdclk_freq. If so would be good to simplify, if not some code comment
about the real justification for atomic_cdclk_freq would be nice. 

--Imre

> 
> > 
> > The patch looks ok:
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > 
> > >  {
> > > -	struct drm_device *dev = old_state->dev;
> > > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > > -	unsigned int req_cdclk = to_intel_atomic_state(old_state)->dev_cdclk;
> > > -
> > > -	/*
> > > -	 * FIXME disable/enable PLL should wrap set_cdclk()
> > > -	 */
> > > -	skl_set_cdclk(dev_priv, req_cdclk);
> > > +	struct drm_i915_private *dev_priv = to_i915(old_state->dev);
> > > +	struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
> > > +	unsigned int req_cdclk = intel_state->dev_cdclk;
> > > +	unsigned int req_vco = intel_state->cdclk_pll_vco;
> > >  
> > > -	dev_priv->skl_vco_freq = to_intel_atomic_state(old_state)->cdclk_pll_vco;
> > > +	skl_set_cdclk(dev_priv, req_cdclk, req_vco);
> > >  }
> > >  
> > >  static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> 
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Re: [PATCH 08/21] drm/i915: Keep track of preferred cdclk vco frequency on SKL

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Now that skl_vco_freq tracks the actual DPLL0 vco frequency, we'll need
> something that keeps track of which vco frequency we want to use in case
> the current vco is 0. This would be important across supend/resume since
> we'll disable DPLL0 around those parts.
> 
> We'll also update our idea of max cdclk/dotclock when the preferred
> vco changes. That could happen if out initial guess was wrong, and
> later eDP would force us to change it. One issue here could be that
> changing the max dotclock could cause our mode list to change during
> next time the displays get probed. But I don't see a good way to avoid
> that, except perhaps by allowing either vco frequency to be used as
> needed. But the docs suggest that such usage wasn't really inteded.
> 
> Also need to make sure we don't update our max_cdclk value before we
> have a preferred vco value, which means moving that to happen after
> the cdclk sanitation.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/intel_display.c  | 48 +++++++++++++++++++++++++++++------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c |  5 ++++
>  drivers/gpu/drm/i915/intel_drv.h      |  1 +
>  4 files changed, 47 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b319da970c8a..46a22732088e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1821,6 +1821,7 @@ struct drm_i915_private {
>  
>  	unsigned int fsb_freq, mem_freq, is_ddr3;
>  	unsigned int skl_vco_freq;
> +	unsigned int skl_preferred_vco_freq;
>  	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
>  	unsigned int max_dotclk_freq;
>  	unsigned int rawclk_freq;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index cd2809179042..107a7799bdde 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5265,21 +5265,34 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
>  		return max_cdclk_freq*90/100;
>  }
>  
> +static int skl_calc_cdclk(int max_pixclk, int vco);
> +
>  static void intel_update_max_cdclk(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
>  		u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> +		int max_cdclk, vco;
> +
> +		vco = dev_priv->skl_preferred_vco_freq;
> +		WARN_ON(vco != 8100 && vco != 8640);
>  
> +		/*
> +		 * Use the lower (vco 8640) cdclk values as a
> +		 * first guess. skl_calc_cdclk() will correct it
> +		 * if the preferred vco is 8100 instead.
> +		 */
>  		if (limit == SKL_DFSM_CDCLK_LIMIT_675)
> -			dev_priv->max_cdclk_freq = 675000;
> +			max_cdclk = 617140;
>  		else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
> -			dev_priv->max_cdclk_freq = 540000;
> +			max_cdclk = 540000;
>  		else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
> -			dev_priv->max_cdclk_freq = 450000;
> +			max_cdclk = 432000;
>  		else
> -			dev_priv->max_cdclk_freq = 337500;
> +			max_cdclk = 308570;
> +
> +		dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
>  	} else if (IS_BROXTON(dev)) {
>  		dev_priv->max_cdclk_freq = 624000;
>  	} else if (IS_BROADWELL(dev))  {
> @@ -5336,9 +5349,6 @@ static void intel_update_cdclk(struct drm_device *dev)
>  	 */
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>  		I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
> -
> -	if (dev_priv->max_cdclk_freq == 0)
> -		intel_update_max_cdclk(dev);
>  }
>  
>  /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
> @@ -5587,12 +5597,24 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
> +{
> +	bool changed = dev_priv->skl_preferred_vco_freq != vco;
> +
> +	dev_priv->skl_preferred_vco_freq = vco;
> +
> +	if (changed)
> +		intel_update_max_cdclk(dev_priv->dev);
> +}
> +
>  static void
>  skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
>  {
>  	int min_cdclk = skl_calc_cdclk(0, vco);
>  	u32 val;
>  
> +	WARN_ON(vco != 8100 && vco != 8640);
> +
>  	/* select the minimum CDCLK before enabling DPLL 0 */
>  	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
>  	I915_WRITE(CDCLK_CTL, val);
> @@ -5628,6 +5650,9 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
>  		DRM_ERROR("DPLL0 not locked\n");
>  
>  	dev_priv->skl_vco_freq = vco;
> +
> +	/* We'll want to keep using the current vco from now on. */
> +	skl_set_preferred_cdclk_vco(dev_priv, vco);
>  }
>  
>  static void
> @@ -5744,7 +5769,9 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
>  		int cdclk, vco;
>  
>  		/* set CDCLK to the lowest frequency, Modeset follows */
> -		vco = 8100;
> +		vco = dev_priv->skl_preferred_vco_freq;
> +		if (vco == 0)
> +			vco = 8100;
>  		cdclk = skl_calc_cdclk(0, vco);
>  
>  		skl_set_cdclk(dev_priv, cdclk, vco);
> @@ -13359,6 +13386,8 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>  	if (dev_priv->display.modeset_calc_cdclk) {
>  		if (!intel_state->cdclk_pll_vco)
>  			intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
> +		if (!intel_state->cdclk_pll_vco)
> +			intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
>  
>  		ret = dev_priv->display.modeset_calc_cdclk(state);
>  		if (ret < 0)
> @@ -15525,6 +15554,9 @@ void intel_modeset_init(struct drm_device *dev)
>  
>  	intel_shared_dpll_init(dev);
>  
> +	if (dev_priv->max_cdclk_freq == 0)
> +		intel_update_max_cdclk(dev);
> +
>  	/* Just disable it once at startup */
>  	i915_disable_vga(dev);
>  	intel_setup_outputs(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 5391ab66b64d..34ec149fde85 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1635,6 +1635,11 @@ static void intel_ddi_pll_init(struct drm_device *dev)
>  	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
>  		if (skl_sanitize_cdclk(dev_priv))
>  			DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> +
> +		/* We'll want to keep using the current vco from now on */
> +		if (dev_priv->skl_vco_freq != 0)
> +			skl_set_preferred_cdclk_vco(dev_priv,
> +						    dev_priv->skl_vco_freq);
>  	} else if (!IS_BROXTON(dev_priv)) {
>  		/*
>  		 * The LCPLL register should be turned on by the BIOS. For now
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c7cb9829547e..8f48a32e991b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1145,6 +1145,7 @@ void i915_audio_component_init(struct drm_i915_private *dev_priv);
>  void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
>  
>  /* intel_display.c */
> +void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
>  void intel_update_rawclk(struct drm_i915_private *dev_priv);
>  int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
>  		      const char *name, u32 reg, int ref_freq);
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Re: [PATCH 09/21] drm/i915: Beef up skl_sanitize_cdclk() a bit

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Also verify the DPLL_CTRL1 register value in skl_sanitize_cdclk(), throw
> out a few unneeded variables, and write the CDCLK_CTL check a bit more
> legible way.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 18 +++++++++++++-----
>  1 file changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 107a7799bdde..493160682b2a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5789,9 +5789,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
>  
>  int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
> -	uint32_t cdctl = I915_READ(CDCLK_CTL);
> -	int freq = dev_priv->cdclk_freq;
> +	uint32_t cdctl, expected;
>  
>  	/*
>  	 * check if the pre-os intialized the display
> @@ -5802,7 +5800,14 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  		goto sanitize;
>  
>  	/* Is PLL enabled and locked ? */
> -	if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
> +	if ((I915_READ(LCPLL1_CTL) & (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK)) !=
> +	    (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK))
> +		goto sanitize;
> +
> +	if ((I915_READ(DPLL_CTRL1) & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
> +				      DPLL_CTRL1_SSC(SKL_DPLL0) |
> +				      DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
> +	    DPLL_CTRL1_OVERRIDE(SKL_DPLL0))
>  		goto sanitize;
>  
>  	/* DPLL okay; verify the cdclock
> @@ -5811,7 +5816,10 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  	 * decimal part is programmed wrong from BIOS where pre-os does not
>  	 * enable display. Verify the same as well.
>  	 */
> -	if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
> +	cdctl = I915_READ(CDCLK_CTL);
> +	expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
> +		skl_cdclk_decimal(dev_priv->cdclk_freq);
> +	if (cdctl == expected)
>  		/* All well; nothing to sanitize */
>  		return false;
>  sanitize:
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Re: [PATCH 10/21] drm/i915: Unify SKL cdclk init paths

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we initialize cdclk on SKL from two different places,
> depending on whether it's during driver init or resume. Let's
> unify it to happen from the same place always, and that place will be
> the display core init function.
> 
> To do this we first run through the cdclk sanitation code, which will
> first verify that the PLL is programmed correctly, after which we can
> read out the current cdclk frequency, and once the cdclk is known we
> verify that the cdclk "decimal" frequency is programmed correctly. If
> any of these fail we will force a cdclk change, and to be safe we also
> force the PLL to be turned off and on again. If the sanitation step
> didn't notice anything amiss, we'll skip the cdclk programming which
> will prevent cdclk reprogramming when the displays might be active.
> 
> We can also toss in a few WARNs about the register values into
> skl_update_dpll0() since we now know that the PLL state should
> always be sane when that function is called.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c    | 40 +++++++++++++++++++++++++--------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c   | 11 ++-------
>  drivers/gpu/drm/i915/intel_drv.h        |  1 -
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  5 +----
>  4 files changed, 34 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 493160682b2a..da903b718c11 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5577,8 +5577,15 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
>  		return;
>  	}
>  
> +	WARN_ON((val & LCPLL_PLL_LOCK) == 0);
> +
>  	val = I915_READ(DPLL_CTRL1);
>  
> +	WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
> +			DPLL_CTRL1_SSC(SKL_DPLL0) |
> +			DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
> +		DPLL_CTRL1_OVERRIDE(SKL_DPLL0));
> +
>  	switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
>  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
>  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
> @@ -5748,6 +5755,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
>  	intel_update_cdclk(dev);
>  }
>  
> +static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> +
>  void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	/* disable DBUF power */
> @@ -5764,10 +5773,19 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>  
>  void skl_init_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	/* DPLL0 not enabled (happens on early BIOS versions) */
> -	if (dev_priv->skl_vco_freq == 0) {
> -		int cdclk, vco;
> +	int cdclk, vco;
> +
> +	skl_sanitize_cdclk(dev_priv);
>  
> +	if (dev_priv->cdclk_freq != 0 && dev_priv->skl_vco_freq != 0) {
> +		/*
> +		 * Use the current vco as out initial

typo above.

Looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +		 * guess as to what the preferred vco is.
> +		 */
> +		if (dev_priv->skl_preferred_vco_freq == 0)
> +			skl_set_preferred_cdclk_vco(dev_priv,
> +						    dev_priv->skl_vco_freq);
> +	} else {
>  		/* set CDCLK to the lowest frequency, Modeset follows */
>  		vco = dev_priv->skl_preferred_vco_freq;
>  		if (vco == 0)
> @@ -5787,7 +5805,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
>  		DRM_ERROR("DBuf power enable timeout\n");
>  }
>  
> -int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> +static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	uint32_t cdctl, expected;
>  
> @@ -5810,6 +5828,8 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  	    DPLL_CTRL1_OVERRIDE(SKL_DPLL0))
>  		goto sanitize;
>  
> +	intel_update_cdclk(dev_priv->dev);
> +
>  	/* DPLL okay; verify the cdclock
>  	 *
>  	 * Noticed in some instances that the freq selection is correct but
> @@ -5821,13 +5841,15 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
>  		skl_cdclk_decimal(dev_priv->cdclk_freq);
>  	if (cdctl == expected)
>  		/* All well; nothing to sanitize */
> -		return false;
> -sanitize:
> +		return;
>  
> -	skl_init_cdclk(dev_priv);
> +sanitize:
> +	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
>  
> -	/* we did have to sanitize */
> -	return true;
> +	/* force cdclk programming */
> +	dev_priv->cdclk_freq = 0;
> +	/* force full PLL disable + enable */
> +	dev_priv->skl_vco_freq = -1;
>  }
>  
>  /* Adjust CDclk dividers to allow high res or save power if possible */
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 34ec149fde85..6b70e1eccb13 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1630,17 +1630,10 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
>  static void intel_ddi_pll_init(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	uint32_t val = I915_READ(LCPLL_CTL);
>  
> -	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> -		if (skl_sanitize_cdclk(dev_priv))
> -			DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> +	if (INTEL_GEN(dev_priv) < 9) {
> +		uint32_t val = I915_READ(LCPLL_CTL);
>  
> -		/* We'll want to keep using the current vco from now on */
> -		if (dev_priv->skl_vco_freq != 0)
> -			skl_set_preferred_cdclk_vco(dev_priv,
> -						    dev_priv->skl_vco_freq);
> -	} else if (!IS_BROXTON(dev_priv)) {
>  		/*
>  		 * The LCPLL register should be turned on by the BIOS. For now
>  		 * let's just check its state and print errors in case
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 8f48a32e991b..319e52278d1f 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1279,7 +1279,6 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
>  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
>  void gen9_enable_dc5(struct drm_i915_private *dev_priv);
>  void skl_init_cdclk(struct drm_i915_private *dev_priv);
> -int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
>  void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
>  unsigned int skl_cdclk_get_vco(unsigned int freq);
>  void skl_enable_dc6(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index b69b935516fb..fefe22c3c163 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2200,12 +2200,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  
>  	mutex_unlock(&power_domains->lock);
>  
> -	if (!resume)
> -		return;
> -
>  	skl_init_cdclk(dev_priv);
>  
> -	if (dev_priv->csr.dmc_payload)
> +	if (resume && dev_priv->csr.dmc_payload)
>  		intel_csr_load_program(dev_priv);
>  }
>  
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Re: [PATCH 11/21] drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> SKL and BXT have the same snippets of code for enabling disabling the
> DBUF. Extract those into helpers and move the calls from
> init/unit_cdclk() to the display core init/init since this stuff isn't
> really about cdclk. Also doing the enable twice shouldn't hurt since
> you're just setting the request bit again when it was already set.
> 
> We can also toss in a few WARNs about the register values into
> skl_get_dpll0_vco() now that we know that things should always be
> sane there.
> 
> Flatten skl_init_cdclk() while at it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c    | 58 ++++-----------------------------
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 32 ++++++++++++++++++
>  2 files changed, 38 insertions(+), 52 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index da903b718c11..e908f360da74 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5480,18 +5480,6 @@ static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
>  
>  	/* TODO: Check for a valid CDCLK rate */
>  
> -	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
> -		DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
> -
> -		return false;
> -	}
> -
> -	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
> -		DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
> -
> -		return false;
> -	}
> -
>  	return true;
>  }
>  
> @@ -5518,26 +5506,10 @@ void broxton_init_cdclk(struct drm_i915_private *dev_priv)
>  	 *   here, it belongs to modeset time
>  	 */
>  	broxton_set_cdclk(dev_priv, 624000);
> -
> -	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> -	POSTING_READ(DBUF_CTL);
> -
> -	udelay(10);
> -
> -	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
> -		DRM_ERROR("DBuf power enable timeout!\n");
>  }
>  
>  void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
> -	POSTING_READ(DBUF_CTL);
> -
> -	udelay(10);
> -
> -	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
> -		DRM_ERROR("DBuf power disable timeout!\n");
> -
>  	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
>  	broxton_set_cdclk(dev_priv, 19200);
>  }
> @@ -5759,15 +5731,6 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
>  
>  void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	/* disable DBUF power */
> -	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
> -	POSTING_READ(DBUF_CTL);
> -
> -	udelay(10);
> -
> -	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
> -		DRM_ERROR("DBuf power disable timeout\n");
> -
>  	skl_set_cdclk(dev_priv, 24000, 0);
>  }
>  
> @@ -5785,24 +5748,15 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
>  		if (dev_priv->skl_preferred_vco_freq == 0)
>  			skl_set_preferred_cdclk_vco(dev_priv,
>  						    dev_priv->skl_vco_freq);
> -	} else {
> -		/* set CDCLK to the lowest frequency, Modeset follows */
> -		vco = dev_priv->skl_preferred_vco_freq;
> -		if (vco == 0)
> -			vco = 8100;
> -		cdclk = skl_calc_cdclk(0, vco);
> -
> -		skl_set_cdclk(dev_priv, cdclk, vco);
> +		return;
>  	}
>  
> -	/* enable DBUF power */
> -	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> -	POSTING_READ(DBUF_CTL);
> -
> -	udelay(10);
> +	vco = dev_priv->skl_preferred_vco_freq;
> +	if (vco == 0)
> +		vco = 8100;
> +	cdclk = skl_calc_cdclk(0, vco);
>  
> -	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
> -		DRM_ERROR("DBuf power enable timeout\n");
> +	skl_set_cdclk(dev_priv, cdclk, vco);
>  }
>  
>  static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index fefe22c3c163..6817a3cb5fbc 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2176,6 +2176,28 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
>  	mutex_unlock(&power_domains->lock);
>  }
>  
> +static void skl_dbuf_enable(struct drm_i915_private *dev_priv)

I would've used gen9_ for these, but either way:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +{
> +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> +	POSTING_READ(DBUF_CTL);
> +
> +	udelay(10);
> +
> +	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
> +		DRM_ERROR("DBuf power enable timeout\n");
> +}
> +
> +static void skl_dbuf_disable(struct drm_i915_private *dev_priv)
> +{
> +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
> +	POSTING_READ(DBUF_CTL);
> +
> +	udelay(10);
> +
> +	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
> +		DRM_ERROR("DBuf power disable timeout!\n");
> +}
> +
>  static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  				   bool resume)
>  {
> @@ -2202,6 +2224,8 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  
>  	skl_init_cdclk(dev_priv);
>  
> +	skl_dbuf_enable(dev_priv);
> +
>  	if (resume && dev_priv->csr.dmc_payload)
>  		intel_csr_load_program(dev_priv);
>  }
> @@ -2213,6 +2237,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
>  
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
> +	skl_dbuf_disable(dev_priv);
> +
>  	skl_uninit_cdclk(dev_priv);
>  
>  	/* The spec doesn't call for removing the reset handshake flag */
> @@ -2257,6 +2283,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
>  	mutex_unlock(&power_domains->lock);
>  
>  	broxton_init_cdclk(dev_priv);
> +
> +	skl_dbuf_enable(dev_priv);
> +
>  	broxton_ddi_phy_init(dev_priv);
>  
>  	broxton_cdclk_verify_state(dev_priv);
> @@ -2274,6 +2303,9 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
>  	broxton_ddi_phy_uninit(dev_priv);
> +
> +	skl_dbuf_disable(dev_priv);
> +
>  	broxton_uninit_cdclk(dev_priv);
>  
>  	/* The spec doesn't call for removing the reset handshake flag */
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Re: [PATCH 12/21] drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The SKL 308.57 MHz cdclk is probably 8640/28 = ~308.571 Mhz.
> Similartly the 617.14 MHz cdclk is probably 8640/14 = ~617.143 MHz.
> Let's use the slightly more accurate numbers. Potentially we might
> change to computing all of these based on dividers, but let's
> stick to the current theme for now..
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index e908f360da74..c0dbff37e2c3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5284,13 +5284,13 @@ static void intel_update_max_cdclk(struct
> drm_device *dev)
>  		 * if the preferred vco is 8100 instead.
>  		 */
>  		if (limit == SKL_DFSM_CDCLK_LIMIT_675)
> -			max_cdclk = 617140;
> +			max_cdclk = 617143;
>  		else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
>  			max_cdclk = 540000;
>  		else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
>  			max_cdclk = 432000;
>  		else
> -			max_cdclk = 308570;
> +			max_cdclk = 308571;
>  
>  		dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk,
> vco);
>  	} else if (IS_BROXTON(dev)) {
> @@ -5518,13 +5518,13 @@ static int skl_calc_cdclk(int max_pixclk, int
> vco)
>  {
>  	if (vco == 8640) {
>  		if (max_pixclk > 540000)
> -			return 617140;
> +			return 617143;
>  		else if (max_pixclk > 432000)
>  			return 540000;
> -		else if (max_pixclk > 308570)
> +		else if (max_pixclk > 308571)
>  			return 432000;
>  		else
> -			return 308570;
> +			return 308571;
>  	} else {
>  		/* VCO 8100 */
>  		if (max_pixclk > 540000)
> @@ -5696,13 +5696,13 @@ static void skl_set_cdclk(struct
> drm_i915_private *dev_priv, int cdclk, int vco)
>  		freq_select = CDCLK_FREQ_540;
>  		pcu_ack = 2;
>  		break;
> -	case 308570:
> +	case 308571:
>  	case 337500:
>  	default:
>  		freq_select = CDCLK_FREQ_337_308;
>  		pcu_ack = 0;
>  		break;
> -	case 617140:
> +	case 617143:
>  	case 675000:
>  		freq_select = CDCLK_FREQ_675_617;
>  		pcu_ack = 3;
> @@ -6656,11 +6656,11 @@ static int
> skylake_get_display_clock_speed(struct drm_device *dev)
>  		case CDCLK_FREQ_450_432:
>  			return 432000;
>  		case CDCLK_FREQ_337_308:
> -			return 308570;
> +			return 308571;
>  		case CDCLK_FREQ_540:
>  			return 540000;
>  		case CDCLK_FREQ_675_617:
> -			return 617140;
> +			return 617143;
>  		default:
>  			MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
>  		}
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Re: [PATCH 13/21] drm/i915: Rename skl_vco_freq to cdclk_pll.vco

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We'll want to store the cdclk PLL (whatever PLL that is in reality) vco
> frequency somewhere on other platforms too, so let's rename the
> skl_vco_freq to cdclk_pll.vco, and let's store it in kHz instead of MHz
> to match most of the other clocks.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  5 +++-
>  drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++------------------
>  drivers/gpu/drm/i915/intel_dp.c      |  4 +--
>  3 files changed, 31 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 46a22732088e..8da787cd2227 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1820,7 +1820,6 @@ struct drm_i915_private {
>  	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
>  
>  	unsigned int fsb_freq, mem_freq, is_ddr3;
> -	unsigned int skl_vco_freq;
>  	unsigned int skl_preferred_vco_freq;
>  	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
>  	unsigned int max_dotclk_freq;
> @@ -1828,6 +1827,10 @@ struct drm_i915_private {
>  	unsigned int hpll_freq;
>  	unsigned int czclk_freq;
>  
> +	struct {
> +		unsigned int vco;
> +	} cdclk_pll;
> +
>  	/**
>  	 * wq - Driver workqueue for GEM.
>  	 *
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c0dbff37e2c3..8bde3ae34869 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5276,7 +5276,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
>  		int max_cdclk, vco;
>  
>  		vco = dev_priv->skl_preferred_vco_freq;
> -		WARN_ON(vco != 8100 && vco != 8640);
> +		WARN_ON(vco != 8100000 && vco != 8640000);
>  
>  		/*
>  		 * Use the lower (vco 8640) cdclk values as a
> @@ -5335,8 +5335,8 @@ static void intel_update_cdclk(struct drm_device *dev)
>  	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
>  
>  	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> -		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d MHz\n",
> -				 dev_priv->cdclk_freq, dev_priv->skl_vco_freq);
> +		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz\n",
> +				 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco);
>  	else
>  		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
>  				 dev_priv->cdclk_freq);
> @@ -5516,7 +5516,7 @@ void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
>  
>  static int skl_calc_cdclk(int max_pixclk, int vco)
>  {
> -	if (vco == 8640) {
> +	if (vco == 8640000) {
>  		if (max_pixclk > 540000)
>  			return 617143;
>  		else if (max_pixclk > 432000)
> @@ -5526,7 +5526,6 @@ static int skl_calc_cdclk(int max_pixclk, int vco)
>  		else
>  			return 308571;
>  	} else {
> -		/* VCO 8100 */
>  		if (max_pixclk > 540000)
>  			return 675000;
>  		else if (max_pixclk > 450000)
> @@ -5545,7 +5544,7 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
>  
>  	val = I915_READ(LCPLL1_CTL);
>  	if ((val & LCPLL_PLL_ENABLE) == 0) {
> -		dev_priv->skl_vco_freq = 0;
> +		dev_priv->cdclk_pll.vco = 0;
>  		return;
>  	}
>  
> @@ -5563,15 +5562,15 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
>  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
>  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
>  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
> -		dev_priv->skl_vco_freq = 8100;
> +		dev_priv->cdclk_pll.vco = 8100000;
>  		break;
>  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
>  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
> -		dev_priv->skl_vco_freq = 8640;
> +		dev_priv->cdclk_pll.vco = 8640000;
>  		break;
>  	default:
>  		MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
> -		dev_priv->skl_vco_freq = 0;
> +		dev_priv->cdclk_pll.vco = 0;
>  		break;
>  	}
>  }
> @@ -5592,7 +5591,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
>  	int min_cdclk = skl_calc_cdclk(0, vco);
>  	u32 val;
>  
> -	WARN_ON(vco != 8100 && vco != 8640);
> +	WARN_ON(vco != 8100000 && vco != 8640000);
>  
>  	/* select the minimum CDCLK before enabling DPLL 0 */
>  	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
> @@ -5613,7 +5612,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
>  	val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
>  		 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
>  	val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
> -	if (vco == 8640)
> +	if (vco == 8640000)
>  		val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
>  					    SKL_DPLL0);
>  	else
> @@ -5628,7 +5627,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
>  	if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
>  		DRM_ERROR("DPLL0 not locked\n");
>  
> -	dev_priv->skl_vco_freq = vco;
> +	dev_priv->cdclk_pll.vco = vco;
>  
>  	/* We'll want to keep using the current vco from now on. */
>  	skl_set_preferred_cdclk_vco(dev_priv, vco);
> @@ -5641,7 +5640,7 @@ skl_dpll0_disable(struct drm_i915_private *dev_priv)
>  	if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
>  		DRM_ERROR("Couldn't disable DPLL0\n");
>  
> -	dev_priv->skl_vco_freq = 0;
> +	dev_priv->cdclk_pll.vco = 0;
>  }
>  
>  static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
> @@ -5678,7 +5677,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
>  
>  	WARN_ON((cdclk == 24000) != (vco == 0));
>  
> -	DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d MHz)\n", cdclk, vco);
> +	DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
>  
>  	if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
>  		DRM_ERROR("failed to inform PCU about cdclk change\n");
> @@ -5709,11 +5708,11 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
>  		break;
>  	}
>  
> -	if (dev_priv->skl_vco_freq != 0 &&
> -	    dev_priv->skl_vco_freq != vco)
> +	if (dev_priv->cdclk_pll.vco != 0 &&
> +	    dev_priv->cdclk_pll.vco != vco)
>  		skl_dpll0_disable(dev_priv);
>  
> -	if (dev_priv->skl_vco_freq != vco)
> +	if (dev_priv->cdclk_pll.vco != vco)
>  		skl_dpll0_enable(dev_priv, vco);
>  
>  	I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
> @@ -5740,20 +5739,20 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
>  
>  	skl_sanitize_cdclk(dev_priv);
>  
> -	if (dev_priv->cdclk_freq != 0 && dev_priv->skl_vco_freq != 0) {
> +	if (dev_priv->cdclk_freq > 0 && dev_priv->cdclk_pll.vco > 0) {

Looks unrelated, could've been part of patch 10/21. In any case:
Reviewed-by: Imre Deak <imre.deak@intel.com>

>  		/*
>  		 * Use the current vco as out initial
>  		 * guess as to what the preferred vco is.
>  		 */
>  		if (dev_priv->skl_preferred_vco_freq == 0)
>  			skl_set_preferred_cdclk_vco(dev_priv,
> -						    dev_priv->skl_vco_freq);
> +						    dev_priv->cdclk_pll.vco);
>  		return;
>  	}
>  
>  	vco = dev_priv->skl_preferred_vco_freq;
>  	if (vco == 0)
> -		vco = 8100;
> +		vco = 8100000;
>  	cdclk = skl_calc_cdclk(0, vco);
>  
>  	skl_set_cdclk(dev_priv, cdclk, vco);
> @@ -5803,7 +5802,7 @@ sanitize:
>  	/* force cdclk programming */
>  	dev_priv->cdclk_freq = 0;
>  	/* force full PLL disable + enable */
> -	dev_priv->skl_vco_freq = -1;
> +	dev_priv->cdclk_pll.vco = -1;
>  }
>  
>  /* Adjust CDclk dividers to allow high res or save power if possible */
> @@ -6646,12 +6645,12 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
>  
>  	skl_dpll0_update(dev_priv);
>  
> -	if (dev_priv->skl_vco_freq == 0)
> +	if (dev_priv->cdclk_pll.vco == 0)
>  		return 24000; /* 24MHz is the cd freq with NSSC ref */
>  
>  	cdctl = I915_READ(CDCLK_CTL);
>  
> -	if (dev_priv->skl_vco_freq == 8640) {
> +	if (dev_priv->cdclk_pll.vco == 8640000) {
>  		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
>  		case CDCLK_FREQ_450_432:
>  			return 432000;
> @@ -13369,7 +13368,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>  	 */
>  	if (dev_priv->display.modeset_calc_cdclk) {
>  		if (!intel_state->cdclk_pll_vco)
> -			intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
> +			intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
>  		if (!intel_state->cdclk_pll_vco)
>  			intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
>  
> @@ -13378,7 +13377,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
>  			return ret;
>  
>  		if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> -		    intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
> +		    intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
>  			ret = intel_modeset_all_pipes(state);
>  
>  		if (ret < 0)
> @@ -13720,7 +13719,7 @@ static int intel_atomic_commit(struct drm_device *dev,
>  
>  		if (dev_priv->display.modeset_commit_cdclk &&
>  		    (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> -		     intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
> +		     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
>  			dev_priv->display.modeset_commit_cdclk(state);
>  
>  		intel_modeset_verify_disabled(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 908c6f0f7feb..5f9a03651649 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1588,10 +1588,10 @@ found:
>  		switch (pipe_config->port_clock / 2) {
>  		case 108000:
>  		case 216000:
> -			vco = 8640;
> +			vco = 8640000;
>  			break;
>  		default:
> -			vco = 8100;
> +			vco = 8100000;
>  			break;
>  		}
>  
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Re: [PATCH 13/21] drm/i915: Rename skl_vco_freq to cdclk_pll.vco

[Ville Syrjälä]

On Thu, May 19, 2016 at 07:17:17PM +0300, Imre Deak wrote:
> On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > We'll want to store the cdclk PLL (whatever PLL that is in reality) vco
> > frequency somewhere on other platforms too, so let's rename the
> > skl_vco_freq to cdclk_pll.vco, and let's store it in kHz instead of MHz
> > to match most of the other clocks.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h      |  5 +++-
> >  drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++------------------
> >  drivers/gpu/drm/i915/intel_dp.c      |  4 +--
> >  3 files changed, 31 insertions(+), 29 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 46a22732088e..8da787cd2227 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1820,7 +1820,6 @@ struct drm_i915_private {
> >  	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
> >  
> >  	unsigned int fsb_freq, mem_freq, is_ddr3;
> > -	unsigned int skl_vco_freq;
> >  	unsigned int skl_preferred_vco_freq;
> >  	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
> >  	unsigned int max_dotclk_freq;
> > @@ -1828,6 +1827,10 @@ struct drm_i915_private {
> >  	unsigned int hpll_freq;
> >  	unsigned int czclk_freq;
> >  
> > +	struct {
> > +		unsigned int vco;
> > +	} cdclk_pll;
> > +
> >  	/**
> >  	 * wq - Driver workqueue for GEM.
> >  	 *
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index c0dbff37e2c3..8bde3ae34869 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5276,7 +5276,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> >  		int max_cdclk, vco;
> >  
> >  		vco = dev_priv->skl_preferred_vco_freq;
> > -		WARN_ON(vco != 8100 && vco != 8640);
> > +		WARN_ON(vco != 8100000 && vco != 8640000);
> >  
> >  		/*
> >  		 * Use the lower (vco 8640) cdclk values as a
> > @@ -5335,8 +5335,8 @@ static void intel_update_cdclk(struct drm_device *dev)
> >  	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> >  
> >  	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > -		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d MHz\n",
> > -				 dev_priv->cdclk_freq, dev_priv->skl_vco_freq);
> > +		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz\n",
> > +				 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco);
> >  	else
> >  		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
> >  				 dev_priv->cdclk_freq);
> > @@ -5516,7 +5516,7 @@ void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
> >  
> >  static int skl_calc_cdclk(int max_pixclk, int vco)
> >  {
> > -	if (vco == 8640) {
> > +	if (vco == 8640000) {
> >  		if (max_pixclk > 540000)
> >  			return 617143;
> >  		else if (max_pixclk > 432000)
> > @@ -5526,7 +5526,6 @@ static int skl_calc_cdclk(int max_pixclk, int vco)
> >  		else
> >  			return 308571;
> >  	} else {
> > -		/* VCO 8100 */
> >  		if (max_pixclk > 540000)
> >  			return 675000;
> >  		else if (max_pixclk > 450000)
> > @@ -5545,7 +5544,7 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
> >  
> >  	val = I915_READ(LCPLL1_CTL);
> >  	if ((val & LCPLL_PLL_ENABLE) == 0) {
> > -		dev_priv->skl_vco_freq = 0;
> > +		dev_priv->cdclk_pll.vco = 0;
> >  		return;
> >  	}
> >  
> > @@ -5563,15 +5562,15 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
> >  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
> >  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
> >  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
> > -		dev_priv->skl_vco_freq = 8100;
> > +		dev_priv->cdclk_pll.vco = 8100000;
> >  		break;
> >  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
> >  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
> > -		dev_priv->skl_vco_freq = 8640;
> > +		dev_priv->cdclk_pll.vco = 8640000;
> >  		break;
> >  	default:
> >  		MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
> > -		dev_priv->skl_vco_freq = 0;
> > +		dev_priv->cdclk_pll.vco = 0;
> >  		break;
> >  	}
> >  }
> > @@ -5592,7 +5591,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
> >  	int min_cdclk = skl_calc_cdclk(0, vco);
> >  	u32 val;
> >  
> > -	WARN_ON(vco != 8100 && vco != 8640);
> > +	WARN_ON(vco != 8100000 && vco != 8640000);
> >  
> >  	/* select the minimum CDCLK before enabling DPLL 0 */
> >  	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
> > @@ -5613,7 +5612,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
> >  	val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
> >  		 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
> >  	val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
> > -	if (vco == 8640)
> > +	if (vco == 8640000)
> >  		val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
> >  					    SKL_DPLL0);
> >  	else
> > @@ -5628,7 +5627,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
> >  	if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
> >  		DRM_ERROR("DPLL0 not locked\n");
> >  
> > -	dev_priv->skl_vco_freq = vco;
> > +	dev_priv->cdclk_pll.vco = vco;
> >  
> >  	/* We'll want to keep using the current vco from now on. */
> >  	skl_set_preferred_cdclk_vco(dev_priv, vco);
> > @@ -5641,7 +5640,7 @@ skl_dpll0_disable(struct drm_i915_private *dev_priv)
> >  	if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
> >  		DRM_ERROR("Couldn't disable DPLL0\n");
> >  
> > -	dev_priv->skl_vco_freq = 0;
> > +	dev_priv->cdclk_pll.vco = 0;
> >  }
> >  
> >  static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
> > @@ -5678,7 +5677,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
> >  
> >  	WARN_ON((cdclk == 24000) != (vco == 0));
> >  
> > -	DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d MHz)\n", cdclk, vco);
> > +	DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
> >  
> >  	if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
> >  		DRM_ERROR("failed to inform PCU about cdclk change\n");
> > @@ -5709,11 +5708,11 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
> >  		break;
> >  	}
> >  
> > -	if (dev_priv->skl_vco_freq != 0 &&
> > -	    dev_priv->skl_vco_freq != vco)
> > +	if (dev_priv->cdclk_pll.vco != 0 &&
> > +	    dev_priv->cdclk_pll.vco != vco)
> >  		skl_dpll0_disable(dev_priv);
> >  
> > -	if (dev_priv->skl_vco_freq != vco)
> > +	if (dev_priv->cdclk_pll.vco != vco)
> >  		skl_dpll0_enable(dev_priv, vco);
> >  
> >  	I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
> > @@ -5740,20 +5739,20 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
> >  
> >  	skl_sanitize_cdclk(dev_priv);
> >  
> > -	if (dev_priv->cdclk_freq != 0 && dev_priv->skl_vco_freq != 0) {
> > +	if (dev_priv->cdclk_freq > 0 && dev_priv->cdclk_pll.vco > 0) {
> 
> Looks unrelated, could've been part of patch 10/21. In any case:

I think I had some notion of making these signed, but in the end I
didn't, as far as I remember :) So this change can be just dropped.

> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> >  		/*
> >  		 * Use the current vco as out initial
> >  		 * guess as to what the preferred vco is.
> >  		 */
> >  		if (dev_priv->skl_preferred_vco_freq == 0)
> >  			skl_set_preferred_cdclk_vco(dev_priv,
> > -						    dev_priv->skl_vco_freq);
> > +						    dev_priv->cdclk_pll.vco);
> >  		return;
> >  	}
> >  
> >  	vco = dev_priv->skl_preferred_vco_freq;
> >  	if (vco == 0)
> > -		vco = 8100;
> > +		vco = 8100000;
> >  	cdclk = skl_calc_cdclk(0, vco);
> >  
> >  	skl_set_cdclk(dev_priv, cdclk, vco);
> > @@ -5803,7 +5802,7 @@ sanitize:
> >  	/* force cdclk programming */
> >  	dev_priv->cdclk_freq = 0;
> >  	/* force full PLL disable + enable */
> > -	dev_priv->skl_vco_freq = -1;
> > +	dev_priv->cdclk_pll.vco = -1;
> >  }
> >  
> >  /* Adjust CDclk dividers to allow high res or save power if possible */
> > @@ -6646,12 +6645,12 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
> >  
> >  	skl_dpll0_update(dev_priv);
> >  
> > -	if (dev_priv->skl_vco_freq == 0)
> > +	if (dev_priv->cdclk_pll.vco == 0)
> >  		return 24000; /* 24MHz is the cd freq with NSSC ref */
> >  
> >  	cdctl = I915_READ(CDCLK_CTL);
> >  
> > -	if (dev_priv->skl_vco_freq == 8640) {
> > +	if (dev_priv->cdclk_pll.vco == 8640000) {
> >  		switch (cdctl & CDCLK_FREQ_SEL_MASK) {
> >  		case CDCLK_FREQ_450_432:
> >  			return 432000;
> > @@ -13369,7 +13368,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> >  	 */
> >  	if (dev_priv->display.modeset_calc_cdclk) {
> >  		if (!intel_state->cdclk_pll_vco)
> > -			intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
> > +			intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
> >  		if (!intel_state->cdclk_pll_vco)
> >  			intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
> >  
> > @@ -13378,7 +13377,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
> >  			return ret;
> >  
> >  		if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> > -		    intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
> > +		    intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
> >  			ret = intel_modeset_all_pipes(state);
> >  
> >  		if (ret < 0)
> > @@ -13720,7 +13719,7 @@ static int intel_atomic_commit(struct drm_device *dev,
> >  
> >  		if (dev_priv->display.modeset_commit_cdclk &&
> >  		    (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
> > -		     intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
> > +		     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
> >  			dev_priv->display.modeset_commit_cdclk(state);
> >  
> >  		intel_modeset_verify_disabled(dev);
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 908c6f0f7feb..5f9a03651649 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1588,10 +1588,10 @@ found:
> >  		switch (pipe_config->port_clock / 2) {
> >  		case 108000:
> >  		case 216000:
> > -			vco = 8640;
> > +			vco = 8640000;
> >  			break;
> >  		default:
> > -			vco = 8100;
> > +			vco = 8100000;
> >  			break;
> >  		}
> >  

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 14/21] drm/i915: Store cdclk PLL reference clock under dev_priv

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Future platforms will have multiple options for the cdclk PLL reference
> clock, so let's start tracking that under dev_priv alreday on SKL,
> although on SKL it's always 24 MHz.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  2 +-
>  drivers/gpu/drm/i915/intel_display.c | 14 ++++++++------
>  2 files changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8da787cd2227..422f219450c1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1828,7 +1828,7 @@ struct drm_i915_private {
>  	unsigned int czclk_freq;
>  
>  	struct {
> -		unsigned int vco;
> +		unsigned int vco, ref;
>  	} cdclk_pll;
>  
>  	/**
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8bde3ae34869..11e90863533b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5335,8 +5335,9 @@ static void intel_update_cdclk(struct drm_device *dev)
>  	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
>  
>  	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> -		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz\n",
> -				 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco);
> +		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
> +				 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
> +				 dev_priv->cdclk_pll.ref);
>  	else
>  		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
>  				 dev_priv->cdclk_freq);
> @@ -5542,6 +5543,8 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
>  {
>  	u32 val;
>  
> +	dev_priv->cdclk_pll.ref = 24000;
> +
>  	val = I915_READ(LCPLL1_CTL);
>  	if ((val & LCPLL_PLL_ENABLE) == 0) {
>  		dev_priv->cdclk_pll.vco = 0;
> @@ -5730,7 +5733,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
>  
>  void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	skl_set_cdclk(dev_priv, 24000, 0);
> +	skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
>  }
>  
>  void skl_init_cdclk(struct drm_i915_private *dev_priv)
> @@ -6646,7 +6649,7 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
>  	skl_dpll0_update(dev_priv);
>  
>  	if (dev_priv->cdclk_pll.vco == 0)
> -		return 24000; /* 24MHz is the cd freq with NSSC ref */
> +		return dev_priv->cdclk_pll.ref;
>  
>  	cdctl = I915_READ(CDCLK_CTL);
>  
> @@ -6678,8 +6681,7 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
>  		}
>  	}
>  
> -	/* error case, do as if DPLL0 isn't enabled */
> -	return 24000;
> +	return dev_priv->cdclk_pll.ref;
>  }
>  
>  static int broxton_get_display_clock_speed(struct drm_device *dev)
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Re: [PATCH 15/21] drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk()

[Imre Deak]

On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Enabling and disalbing the DE PLL are two nice self contained
> operations, so let's move them into a few small helper functions.
> Makes it easier to see the forest from the trees in broxton_set_cdclk().
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 41 ++++++++++++++++++++++++------------
>  1 file changed, 27 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 11e90863533b..76d59d1214f4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5358,6 +5358,31 @@ static int skl_cdclk_decimal(int cdclk)
>  	return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
>  }
>  
> +static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> +{
> +	I915_WRITE(BXT_DE_PLL_ENABLE, 0);
> +
> +	/* Timeout 200us */
> +	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
> +		DRM_ERROR("timeout waiting for DE PLL unlock\n");
> +}
> +
> +static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio)
> +{
> +	u32 val;
> +
> +	val = I915_READ(BXT_DE_PLL_CTL);
> +	val &= ~BXT_DE_PLL_RATIO_MASK;
> +	val |= ratio;
> +	I915_WRITE(BXT_DE_PLL_CTL, val);
> +
> +	I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
> +
> +	/* Timeout 200us */
> +	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
> +		DRM_ERROR("timeout waiting for DE PLL lock\n");
> +}
> +
>  static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
>  {
>  	uint32_t divider;
> @@ -5425,25 +5450,13 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
>  	 */
>  	if (cdclk == 19200 || cdclk == 624000 ||
>  	    current_cdclk == 624000) {
> -		I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
> -		/* Timeout 200us */
> -		if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
> -			     1))
> -			DRM_ERROR("timout waiting for DE PLL unlock\n");
> +		bxt_de_pll_disable(dev_priv);
>  	}
>  
>  	if (cdclk != 19200) {
>  		uint32_t val;
>  
> -		val = I915_READ(BXT_DE_PLL_CTL);
> -		val &= ~BXT_DE_PLL_RATIO_MASK;
> -		val |= ratio;
> -		I915_WRITE(BXT_DE_PLL_CTL, val);
> -
> -		I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
> -		/* Timeout 200us */
> -		if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
> -			DRM_ERROR("timeout waiting for DE PLL lock\n");
> +		bxt_de_pll_enable(dev_priv, ratio);
>  
>  		val = divider | skl_cdclk_decimal(cdclk);
>  		/*
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Re: [PATCH 16/21] drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv

[Imre Deak]

On Fri, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We have need to know the DE PLL refclk and output frequency in various
> cdclk calculations, so let's store those in dev_priv.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 76d59d1214f4..0d55e8175573 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5334,7 +5334,7 @@ static void intel_update_cdclk(struct drm_device *dev)
>  
>  	dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
>  
> -	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> +	if (INTEL_GEN(dev_priv) >= 9)
>  		DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
>  				 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
>  				 dev_priv->cdclk_pll.ref);
> @@ -5365,6 +5365,8 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
>  	/* Timeout 200us */
>  	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
>  		DRM_ERROR("timeout waiting for DE PLL unlock\n");
> +
> +	dev_priv->cdclk_pll.vco = 0;
>  }
>  
>  static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio)
> @@ -5381,6 +5383,8 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio)
>  	/* Timeout 200us */
>  	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
>  		DRM_ERROR("timeout waiting for DE PLL lock\n");
> +
> +	dev_priv->cdclk_pll.vco = ratio * dev_priv->cdclk_pll.ref;
>  }
>  
>  static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
> @@ -6697,6 +6701,25 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
>  	return dev_priv->cdclk_pll.ref;
>  }
>  
> +static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
> +{
> +	u32 val;
> +
> +	dev_priv->cdclk_pll.ref = 19200;
> +
> +	val = I915_READ(BXT_DE_PLL_ENABLE);
> +	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) {
> +		dev_priv->cdclk_pll.vco = 0;
> +		return;
> +	}
> +
> +	WARN_ON((val & BXT_DE_PLL_LOCK) == 0);
> +
> +	val = I915_READ(BXT_DE_PLL_CTL);
> +	dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
> +		dev_priv->cdclk_pll.ref;
> +}
> +
>  static int broxton_get_display_clock_speed(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -6705,6 +6728,8 @@ static int broxton_get_display_clock_speed(struct drm_device *dev)
>  	uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
>  	int cdclk;
>  
> +	bxt_de_pll_update(dev_priv);
> +
>  	if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
>  		return 19200;
>  
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Re: [PATCH 17/21] drm/i915: Update cached cdclk state from broxton_init_cdclk()

[Imre Deak]

On Fri, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Let's make sure our cached cdclk state is accurate right after
> broxton_init_cdclk() whether or not we end up changing the cdclk
> frequency.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 0d55e8175573..834373503a8d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5508,13 +5508,10 @@ bool broxton_cdclk_verify_state(struct
> drm_i915_private *dev_priv)
>  
>  void broxton_init_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	/* check if cd clock is enabled */
> -	if (broxton_cdclk_is_enabled(dev_priv)) {
> -		DRM_DEBUG_KMS("CDCLK already enabled, won't
> reprogram it\n");
> -		return;
> -	}
> +	intel_update_cdclk(dev_priv->dev);
>  
> -	DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
> +	if (dev_priv->cdclk_pll.vco != 0)
> +		return;
>  
>  	/*
>  	 * FIXME:
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Re: [PATCH 18/21] drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE PLL vco/refclk

[Imre Deak]

On Fri, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Now that we've read out the DE PLL vco and refclk, we can just use them
> in the cdclk calculation. While at it switch over to
> DIV_ROUND_CLOSEST().
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++--------------
>  1 file changed, 19 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 834373503a8d..4542c1f5012f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6720,31 +6720,36 @@ static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
>  static int broxton_get_display_clock_speed(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	uint32_t cdctl = I915_READ(CDCLK_CTL);
> -	uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
> -	uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
> -	int cdclk;
> +	u32 divider;
> +	int div, vco;
>  
>  	bxt_de_pll_update(dev_priv);
>  
> -	if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
> -		return 19200;
> +	vco = dev_priv->cdclk_pll.vco;
> +	if (vco == 0)
> +		return dev_priv->cdclk_pll.ref;
>  
> -	cdclk = 19200 * pll_ratio / 2;
> +	divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
>  
> -	switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
> +	switch (divider) {
>  	case BXT_CDCLK_CD2X_DIV_SEL_1:
> -		return cdclk;  /* 576MHz or 624MHz */
> +		div = 2;
> +		break;
>  	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> -		return cdclk * 2 / 3; /* 384MHz */
> +		div = 3;
> +		break;
>  	case BXT_CDCLK_CD2X_DIV_SEL_2:
> -		return cdclk / 2; /* 288MHz */
> +		div = 4;
> +		break;
>  	case BXT_CDCLK_CD2X_DIV_SEL_4:
> -		return cdclk / 4; /* 144MHz */
> +		div = 8;
> +		break;
> +	default:
> +		MISSING_CASE(divider);
> +		return dev_priv->cdclk_pll.ref;
>  	}
>  
> -	/* error case, do as if DE PLL isn't enabled */
> -	return 19200;
> +	return DIV_ROUND_CLOSEST(vco, div);
>  }
>  
>  static int broadwell_get_display_clock_speed(struct drm_device *dev)
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Re: [PATCH 19/21] drm/i915: Make bxt_set_cdclk() operate in terms of the current vs target DE PLL vco

[Imre Deak]

On Fri, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Make bxt_set_cdclk() more readable by looking at current vs. target
> DE PLL vco to determine if the DE PLL needs disabling and/or enabling.
> We can also calculate the CD2X divider simply as (vco/cdclk) instead of
> depending on magic numbers.
> 
> The magic numbers are still needed though, but only to map the supported
> cdclk frequencies to corresponding DE PLL frequencies.
> 
> Note that w'll now program CDCLK_CTL correctly even for the bypass case.
> Actually the CD2X divider should not matter in that case since the
> hardware will bypass it too, but the "decimal" part should matter (if we
> want to do gmbus/aux with the bypass enabled).

Well, what the bypass can be used for is not defined by the spec
(neither is the decimal value for the bypass freq).

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 128 +++++++++++++++++------------------
>  1 file changed, 63 insertions(+), 65 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4542c1f5012f..14bc14c7827b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5358,6 +5358,30 @@ static int skl_cdclk_decimal(int cdclk)
>  	return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
>  }
>  
> +static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> +{
> +	int ratio;
> +
> +	if (cdclk == dev_priv->cdclk_pll.ref)
> +		return 0;
> +
> +	switch (cdclk) {
> +	default:
> +		MISSING_CASE(cdclk);
> +	case 144000:
> +	case 288000:
> +	case 384000:
> +	case 576000:
> +		ratio = 60;
> +		break;
> +	case 624000:
> +		ratio = 65;
> +		break;
> +	}
> +
> +	return dev_priv->cdclk_pll.ref * ratio;
> +}

We could also check in bxt_de_pll_update() that the VCO is always
either 1152 or 1248MHz.

The patch makes things easier to follow and closer to SKL:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +
>  static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
>  {
>  	I915_WRITE(BXT_DE_PLL_ENABLE, 0);
> @@ -5369,13 +5393,14 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
>  	dev_priv->cdclk_pll.vco = 0;
>  }
>  
> -static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio)
> +static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
>  {
> +	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
>  	u32 val;
>  
>  	val = I915_READ(BXT_DE_PLL_CTL);
>  	val &= ~BXT_DE_PLL_RATIO_MASK;
> -	val |= ratio;
> +	val |= BXT_DE_PLL_RATIO(ratio);
>  	I915_WRITE(BXT_DE_PLL_CTL, val);
>  
>  	I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
> @@ -5384,54 +5409,42 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio)
>  	if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
>  		DRM_ERROR("timeout waiting for DE PLL lock\n");
>  
> -	dev_priv->cdclk_pll.vco = ratio * dev_priv->cdclk_pll.ref;
> +	dev_priv->cdclk_pll.vco = vco;
>  }
>  
>  static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
>  {
> -	uint32_t divider;
> -	uint32_t ratio;
> -	uint32_t current_cdclk;
> -	int ret;
> +	u32 val, divider;
> +	int vco, ret;
>  
> -	/* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
> -	switch (cdclk) {
> -	case 144000:
> +	vco = bxt_de_pll_vco(dev_priv, cdclk);
> +
> +	DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
> +
> +	/* cdclk = vco / 2 / div{1,1.5,2,4} */
> +	switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
> +	case 8:
>  		divider = BXT_CDCLK_CD2X_DIV_SEL_4;
> -		ratio = BXT_DE_PLL_RATIO(60);
>  		break;
> -	case 288000:
> +	case 4:
>  		divider = BXT_CDCLK_CD2X_DIV_SEL_2;
> -		ratio = BXT_DE_PLL_RATIO(60);
>  		break;
> -	case 384000:
> +	case 3:
>  		divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
> -		ratio = BXT_DE_PLL_RATIO(60);
> -		break;
> -	case 576000:
> -		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
> -		ratio = BXT_DE_PLL_RATIO(60);
>  		break;
> -	case 624000:
> +	case 2:
>  		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
> -		ratio = BXT_DE_PLL_RATIO(65);
> -		break;
> -	case 19200:
> -		/*
> -		 * Bypass frequency with DE PLL disabled. Init ratio, divider
> -		 * to suppress GCC warning.
> -		 */
> -		ratio = 0;
> -		divider = 0;
>  		break;
>  	default:
> -		DRM_ERROR("unsupported CDCLK freq %d", cdclk);
> +		WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
> +		WARN_ON(vco != 0);
>  
> -		return;
> +		divider = BXT_CDCLK_CD2X_DIV_SEL_1;
> +		break;
>  	}
>  
> -	mutex_lock(&dev_priv->rps.hw_lock);
>  	/* Inform power controller of upcoming frequency change */
> +	mutex_lock(&dev_priv->rps.hw_lock);
>  	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
>  				      0x80000000);
>  	mutex_unlock(&dev_priv->rps.hw_lock);
> @@ -5442,40 +5455,26 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
>  		return;
>  	}
>  
> -	current_cdclk = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
> -	/* convert from .1 fixpoint MHz with -1MHz offset to kHz */
> -	current_cdclk = current_cdclk * 500 + 1000;
> -
> -	/*
> -	 * DE PLL has to be disabled when
> -	 * - setting to 19.2MHz (bypass, PLL isn't used)
> -	 * - before setting to 624MHz (PLL needs toggling)
> -	 * - before setting to any frequency from 624MHz (PLL needs toggling)
> -	 */
> -	if (cdclk == 19200 || cdclk == 624000 ||
> -	    current_cdclk == 624000) {
> +	if (dev_priv->cdclk_pll.vco != 0 &&
> +	    dev_priv->cdclk_pll.vco != vco)
>  		bxt_de_pll_disable(dev_priv);
> -	}
> -
> -	if (cdclk != 19200) {
> -		uint32_t val;
>  
> -		bxt_de_pll_enable(dev_priv, ratio);
> +	if (dev_priv->cdclk_pll.vco != vco)
> +		bxt_de_pll_enable(dev_priv, vco);
>  
> -		val = divider | skl_cdclk_decimal(cdclk);
> -		/*
> -		 * FIXME if only the cd2x divider needs changing, it could be done
> -		 * without shutting off the pipe (if only one pipe is active).
> -		 */
> -		val |= BXT_CDCLK_CD2X_PIPE_NONE;
> -		/*
> -		 * Disable SSA Precharge when CD clock frequency < 500 MHz,
> -		 * enable otherwise.
> -		 */
> -		if (cdclk >= 500000)
> -			val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
> -		I915_WRITE(CDCLK_CTL, val);
> -	}
> +	val = divider | skl_cdclk_decimal(cdclk);
> +	/*
> +	 * FIXME if only the cd2x divider needs changing, it could be done
> +	 * without shutting off the pipe (if only one pipe is active).
> +	 */
> +	val |= BXT_CDCLK_CD2X_PIPE_NONE;
> +	/*
> +	 * Disable SSA Precharge when CD clock frequency < 500 MHz,
> +	 * enable otherwise.
> +	 */
> +	if (cdclk >= 500000)
> +		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
> +	I915_WRITE(CDCLK_CTL, val);
>  
>  	mutex_lock(&dev_priv->rps.hw_lock);
>  	ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
> @@ -5525,8 +5524,7 @@ void broxton_init_cdclk(struct drm_i915_private *dev_priv)
>  
>  void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
> -	broxton_set_cdclk(dev_priv, 19200);
> +	broxton_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
>  }
>  
>  static int skl_calc_cdclk(int max_pixclk, int vco)
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Re: [PATCH 20/21] drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk check

[Imre Deak]

On Fri, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Rather than having a BXT specific function to make sure the DE PLL is
> enabled after disabling DC6, let's just make sure the current cdclk
> is the same as what we last programmed.
> 
> Having another check in bxt_display_core_init() almost immediately after
> the cdclk init seems redundant, so let's just kill that one.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c    | 15 ---------------
>  drivers/gpu/drm/i915/intel_drv.h        |  1 -
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  8 ++++----
>  3 files changed, 4 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 14bc14c7827b..9725ba59716e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5490,21 +5490,6 @@ static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
>  	intel_update_cdclk(dev_priv->dev);
>  }
>  
> -static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
> -{
> -	if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
> -		return false;
> -
> -	/* TODO: Check for a valid CDCLK rate */
> -
> -	return true;
> -}
> -
> -bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
> -{
> -	return broxton_cdclk_is_enabled(dev_priv);
> -}
> -
>  void broxton_init_cdclk(struct drm_i915_private *dev_priv)
>  {
>  	intel_update_cdclk(dev_priv->dev);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 319e52278d1f..f1f4bde4108d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1270,7 +1270,6 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
>  void hsw_disable_pc8(struct drm_i915_private *dev_priv);
>  void broxton_init_cdclk(struct drm_i915_private *dev_priv);
>  void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
> -bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv);
>  void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
>  void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
>  void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6817a3cb5fbc..b70e123f67ca 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -811,10 +811,11 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
>  {
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
> -	if (IS_BROXTON(dev_priv)) {
> -		broxton_cdclk_verify_state(dev_priv);
> +	WARN_ON(dev_priv->cdclk_freq !=
> +		dev_priv->display.get_display_clock_speed(dev_priv->dev));
> +
> +	if (IS_BROXTON(dev_priv))
>  		broxton_ddi_phy_verify_state(dev_priv);
> -	}
>  }
>  
>  static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> @@ -2288,7 +2289,6 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
>  
>  	broxton_ddi_phy_init(dev_priv);
>  
> -	broxton_cdclk_verify_state(dev_priv);
>  	broxton_ddi_phy_verify_state(dev_priv);
>  
>  	if (resume && dev_priv->csr.dmc_payload)
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Re: [PATCH 21/21] drm/i915: Set BXT cdclk to minimum initially

[Imre Deak]

On Fri, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> In case the driver is initialized without active displays, we should
> just drop the cdclk to the minimum frequency right off the bat. There
> might not be a modeset to drop it to the minimum late rafter all.
> 
> With DMC supposedly we should always have the cdclk up and running.
> The DMC will shut the DE PLL down when appropriate, so let's nuke
> the related FIXMEs as well. Trying to do anything different would
> go against the expectations of the DMC firmware, and we all know
> how fragile the DMC firmware is.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 9 ++-------
>  1 file changed, 2 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9725ba59716e..ac8d448e96d1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -118,6 +118,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc);
>  static void intel_modeset_setup_hw_state(struct drm_device *dev);
>  static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
>  static int ilk_max_pixel_rate(struct drm_atomic_state *state);
> +static int broxton_calc_cdclk(int max_pixclk);
>  
>  struct intel_limit {
>  	struct {
> @@ -5501,10 +5502,8 @@ void broxton_init_cdclk(struct drm_i915_private *dev_priv)
>  	 * FIXME:
>  	 * - The initial CDCLK needs to be read from VBT.
>  	 *   Need to make this change after VBT has changes for BXT.
> -	 * - check if setting the max (or any) cdclk freq is really necessary
> -	 *   here, it belongs to modeset time
>  	 */
> -	broxton_set_cdclk(dev_priv, 624000);
> +	broxton_set_cdclk(dev_priv, broxton_calc_cdclk(0));
>  }
>  
>  void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
> @@ -5944,10 +5943,6 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>  
>  static int broxton_calc_cdclk(int max_pixclk)
>  {
> -	/*
> -	 * FIXME:
> -	 * - set 19.2MHz bypass frequency if there are no active pipes
> -	 */
>  	if (max_pixclk > 576000)
>  		return 624000;
>  	else if (max_pixclk > 384000)
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Re: [PATCH 22/21] drm/i915: Assert the dbuf is enabled when disabling DC5/6

[Imre Deak]

On Mon, 2016-05-16 at 16:59 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Like with cdclk, the DMC is supposed to manage dbuf enabling/disabling.
> Let's make sure it has correctly restored the dbuf state to enabled
> when we disable the DC states.
> 
> Cc: Imre Deak <imre.deak@intel.com>
> Suggested-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index b70e123f67ca..27cb92c18bb5 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -806,6 +806,15 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
>  	return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
>  }
>  
> +static void skl_assert_dbuf_enabled(struct drm_i915_private *dev_priv)

I would've used gen9_ prefix. Either way:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> +{
> +	u32 tmp = I915_READ(DBUF_CTL);
> +
> +	WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
> +	     (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
> +	     "Unexpected DBuf power power state (0x%08x)\n", tmp);
> +}
> +
>  static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
>  					  struct i915_power_well *power_well)
>  {
> @@ -814,6 +823,8 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
>  	WARN_ON(dev_priv->cdclk_freq !=
>  		dev_priv->display.get_display_clock_speed(dev_priv->dev));
>  
> +	skl_assert_dbuf_enabled(dev_priv);
> +
>  	if (IS_BROXTON(dev_priv))
>  		broxton_ddi_phy_verify_state(dev_priv);
>  }
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Re: ✗ Ro.CI.BAT: failure for drm/i915: SKL/KBL/BXT cdclk stuff

[Ville Syrjälä]

On Sat, May 14, 2016 at 05:25:57AM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: SKL/KBL/BXT cdclk stuff
> URL   : https://patchwork.freedesktop.org/series/7169/
> State : failure
> 
> == Summary ==
> 
> Series 7169v1 drm/i915: SKL/KBL/BXT cdclk stuff
> http://patchwork.freedesktop.org/api/1.0/series/7169/revisions/1/mbox
> 
> Test gem_exec_flush:
>         Subgroup basic-batch-kernel-default-cmd:
>                 fail       -> PASS       (ro-byt-n2820)
> Test kms_flip:
>         Subgroup basic-flip-vs-wf_vblank:
>                 pass       -> FAIL       (ro-hsw-i3-4010u)

(kms_flip:8003) DEBUG: name = vblank
last_ts = 626.544176 usec
last_received_ts = 626.543125 usec
last_seq = 623
current_ts = 626.877510 usec
current_received_ts = 626.876400 usec
current_seq = 633
count = 9
seq_step = 10
(kms_flip:8003) CRITICAL: Test assertion failure function check_final_state, file kms_flip.c:1192:
(kms_flip:8003) CRITICAL: Failed assertion: count >= expected * 99/100 && count <= expected * 101/100
(kms_flip:8003) CRITICAL: Last errno: 25, Inappropriate ioctl for device
(kms_flip:8003) CRITICAL: dropped frames, expected 99, counted 100, encoder type 2

https://bugs.freedesktop.org/show_bug.cgi?id=95380

> Test kms_pipe_crc_basic:
>         Subgroup hang-read-crc-pipe-a:
>                 pass       -> DMESG-WARN (ro-ivb2-i7-3770)

[  531.288533] WARNING: CPU: 7 PID: 7836 at drivers/gpu/drm/i915/intel_display.c:13623 intel_atomic_commit+0x13b6/0x1460 [i915]
[  531.288534] pipe A vblank wait timed out

https://bugs.freedesktop.org/show_bug.cgi?id=95125

> 
> ro-bdw-i5-5250u  total:219  pass:181  dwarn:0   dfail:0   fail:0   skip:38 
> ro-bdw-i7-5557U  total:219  pass:206  dwarn:0   dfail:0   fail:0   skip:13 
> ro-bdw-i7-5600u  total:219  pass:187  dwarn:0   dfail:0   fail:0   skip:32 
> ro-bsw-n3050     total:219  pass:175  dwarn:0   dfail:0   fail:2   skip:42 
> ro-byt-n2820     total:218  pass:175  dwarn:0   dfail:0   fail:2   skip:41 
> ro-hsw-i3-4010u  total:218  pass:192  dwarn:0   dfail:0   fail:1   skip:25 
> ro-hsw-i7-4770r  total:219  pass:194  dwarn:0   dfail:0   fail:0   skip:25 
> ro-ilk-i7-620lm  total:219  pass:151  dwarn:0   dfail:0   fail:1   skip:67 
> ro-ilk1-i5-650   total:214  pass:152  dwarn:0   dfail:0   fail:1   skip:61 
> ro-ivb2-i7-3770  total:219  pass:186  dwarn:1   dfail:0   fail:0   skip:32 
> ro-skl-i7-6700hq total:214  pass:190  dwarn:0   dfail:0   fail:0   skip:24 
> ro-snb-i7-2620M  total:219  pass:177  dwarn:0   dfail:0   fail:1   skip:41 
> ro-ivb-i7-3770 failed to connect after reboot
> 
> Results at /archive/results/CI_IGT_test/RO_Patchwork_900/
> 
> 1a536db drm-intel-nightly: 2016y-05m-13d-21h-21m-06s UTC integration manifest
> b974b6b drm/i915: Set BXT cdclk to minimum initially
> c75fe510 drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk check
> ef3fb6c drm/i915: Make bxt_set_cdclk() operate in terms of the current vs target DE PLL vco
> b8ee27d drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE PLL vco/refclk
> 77095f2 drm/i915: Update cached cdclk state from broxton_init_cdclk()
> 7c27fe0 drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv
> 351a2e3 drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk()
> dabb9dd drm/i915: Store cdclk PLL reference clock under dev_priv
> 995467c drm/i915: Rename skl_vco_freq to cdclk_pll.vco
> 19f5564 drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL
> 3499324 drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit
> 75083d8 drm/i915: Unify SKL cdclk init paths
> 0b482fa drm/i915: Beef up skl_sanitize_cdclk() a bit
> 5fe223b drm/i915: Keep track of preferred cdclk vco frequency on SKL
> b878f36 drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL
> 8fbef2c drm/i915: Report the current DPLL0 vco on SKL/KBL
> 244d5cc drm/i915: Actually read out DPLL0 vco on skl from hardware
> 7d03efe drm/i915: Extract skl_calc_cdclk()
> e2cd537 drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config()
> 732fab3 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
> e53fa8e drm/i915: Fix BXT min_pixclk after state readout

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 10/21] drm/i915: Unify SKL cdclk init paths

[Ville Syrjälä]

On Thu, May 19, 2016 at 06:43:32PM +0300, Imre Deak wrote:
> On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Currently we initialize cdclk on SKL from two different places,
> > depending on whether it's during driver init or resume. Let's
> > unify it to happen from the same place always, and that place will be
> > the display core init function.
> > 
> > To do this we first run through the cdclk sanitation code, which will
> > first verify that the PLL is programmed correctly, after which we can
> > read out the current cdclk frequency, and once the cdclk is known we
> > verify that the cdclk "decimal" frequency is programmed correctly. If
> > any of these fail we will force a cdclk change, and to be safe we also
> > force the PLL to be turned off and on again. If the sanitation step
> > didn't notice anything amiss, we'll skip the cdclk programming which
> > will prevent cdclk reprogramming when the displays might be active.
> > 
> > We can also toss in a few WARNs about the register values into
> > skl_update_dpll0() since we now know that the PLL state should
> > always be sane when that function is called.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c    | 40 +++++++++++++++++++++++++--------
> >  drivers/gpu/drm/i915/intel_dpll_mgr.c   | 11 ++-------
> >  drivers/gpu/drm/i915/intel_drv.h        |  1 -
> >  drivers/gpu/drm/i915/intel_runtime_pm.c |  5 +----
> >  4 files changed, 34 insertions(+), 23 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 493160682b2a..da903b718c11 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5577,8 +5577,15 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
> >  		return;
> >  	}
> >  
> > +	WARN_ON((val & LCPLL_PLL_LOCK) == 0);
> > +
> >  	val = I915_READ(DPLL_CTRL1);
> >  
> > +	WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
> > +			DPLL_CTRL1_SSC(SKL_DPLL0) |
> > +			DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
> > +		DPLL_CTRL1_OVERRIDE(SKL_DPLL0));
> > +
> >  	switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
> >  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
> >  	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
> > @@ -5748,6 +5755,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
> >  	intel_update_cdclk(dev);
> >  }
> >  
> > +static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> > +
> >  void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> >  {
> >  	/* disable DBUF power */
> > @@ -5764,10 +5773,19 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> >  
> >  void skl_init_cdclk(struct drm_i915_private *dev_priv)
> >  {
> > -	/* DPLL0 not enabled (happens on early BIOS versions) */
> > -	if (dev_priv->skl_vco_freq == 0) {
> > -		int cdclk, vco;
> > +	int cdclk, vco;
> > +
> > +	skl_sanitize_cdclk(dev_priv);
> >  
> > +	if (dev_priv->cdclk_freq != 0 && dev_priv->skl_vco_freq != 0) {
> > +		/*
> > +		 * Use the current vco as out initial
> 
> typo above.

Fixed while applying.

> 
> Looks ok:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> > +		 * guess as to what the preferred vco is.
> > +		 */
> > +		if (dev_priv->skl_preferred_vco_freq == 0)
> > +			skl_set_preferred_cdclk_vco(dev_priv,
> > +						    dev_priv->skl_vco_freq);
> > +	} else {
> >  		/* set CDCLK to the lowest frequency, Modeset follows */
> >  		vco = dev_priv->skl_preferred_vco_freq;
> >  		if (vco == 0)
> > @@ -5787,7 +5805,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
> >  		DRM_ERROR("DBuf power enable timeout\n");
> >  }
> >  
> > -int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> > +static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> >  {
> >  	uint32_t cdctl, expected;
> >  
> > @@ -5810,6 +5828,8 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> >  	    DPLL_CTRL1_OVERRIDE(SKL_DPLL0))
> >  		goto sanitize;
> >  
> > +	intel_update_cdclk(dev_priv->dev);
> > +
> >  	/* DPLL okay; verify the cdclock
> >  	 *
> >  	 * Noticed in some instances that the freq selection is correct but
> > @@ -5821,13 +5841,15 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> >  		skl_cdclk_decimal(dev_priv->cdclk_freq);
> >  	if (cdctl == expected)
> >  		/* All well; nothing to sanitize */
> > -		return false;
> > -sanitize:
> > +		return;
> >  
> > -	skl_init_cdclk(dev_priv);
> > +sanitize:
> > +	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> >  
> > -	/* we did have to sanitize */
> > -	return true;
> > +	/* force cdclk programming */
> > +	dev_priv->cdclk_freq = 0;
> > +	/* force full PLL disable + enable */
> > +	dev_priv->skl_vco_freq = -1;
> >  }
> >  
> >  /* Adjust CDclk dividers to allow high res or save power if possible */
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index 34ec149fde85..6b70e1eccb13 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -1630,17 +1630,10 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
> >  static void intel_ddi_pll_init(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	uint32_t val = I915_READ(LCPLL_CTL);
> >  
> > -	if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> > -		if (skl_sanitize_cdclk(dev_priv))
> > -			DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
> > +	if (INTEL_GEN(dev_priv) < 9) {
> > +		uint32_t val = I915_READ(LCPLL_CTL);
> >  
> > -		/* We'll want to keep using the current vco from now on */
> > -		if (dev_priv->skl_vco_freq != 0)
> > -			skl_set_preferred_cdclk_vco(dev_priv,
> > -						    dev_priv->skl_vco_freq);
> > -	} else if (!IS_BROXTON(dev_priv)) {
> >  		/*
> >  		 * The LCPLL register should be turned on by the BIOS. For now
> >  		 * let's just check its state and print errors in case
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 8f48a32e991b..319e52278d1f 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1279,7 +1279,6 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv);
> >  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> >  void gen9_enable_dc5(struct drm_i915_private *dev_priv);
> >  void skl_init_cdclk(struct drm_i915_private *dev_priv);
> > -int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> >  void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
> >  unsigned int skl_cdclk_get_vco(unsigned int freq);
> >  void skl_enable_dc6(struct drm_i915_private *dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index b69b935516fb..fefe22c3c163 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -2200,12 +2200,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
> >  
> >  	mutex_unlock(&power_domains->lock);
> >  
> > -	if (!resume)
> > -		return;
> > -
> >  	skl_init_cdclk(dev_priv);
> >  
> > -	if (dev_priv->csr.dmc_payload)
> > +	if (resume && dev_priv->csr.dmc_payload)
> >  		intel_csr_load_program(dev_priv);
> >  }
> >  

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 11/21] drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit

[Ville Syrjälä]

On Thu, May 19, 2016 at 06:48:37PM +0300, Imre Deak wrote:
> On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > SKL and BXT have the same snippets of code for enabling disabling the
> > DBUF. Extract those into helpers and move the calls from
> > init/unit_cdclk() to the display core init/init since this stuff isn't
> > really about cdclk. Also doing the enable twice shouldn't hurt since
> > you're just setting the request bit again when it was already set.
> > 
> > We can also toss in a few WARNs about the register values into
> > skl_get_dpll0_vco() now that we know that things should always be
> > sane there.
> > 
> > Flatten skl_init_cdclk() while at it.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c    | 58 ++++-----------------------------
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 32 ++++++++++++++++++
> >  2 files changed, 38 insertions(+), 52 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index da903b718c11..e908f360da74 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5480,18 +5480,6 @@ static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
> >  
> >  	/* TODO: Check for a valid CDCLK rate */
> >  
> > -	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
> > -		DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
> > -
> > -		return false;
> > -	}
> > -
> > -	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
> > -		DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
> > -
> > -		return false;
> > -	}
> > -
> >  	return true;
> >  }
> >  
> > @@ -5518,26 +5506,10 @@ void broxton_init_cdclk(struct drm_i915_private *dev_priv)
> >  	 *   here, it belongs to modeset time
> >  	 */
> >  	broxton_set_cdclk(dev_priv, 624000);
> > -
> > -	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> > -	POSTING_READ(DBUF_CTL);
> > -
> > -	udelay(10);
> > -
> > -	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
> > -		DRM_ERROR("DBuf power enable timeout!\n");
> >  }
> >  
> >  void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
> >  {
> > -	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
> > -	POSTING_READ(DBUF_CTL);
> > -
> > -	udelay(10);
> > -
> > -	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
> > -		DRM_ERROR("DBuf power disable timeout!\n");
> > -
> >  	/* Set minimum (bypass) frequency, in effect turning off the DE PLL */
> >  	broxton_set_cdclk(dev_priv, 19200);
> >  }
> > @@ -5759,15 +5731,6 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
> >  
> >  void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> >  {
> > -	/* disable DBUF power */
> > -	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
> > -	POSTING_READ(DBUF_CTL);
> > -
> > -	udelay(10);
> > -
> > -	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
> > -		DRM_ERROR("DBuf power disable timeout\n");
> > -
> >  	skl_set_cdclk(dev_priv, 24000, 0);
> >  }
> >  
> > @@ -5785,24 +5748,15 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv)
> >  		if (dev_priv->skl_preferred_vco_freq == 0)
> >  			skl_set_preferred_cdclk_vco(dev_priv,
> >  						    dev_priv->skl_vco_freq);
> > -	} else {
> > -		/* set CDCLK to the lowest frequency, Modeset follows */
> > -		vco = dev_priv->skl_preferred_vco_freq;
> > -		if (vco == 0)
> > -			vco = 8100;
> > -		cdclk = skl_calc_cdclk(0, vco);
> > -
> > -		skl_set_cdclk(dev_priv, cdclk, vco);
> > +		return;
> >  	}
> >  
> > -	/* enable DBUF power */
> > -	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> > -	POSTING_READ(DBUF_CTL);
> > -
> > -	udelay(10);
> > +	vco = dev_priv->skl_preferred_vco_freq;
> > +	if (vco == 0)
> > +		vco = 8100;
> > +	cdclk = skl_calc_cdclk(0, vco);
> >  
> > -	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
> > -		DRM_ERROR("DBuf power enable timeout\n");
> > +	skl_set_cdclk(dev_priv, cdclk, vco);
> >  }
> >  
> >  static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index fefe22c3c163..6817a3cb5fbc 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -2176,6 +2176,28 @@ static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
> >  	mutex_unlock(&power_domains->lock);
> >  }
> >  
> > +static void skl_dbuf_enable(struct drm_i915_private *dev_priv)
> 
> I would've used gen9_ for these, but either way:

Changed while applying.

> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> > +{
> > +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
> > +	POSTING_READ(DBUF_CTL);
> > +
> > +	udelay(10);
> > +
> > +	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
> > +		DRM_ERROR("DBuf power enable timeout\n");
> > +}
> > +
> > +static void skl_dbuf_disable(struct drm_i915_private *dev_priv)
> > +{
> > +	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
> > +	POSTING_READ(DBUF_CTL);
> > +
> > +	udelay(10);
> > +
> > +	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
> > +		DRM_ERROR("DBuf power disable timeout!\n");
> > +}
> > +
> >  static void skl_display_core_init(struct drm_i915_private *dev_priv,
> >  				   bool resume)
> >  {
> > @@ -2202,6 +2224,8 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
> >  
> >  	skl_init_cdclk(dev_priv);
> >  
> > +	skl_dbuf_enable(dev_priv);
> > +
> >  	if (resume && dev_priv->csr.dmc_payload)
> >  		intel_csr_load_program(dev_priv);
> >  }
> > @@ -2213,6 +2237,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
> >  
> >  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >  
> > +	skl_dbuf_disable(dev_priv);
> > +
> >  	skl_uninit_cdclk(dev_priv);
> >  
> >  	/* The spec doesn't call for removing the reset handshake flag */
> > @@ -2257,6 +2283,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
> >  	mutex_unlock(&power_domains->lock);
> >  
> >  	broxton_init_cdclk(dev_priv);
> > +
> > +	skl_dbuf_enable(dev_priv);
> > +
> >  	broxton_ddi_phy_init(dev_priv);
> >  
> >  	broxton_cdclk_verify_state(dev_priv);
> > @@ -2274,6 +2303,9 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
> >  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> >  
> >  	broxton_ddi_phy_uninit(dev_priv);
> > +
> > +	skl_dbuf_disable(dev_priv);
> > +
> >  	broxton_uninit_cdclk(dev_priv);
> >  
> >  	/* The spec doesn't call for removing the reset handshake flag */

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 22/21] drm/i915: Assert the dbuf is enabled when disabling DC5/6

[Ville Syrjälä]

On Thu, May 19, 2016 at 10:49:23PM +0300, Imre Deak wrote:
> On Mon, 2016-05-16 at 16:59 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Like with cdclk, the DMC is supposed to manage dbuf enabling/disabling.
> > Let's make sure it has correctly restored the dbuf state to enabled
> > when we disable the DC states.
> > 
> > Cc: Imre Deak <imre.deak@intel.com>
> > Suggested-by: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index b70e123f67ca..27cb92c18bb5 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -806,6 +806,15 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
> >  	return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> >  }
> >  
> > +static void skl_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
> 
> I would've used gen9_ prefix. Either way:

Changed while applying.

> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> > +{
> > +	u32 tmp = I915_READ(DBUF_CTL);
> > +
> > +	WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
> > +	     (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
> > +	     "Unexpected DBuf power power state (0x%08x)\n", tmp);
> > +}
> > +
> >  static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> >  					  struct i915_power_well *power_well)
> >  {
> > @@ -814,6 +823,8 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> >  	WARN_ON(dev_priv->cdclk_freq !=
> >  		dev_priv->display.get_display_clock_speed(dev_priv->dev));
> >  
> > +	skl_assert_dbuf_enabled(dev_priv);
> > +
> >  	if (IS_BROXTON(dev_priv))
> >  		broxton_ddi_phy_verify_state(dev_priv);
> >  }

-- 
Ville Syrjälä
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Re: [PATCH 00/21] drm/i915: SKL/KBL/BXT cdclk stuff

[Ville Syrjälä]

On Fri, May 13, 2016 at 11:41:19PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Here's my second installment of SKL+ cdclk stuff. I've picked up Clint's latest
> SKL/KBL cdclk patch and expanded on it quite a bit. After this series we're
> capable of actually changing the DPLL0 VCO frequency dynamically, and a lot of
> the code gets a much more uniform feel to it between SKL/KBL vs. BXT. This
> should make it possible to land some future hardware work on top as well,
> without making the code an awful mess.
> 
> Series available here:
> git://github.com/vsyrjala/linux.git skl_bxt_cdclk_part_2
> 
> Clint Taylor (1):
>   drm/i915/skl: SKL CDCLK change on modeset tracking VCO
> 
> Ville Syrjälä (20):
>   drm/i915: Fix BXT min_pixclk after state readout
>   drm/i915: Move the SKL DPLL0 VCO computation into
>     intel_dp_compute_config()
>   drm/i915: Extract skl_calc_cdclk()
>   drm/i915: Actually read out DPLL0 vco on skl from hardware
>   drm/i915: Report the current DPLL0 vco on SKL/KBL
>   drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL
>   drm/i915: Keep track of preferred cdclk vco frequency on SKL
>   drm/i915: Beef up skl_sanitize_cdclk() a bit
>   drm/i915: Unify SKL cdclk init paths
>   drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit
>   drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL
>   drm/i915: Rename skl_vco_freq to cdclk_pll.vco
>   drm/i915: Store cdclk PLL reference clock under dev_priv
>   drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk()
>   drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv
>   drm/i915: Update cached cdclk state from broxton_init_cdclk()
>   drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE
>     PLL vco/refclk
>   drm/i915: Make bxt_set_cdclk() operate in terms of the current vs
>     target DE PLL vco
>   drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk
>     check
>   drm/i915: Set BXT cdclk to minimum initially

Entire series pushed to dinq. Thanks for the reviews.

> 
>  drivers/gpu/drm/i915/i915_drv.h         |   6 +-
>  drivers/gpu/drm/i915/intel_display.c    | 623 +++++++++++++++++++-------------
>  drivers/gpu/drm/i915/intel_dp.c         |  21 ++
>  drivers/gpu/drm/i915/intel_dpll_mgr.c   |  19 +-
>  drivers/gpu/drm/i915/intel_drv.h        |   7 +-
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  45 ++-
>  6 files changed, 443 insertions(+), 278 deletions(-)
> 
> -- 
> 2.7.4

-- 
Ville Syrjälä
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