From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 22/21] drm/i915: Assert the dbuf is enabled when disabling DC5/6
Date: Mon, 23 May 2016 21:21:02 +0300 [thread overview]
Message-ID: <20160523182102.GX4329@intel.com> (raw)
In-Reply-To: <1463687363.31690.29.camel@intel.com>
On Thu, May 19, 2016 at 10:49:23PM +0300, Imre Deak wrote:
> On Mon, 2016-05-16 at 16:59 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Like with cdclk, the DMC is supposed to manage dbuf enabling/disabling.
> > Let's make sure it has correctly restored the dbuf state to enabled
> > when we disable the DC states.
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Suggested-by: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index b70e123f67ca..27cb92c18bb5 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -806,6 +806,15 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
> > return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
> > }
> >
> > +static void skl_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
>
> I would've used gen9_ prefix. Either way:
Changed while applying.
> Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> > +{
> > + u32 tmp = I915_READ(DBUF_CTL);
> > +
> > + WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
> > + (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
> > + "Unexpected DBuf power power state (0x%08x)\n", tmp);
> > +}
> > +
> > static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> > struct i915_power_well *power_well)
> > {
> > @@ -814,6 +823,8 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> > WARN_ON(dev_priv->cdclk_freq !=
> > dev_priv->display.get_display_clock_speed(dev_priv->dev));
> >
> > + skl_assert_dbuf_enabled(dev_priv);
> > +
> > if (IS_BROXTON(dev_priv))
> > broxton_ddi_phy_verify_state(dev_priv);
> > }
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2016-05-23 18:21 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-13 20:41 [PATCH 00/21] drm/i915: SKL/KBL/BXT cdclk stuff ville.syrjala
2016-05-13 20:41 ` [PATCH 01/21] drm/i915: Fix BXT min_pixclk after state readout ville.syrjala
2016-05-17 18:09 ` Imre Deak
2016-05-17 18:21 ` Ville Syrjälä
2016-05-17 18:24 ` Imre Deak
2016-05-13 20:41 ` [PATCH 02/21] drm/i915/skl: SKL CDCLK change on modeset tracking VCO ville.syrjala
2016-05-19 9:08 ` Imre Deak
2016-05-19 9:18 ` Ville Syrjälä
2016-05-13 20:41 ` [PATCH 03/21] drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config() ville.syrjala
2016-05-19 11:57 ` Imre Deak
2016-05-13 20:41 ` [PATCH 04/21] drm/i915: Extract skl_calc_cdclk() ville.syrjala
2016-05-19 12:02 ` Imre Deak
2016-05-13 20:41 ` [PATCH 05/21] drm/i915: Actually read out DPLL0 vco on skl from hardware ville.syrjala
2016-05-19 12:38 ` Imre Deak
2016-05-13 20:41 ` [PATCH 06/21] drm/i915: Report the current DPLL0 vco on SKL/KBL ville.syrjala
2016-05-19 12:40 ` Imre Deak
2016-05-13 20:41 ` [PATCH 07/21] drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL ville.syrjala
2016-05-19 13:04 ` Imre Deak
2016-05-19 13:18 ` Ville Syrjälä
2016-05-19 13:39 ` Imre Deak
2016-05-13 20:41 ` [PATCH 08/21] drm/i915: Keep track of preferred cdclk vco frequency " ville.syrjala
2016-05-19 14:25 ` Imre Deak
2016-05-13 20:41 ` [PATCH 09/21] drm/i915: Beef up skl_sanitize_cdclk() a bit ville.syrjala
2016-05-19 14:30 ` Imre Deak
2016-05-13 20:41 ` [PATCH 10/21] drm/i915: Unify SKL cdclk init paths ville.syrjala
2016-05-19 15:43 ` Imre Deak
2016-05-23 18:20 ` Ville Syrjälä
2016-05-13 20:41 ` [PATCH 11/21] drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit ville.syrjala
2016-05-19 15:48 ` Imre Deak
2016-05-23 18:20 ` Ville Syrjälä
2016-05-13 20:41 ` [PATCH 12/21] drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL ville.syrjala
2016-05-19 16:03 ` Imre Deak
2016-05-13 20:41 ` [PATCH 13/21] drm/i915: Rename skl_vco_freq to cdclk_pll.vco ville.syrjala
2016-05-19 16:17 ` Imre Deak
2016-05-19 16:21 ` Ville Syrjälä
2016-05-13 20:41 ` [PATCH 14/21] drm/i915: Store cdclk PLL reference clock under dev_priv ville.syrjala
2016-05-19 17:00 ` Imre Deak
2016-05-13 20:41 ` [PATCH 15/21] drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk() ville.syrjala
2016-05-19 17:04 ` Imre Deak
2016-05-13 20:41 ` [PATCH 16/21] drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv ville.syrjala
2016-05-19 18:43 ` Imre Deak
2016-05-13 20:41 ` [PATCH 17/21] drm/i915: Update cached cdclk state from broxton_init_cdclk() ville.syrjala
2016-05-19 18:46 ` Imre Deak
2016-05-13 20:41 ` [PATCH 18/21] drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE PLL vco/refclk ville.syrjala
2016-05-19 19:05 ` Imre Deak
2016-05-13 20:41 ` [PATCH 19/21] drm/i915: Make bxt_set_cdclk() operate in terms of the current vs target DE PLL vco ville.syrjala
2016-05-19 19:40 ` Imre Deak
2016-05-13 20:41 ` [PATCH 20/21] drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk check ville.syrjala
2016-05-19 19:41 ` Imre Deak
2016-05-13 20:41 ` [PATCH 21/21] drm/i915: Set BXT cdclk to minimum initially ville.syrjala
2016-05-19 19:45 ` Imre Deak
2016-05-14 5:25 ` ✗ Ro.CI.BAT: failure for drm/i915: SKL/KBL/BXT cdclk stuff Patchwork
2016-05-23 17:25 ` Ville Syrjälä
2016-05-16 13:59 ` [PATCH 22/21] drm/i915: Assert the dbuf is enabled when disabling DC5/6 ville.syrjala
2016-05-19 19:49 ` Imre Deak
2016-05-23 18:21 ` Ville Syrjälä [this message]
2016-05-23 18:21 ` [PATCH 00/21] drm/i915: SKL/KBL/BXT cdclk stuff Ville Syrjälä
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