* ✗ Ro.CI.BAT: failure for drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
2016-06-03 11:40 [PATCH] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear Arun Siluvery
@ 2016-06-03 12:04 ` Patchwork
2016-06-03 12:15 ` Patchwork
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2016-06-03 12:04 UTC (permalink / raw)
To: arun.siluvery; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
URL : https://patchwork.freedesktop.org/series/8218/
State : failure
== Summary ==
Series 8218v1 drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
http://patchwork.freedesktop.org/api/1.0/series/8218/revisions/1/mbox
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass -> INCOMPLETE (fi-hsw-i7-4770k)
fi-hsw-i7-4770k total:196 pass:175 dwarn:0 dfail:0 fail:3 skip:17
ro-ilk-i7-620lm total:1 pass:0 dwarn:0 dfail:0 fail:0 skip:0
fi-bdw-i7-5557u failed to connect after reboot
fi-skl-i5-6260u failed to connect after reboot
fi-skl-i7-6700k failed to connect after reboot
fi-snb-i7-2600 failed to connect after reboot
ro-bdw-i5-5250u failed to connect after reboot
ro-bdw-i7-5557U failed to connect after reboot
ro-bdw-i7-5600u failed to connect after reboot
ro-byt-n2820 failed to connect after reboot
ro-hsw-i3-4010u failed to connect after reboot
ro-hsw-i7-4770r failed to connect after reboot
ro-ilk1-i5-650 failed to connect after reboot
ro-ivb2-i7-3770 failed to connect after reboot
ro-ivb-i7-3770 failed to connect after reboot
ro-skl-i7-6700hq failed to connect after reboot
ro-snb-i7-2620M failed to connect after reboot
Results at /archive/results/CI_IGT_test/RO_Patchwork_1097/
357b87b drm-intel-nightly: 2016y-06m-03d-08h-46m-18s UTC integration manifest
ef9ed8d drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* ✗ Ro.CI.BAT: failure for drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
2016-06-03 11:40 [PATCH] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear Arun Siluvery
2016-06-03 12:04 ` ✗ Ro.CI.BAT: failure for " Patchwork
@ 2016-06-03 12:15 ` Patchwork
2016-06-03 23:34 ` [PATCH] " Jeff McGee
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2016-06-03 12:15 UTC (permalink / raw)
To: arun.siluvery; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
URL : https://patchwork.freedesktop.org/series/8218/
State : failure
== Summary ==
scripts/Makefile.clean:86: recipe for target 'drivers/staging/lustre/lnet/lnet' failed
make[4]: *** [drivers/staging/lustre/lnet/lnet] Terminated
scripts/Makefile.clean:86: recipe for target 'drivers/staging/lustre/lnet' failed
make[3]: *** [drivers/staging/lustre/lnet] Terminated
scripts/Makefile.clean:86: recipe for target 'drivers/staging/lustre' failed
make[2]: *** [drivers/staging/lustre] Terminated
scripts/Makefile.clean:86: recipe for target 'drivers/staging' failed
make[1]: *** [drivers/staging] Terminated
Makefile:1258: recipe for target '_clean_drivers' failed
make: *** [_clean_drivers] Error 2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
2016-06-03 11:40 [PATCH] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear Arun Siluvery
2016-06-03 12:04 ` ✗ Ro.CI.BAT: failure for " Patchwork
2016-06-03 12:15 ` Patchwork
@ 2016-06-03 23:34 ` Jeff McGee
2016-06-06 8:52 ` [RESEND_FOR_CI] " Arun Siluvery
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Jeff McGee @ 2016-06-03 23:34 UTC (permalink / raw)
To: Arun Siluvery; +Cc: intel-gfx
On Fri, Jun 03, 2016 at 12:40:00PM +0100, Arun Siluvery wrote:
> Kernel only need to add a register to HW whitelist, required for a
> preemption related issue.
>
> Reference: HSD#2131039
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e307725..1f6040a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6072,6 +6072,7 @@ enum skl_disp_power_wells {
> #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
>
> #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
> +#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
> #define GEN8_CS_CHICKEN1 _MMIO(0x2580)
>
> /* GEN7 chicken */
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8d35a39..1f9d3a4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -987,6 +987,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> GEN8_LQSC_FLUSH_COHERENT_LINES));
>
> + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
> + ret= wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
> + if (ret)
> + return ret;
> +
> /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
> ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
> if (ret)
> --
> 1.9.1
>
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* [RESEND_FOR_CI] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
2016-06-03 11:40 [PATCH] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear Arun Siluvery
` (2 preceding siblings ...)
2016-06-03 23:34 ` [PATCH] " Jeff McGee
@ 2016-06-06 8:52 ` Arun Siluvery
2016-06-06 9:28 ` ✗ Ro.CI.BAT: warning for drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear (rev2) Patchwork
2017-11-01 22:44 ` [PATCH] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear Chris Wilson
5 siblings, 0 replies; 10+ messages in thread
From: Arun Siluvery @ 2016-06-06 8:52 UTC (permalink / raw)
To: intel-gfx
Kernel only need to add a register to HW whitelist, required for a
preemption related issue.
Reference: HSD#2131039
Reviewed-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dfb4c7a..ee6757e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6072,6 +6072,7 @@ enum skl_disp_power_wells {
#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
+#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
/* GEN7 chicken */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8d35a39..f6e6128 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -987,6 +987,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
+ /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
+ ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
+ if (ret)
+ return ret;
+
/* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
if (ret)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* ✗ Ro.CI.BAT: warning for drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear (rev2)
2016-06-03 11:40 [PATCH] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear Arun Siluvery
` (3 preceding siblings ...)
2016-06-06 8:52 ` [RESEND_FOR_CI] " Arun Siluvery
@ 2016-06-06 9:28 ` Patchwork
2016-06-06 10:03 ` Arun Siluvery
2017-11-01 22:44 ` [PATCH] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear Chris Wilson
5 siblings, 1 reply; 10+ messages in thread
From: Patchwork @ 2016-06-06 9:28 UTC (permalink / raw)
To: arun.siluvery; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear (rev2)
URL : https://patchwork.freedesktop.org/series/8218/
State : warning
== Summary ==
Series 8218v2 drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
http://patchwork.freedesktop.org/api/1.0/series/8218/revisions/2/mbox
Test gem_basic:
Subgroup create-close:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Test gem_busy:
Subgroup basic-parallel-bsd:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Test gem_close_race:
Subgroup basic-threads:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_cs_tlb:
Subgroup basic-default:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Test gem_ctx_param:
Subgroup basic:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_exec_flush:
Subgroup basic-uc-set-default:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_flink_basic:
Subgroup basic:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Test gem_mmap_gtt:
Subgroup basic-small-copy-xy:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup basic-write:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup basic-write-gtt:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_addfb_basic:
Subgroup addfb25-x-tiled-mismatch:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup bad-pitch-65536:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup bo-too-small:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup no-handle:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup too-high:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup unused-modifier:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup unused-offsets:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
fi-bdw-i7-5557u total:102 pass:93 dwarn:0 dfail:0 fail:0 skip:8
fi-hsw-i7-4770k total:209 pass:190 dwarn:0 dfail:0 fail:0 skip:19
fi-skl-i5-6260u total:209 pass:198 dwarn:0 dfail:0 fail:0 skip:11
fi-skl-i7-6700k total:209 pass:184 dwarn:0 dfail:0 fail:0 skip:25
fi-snb-i7-2600 total:209 pass:170 dwarn:0 dfail:0 fail:0 skip:39
ro-bsw-n3050 total:209 pass:168 dwarn:0 dfail:0 fail:2 skip:39
ro-byt-n2820 total:209 pass:169 dwarn:0 dfail:0 fail:3 skip:37
ro-hsw-i3-4010u total:209 pass:186 dwarn:0 dfail:0 fail:0 skip:23
ro-hsw-i7-4770r total:102 pass:82 dwarn:0 dfail:0 fail:0 skip:19
ro-ilk-i7-620lm total:1 pass:0 dwarn:0 dfail:0 fail:0 skip:0
ro-ilk1-i5-650 total:204 pass:146 dwarn:0 dfail:0 fail:1 skip:57
ro-ivb-i7-3770 total:102 pass:75 dwarn:0 dfail:0 fail:0 skip:26
ro-ivb2-i7-3770 total:102 pass:79 dwarn:0 dfail:0 fail:0 skip:22
ro-skl-i7-6700hq total:204 pass:172 dwarn:11 dfail:0 fail:0 skip:21
ro-snb-i7-2620M total:102 pass:72 dwarn:0 dfail:0 fail:0 skip:29
ro-bdw-i5-5250u failed to connect after reboot
ro-bdw-i7-5557U failed to connect after reboot
Results at /archive/results/CI_IGT_test/RO_Patchwork_1118/
1930b31 drm-intel-nightly: 2016y-06m-06d-06h-53m-02s UTC integration manifest
29cf429 drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: ✗ Ro.CI.BAT: warning for drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear (rev2)
2016-06-06 9:28 ` ✗ Ro.CI.BAT: warning for drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear (rev2) Patchwork
@ 2016-06-06 10:03 ` Arun Siluvery
2016-06-06 12:05 ` Tvrtko Ursulin
0 siblings, 1 reply; 10+ messages in thread
From: Arun Siluvery @ 2016-06-06 10:03 UTC (permalink / raw)
To: intel-gfx
On 06/06/2016 14:58, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear (rev2)
> URL : https://patchwork.freedesktop.org/series/8218/
> State : warning
>
> == Summary ==
>
> Series 8218v2 drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
> http://patchwork.freedesktop.org/api/1.0/series/8218/revisions/2/mbox
>
> Test gem_basic:
> Subgroup create-close:
> dmesg-warn -> PASS (ro-skl-i7-6700hq)
> Test gem_busy:
> Subgroup basic-parallel-bsd:
> dmesg-warn -> PASS (ro-skl-i7-6700hq)
> Test gem_close_race:
> Subgroup basic-threads:
> pass -> DMESG-WARN (ro-skl-i7-6700hq)
> Test gem_cs_tlb:
> Subgroup basic-default:
> dmesg-warn -> PASS (ro-skl-i7-6700hq)
> Test gem_ctx_param:
> Subgroup basic:
> pass -> DMESG-WARN (ro-skl-i7-6700hq)
> Test gem_exec_flush:
> Subgroup basic-uc-set-default:
> pass -> DMESG-WARN (ro-skl-i7-6700hq)
> Test gem_flink_basic:
> Subgroup basic:
> dmesg-warn -> PASS (ro-skl-i7-6700hq)
> Test gem_mmap_gtt:
> Subgroup basic-small-copy-xy:
> pass -> DMESG-WARN (ro-skl-i7-6700hq)
> Subgroup basic-write:
> dmesg-warn -> PASS (ro-skl-i7-6700hq)
> Subgroup basic-write-gtt:
> pass -> DMESG-WARN (ro-skl-i7-6700hq)
> Test kms_addfb_basic:
> Subgroup addfb25-x-tiled-mismatch:
> dmesg-warn -> PASS (ro-skl-i7-6700hq)
> Subgroup bad-pitch-65536:
> pass -> DMESG-WARN (ro-skl-i7-6700hq)
> Subgroup bo-too-small:
> pass -> DMESG-WARN (ro-skl-i7-6700hq)
> Subgroup no-handle:
> pass -> DMESG-WARN (ro-skl-i7-6700hq)
> Subgroup too-high:
> dmesg-warn -> PASS (ro-skl-i7-6700hq)
> Subgroup unused-modifier:
> dmesg-warn -> PASS (ro-skl-i7-6700hq)
> Subgroup unused-offsets:
> pass -> DMESG-WARN (ro-skl-i7-6700hq)
>
All dmesg-warn are because of a single known issue,
[BAT SKL] *ERROR* Potential atomic update failure on pipe A
https://bugs.freedesktop.org/show_bug.cgi?id=95632
regards
Arun
> fi-bdw-i7-5557u total:102 pass:93 dwarn:0 dfail:0 fail:0 skip:8
> fi-hsw-i7-4770k total:209 pass:190 dwarn:0 dfail:0 fail:0 skip:19
> fi-skl-i5-6260u total:209 pass:198 dwarn:0 dfail:0 fail:0 skip:11
> fi-skl-i7-6700k total:209 pass:184 dwarn:0 dfail:0 fail:0 skip:25
> fi-snb-i7-2600 total:209 pass:170 dwarn:0 dfail:0 fail:0 skip:39
> ro-bsw-n3050 total:209 pass:168 dwarn:0 dfail:0 fail:2 skip:39
> ro-byt-n2820 total:209 pass:169 dwarn:0 dfail:0 fail:3 skip:37
> ro-hsw-i3-4010u total:209 pass:186 dwarn:0 dfail:0 fail:0 skip:23
> ro-hsw-i7-4770r total:102 pass:82 dwarn:0 dfail:0 fail:0 skip:19
> ro-ilk-i7-620lm total:1 pass:0 dwarn:0 dfail:0 fail:0 skip:0
> ro-ilk1-i5-650 total:204 pass:146 dwarn:0 dfail:0 fail:1 skip:57
> ro-ivb-i7-3770 total:102 pass:75 dwarn:0 dfail:0 fail:0 skip:26
> ro-ivb2-i7-3770 total:102 pass:79 dwarn:0 dfail:0 fail:0 skip:22
> ro-skl-i7-6700hq total:204 pass:172 dwarn:11 dfail:0 fail:0 skip:21
> ro-snb-i7-2620M total:102 pass:72 dwarn:0 dfail:0 fail:0 skip:29
> ro-bdw-i5-5250u failed to connect after reboot
> ro-bdw-i7-5557U failed to connect after reboot
>
> Results at /archive/results/CI_IGT_test/RO_Patchwork_1118/
>
> 1930b31 drm-intel-nightly: 2016y-06m-06d-06h-53m-02s UTC integration manifest
> 29cf429 drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: ✗ Ro.CI.BAT: warning for drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear (rev2)
2016-06-06 10:03 ` Arun Siluvery
@ 2016-06-06 12:05 ` Tvrtko Ursulin
0 siblings, 0 replies; 10+ messages in thread
From: Tvrtko Ursulin @ 2016-06-06 12:05 UTC (permalink / raw)
To: Arun Siluvery, intel-gfx
On 06/06/16 11:03, Arun Siluvery wrote:
> On 06/06/2016 14:58, Patchwork wrote:
>> == Series Details ==
>>
>> Series: drm/i915/gen9: Add
>> WaVFEStateAfterPipeControlwithMediaStateClear (rev2)
>> URL : https://patchwork.freedesktop.org/series/8218/
>> State : warning
>>
>> == Summary ==
>>
>> Series 8218v2 drm/i915/gen9: Add
>> WaVFEStateAfterPipeControlwithMediaStateClear
>> http://patchwork.freedesktop.org/api/1.0/series/8218/revisions/2/mbox
>>
>> Test gem_basic:
>> Subgroup create-close:
>> dmesg-warn -> PASS (ro-skl-i7-6700hq)
>> Test gem_busy:
>> Subgroup basic-parallel-bsd:
>> dmesg-warn -> PASS (ro-skl-i7-6700hq)
>> Test gem_close_race:
>> Subgroup basic-threads:
>> pass -> DMESG-WARN (ro-skl-i7-6700hq)
>> Test gem_cs_tlb:
>> Subgroup basic-default:
>> dmesg-warn -> PASS (ro-skl-i7-6700hq)
>> Test gem_ctx_param:
>> Subgroup basic:
>> pass -> DMESG-WARN (ro-skl-i7-6700hq)
>> Test gem_exec_flush:
>> Subgroup basic-uc-set-default:
>> pass -> DMESG-WARN (ro-skl-i7-6700hq)
>> Test gem_flink_basic:
>> Subgroup basic:
>> dmesg-warn -> PASS (ro-skl-i7-6700hq)
>> Test gem_mmap_gtt:
>> Subgroup basic-small-copy-xy:
>> pass -> DMESG-WARN (ro-skl-i7-6700hq)
>> Subgroup basic-write:
>> dmesg-warn -> PASS (ro-skl-i7-6700hq)
>> Subgroup basic-write-gtt:
>> pass -> DMESG-WARN (ro-skl-i7-6700hq)
>> Test kms_addfb_basic:
>> Subgroup addfb25-x-tiled-mismatch:
>> dmesg-warn -> PASS (ro-skl-i7-6700hq)
>> Subgroup bad-pitch-65536:
>> pass -> DMESG-WARN (ro-skl-i7-6700hq)
>> Subgroup bo-too-small:
>> pass -> DMESG-WARN (ro-skl-i7-6700hq)
>> Subgroup no-handle:
>> pass -> DMESG-WARN (ro-skl-i7-6700hq)
>> Subgroup too-high:
>> dmesg-warn -> PASS (ro-skl-i7-6700hq)
>> Subgroup unused-modifier:
>> dmesg-warn -> PASS (ro-skl-i7-6700hq)
>> Subgroup unused-offsets:
>> pass -> DMESG-WARN (ro-skl-i7-6700hq)
>>
>
> All dmesg-warn are because of a single known issue,
>
> [BAT SKL] *ERROR* Potential atomic update failure on pipe A
> https://bugs.freedesktop.org/show_bug.cgi?id=95632
Merged, thanks for the patch and review.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
2016-06-03 11:40 [PATCH] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear Arun Siluvery
` (4 preceding siblings ...)
2016-06-06 9:28 ` ✗ Ro.CI.BAT: warning for drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear (rev2) Patchwork
@ 2017-11-01 22:44 ` Chris Wilson
2017-11-08 13:03 ` Joonas Lahtinen
5 siblings, 1 reply; 10+ messages in thread
From: Chris Wilson @ 2017-11-01 22:44 UTC (permalink / raw)
To: Arun Siluvery, intel-gfx
Quoting Arun Siluvery (2016-06-03 12:40:00)
> Kernel only need to add a register to HW whitelist, required for a
> preemption related issue.
>
> Reference: HSD#2131039
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e307725..1f6040a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6072,6 +6072,7 @@ enum skl_disp_power_wells {
> #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
>
> #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
> +#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
> #define GEN8_CS_CHICKEN1 _MMIO(0x2580)
>
> /* GEN7 chicken */
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8d35a39..1f9d3a4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -987,6 +987,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> GEN8_LQSC_FLUSH_COHERENT_LINES));
>
> + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
> + ret= wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
> + if (ret)
> + return ret;
What is for exactly? This register is not context saved, so...
-Chris
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear
2017-11-01 22:44 ` [PATCH] drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear Chris Wilson
@ 2017-11-08 13:03 ` Joonas Lahtinen
0 siblings, 0 replies; 10+ messages in thread
From: Joonas Lahtinen @ 2017-11-08 13:03 UTC (permalink / raw)
To: Jeff McGee, Jon Bloomfield; +Cc: intel-gfx
s/Arun/Jeff + Jon/
This W/A would seem to be breaking context isolation as it is not context saved. Thus it is a candidate for being removed.
I have to say I did not get any wiser from reading the HSD, so can you guys bring some insight here?
Regards, Joonas
On Wed, 2017-11-01 at 22:44 +0000, Chris Wilson wrote:
> Quoting Arun Siluvery (2016-06-03 12:40:00)
> > Kernel only need to add a register to HW whitelist, required for a
> > preemption related issue.
> >
> > Reference: HSD#2131039
> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e307725..1f6040a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6072,6 +6072,7 @@ enum skl_disp_power_wells {
> > #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
> >
> > #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
> > +#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
> > #define GEN8_CS_CHICKEN1 _MMIO(0x2580)
> >
> > /* GEN7 chicken */
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 8d35a39..1f9d3a4 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -987,6 +987,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> > GEN8_LQSC_FLUSH_COHERENT_LINES));
> >
> > + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
> > + ret= wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
> > + if (ret)
> > + return ret;
>
> What is for exactly? This register is not context saved, so...
> -Chris
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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^ permalink raw reply [flat|nested] 10+ messages in thread