[PATCH] drm/i915/dsi: fix bxt split screen and color issue

[PATCH] drm/i915/dsi: fix bxt split screen and color issue

[Jani Nikula]

Fix the failure mode where the display appears split, or shifted about
2/3 of the screen, and the color components are cycled. Turns out we
were missing the crucial BXT_DEFEATURE_DPI_FIFO_CTR bit in the
EOT_DISABLE register.

Per bspec, with the bit set, the "mipi_dpf_vblank_start" signal is
asserted only when the complete frame is transferred in the DPHY line
and also the DPI FIFO is flushed out at the end of each frame.

The problem was mitigated by keeping the panel fitter enabled, but that
only limited the issue to a shift of about 0..10 pixels. With the fix
here, the panel fitter workaround does not seem to be needed at all.

While at it, set BXT_DPHY_DEFEATURE_EN in EOT_DISABLE register which is
also needed per the BXT DSI mode set sequence.

Issue: VIZ-7610
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 2 ++
 drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0845059b6a3b..f7b822a86915 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8151,6 +8151,8 @@ enum skl_disp_power_wells {
 #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
 #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
 #define MIPI_EOT_DISABLE(port)		_MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
+#define  BXT_DEFEATURE_DPI_FIFO_CTR			(1 << 9)
+#define  BXT_DPHY_DEFEATURE_EN				(1 << 8)
 #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)
 #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)
 #define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index c70132aa91d5..0f86da048a63 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1172,6 +1172,12 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 	if (intel_dsi->clock_stop)
 		tmp |= CLOCKSTOP;
 
+	if (IS_BROXTON(dev_priv)) {
+		tmp |= BXT_DPHY_DEFEATURE_EN;
+		if (!is_cmd_mode(intel_dsi))
+			tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
+	}
+
 	for_each_dsi_port(port, intel_dsi->ports) {
 		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
 
-- 
2.1.4

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Re: [PATCH] drm/i915/dsi: fix bxt split screen and color issue

[Ville Syrjälä]

On Fri, Jun 03, 2016 at 05:57:05PM +0300, Jani Nikula wrote:
> Fix the failure mode where the display appears split, or shifted about
> 2/3 of the screen, and the color components are cycled. Turns out we
> were missing the crucial BXT_DEFEATURE_DPI_FIFO_CTR bit in the
> EOT_DISABLE register.
> 
> Per bspec, with the bit set, the "mipi_dpf_vblank_start" signal is
> asserted only when the complete frame is transferred in the DPHY line
> and also the DPI FIFO is flushed out at the end of each frame.
> 
> The problem was mitigated by keeping the panel fitter enabled, but that
> only limited the issue to a shift of about 0..10 pixels. With the fix
> here, the panel fitter workaround does not seem to be needed at all.
> 
> While at it, set BXT_DPHY_DEFEATURE_EN in EOT_DISABLE register which is
> also needed per the BXT DSI mode set sequence.
> 
> Issue: VIZ-7610
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I also noticed that we seem to be deviating from the current sequence in
the spec pretty much all the time. I guess it's possible the spec has
been heavily updated since the code was written, but it might make sense
for someone to actually go through  the thing and try to figure out what
else we're missing and/or doing in the wrong order.

> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
>  drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0845059b6a3b..f7b822a86915 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8151,6 +8151,8 @@ enum skl_disp_power_wells {
>  #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
>  #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
>  #define MIPI_EOT_DISABLE(port)		_MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
> +#define  BXT_DEFEATURE_DPI_FIFO_CTR			(1 << 9)
> +#define  BXT_DPHY_DEFEATURE_EN				(1 << 8)
>  #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)
>  #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)
>  #define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index c70132aa91d5..0f86da048a63 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -1172,6 +1172,12 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
>  	if (intel_dsi->clock_stop)
>  		tmp |= CLOCKSTOP;
>  
> +	if (IS_BROXTON(dev_priv)) {
> +		tmp |= BXT_DPHY_DEFEATURE_EN;
> +		if (!is_cmd_mode(intel_dsi))
> +			tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
> +	}
> +
>  	for_each_dsi_port(port, intel_dsi->ports) {
>  		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
>  
> -- 
> 2.1.4

-- 
Ville Syrjälä
Intel OTC
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✗ Ro.CI.BAT: warning for drm/i915/dsi: fix bxt split screen and color issue

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: fix bxt split screen and color issue
URL   : https://patchwork.freedesktop.org/series/8232/
State : warning

== Summary ==

Series 8232v1 drm/i915/dsi: fix bxt split screen and color issue
http://patchwork.freedesktop.org/api/1.0/series/8232/revisions/1/mbox

Test core_auth:
        Subgroup basic-auth:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_cs_tlb:
        Subgroup basic-default:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_ctx_param:
        Subgroup basic-default:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_exec_flush:
        Subgroup basic-batch-kernel-default-cmd:
                fail       -> PASS       (ro-byt-n2820)
        Subgroup basic-uc-set-default:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup basic-wb-pro-default:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup basic-wb-prw-default:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup basic-wb-ro-before-default:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_mmap_gtt:
        Subgroup basic-copy:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_storedw_loop:
        Subgroup basic-render:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test gem_tiled_pread_basic:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_addfb_basic:
        Subgroup addfb25-bad-modifier:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup addfb25-framebuffer-vs-set-tiling:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup framebuffer-vs-set-tiling:
                pass       -> DMESG-WARN (ro-skl-i7-6700hq)
        Subgroup tile-pitch-mismatch:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
        Subgroup too-wide:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)
Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                dmesg-warn -> PASS       (ro-skl-i7-6700hq)

ro-bdw-i5-5250u  total:102  pass:93   dwarn:0   dfail:0   fail:0   skip:8  
ro-byt-n2820     total:209  pass:170  dwarn:0   dfail:0   fail:2   skip:37 
ro-hsw-i3-4010u  total:209  pass:186  dwarn:0   dfail:0   fail:0   skip:23 
ro-hsw-i7-4770r  total:102  pass:82   dwarn:0   dfail:0   fail:0   skip:19 
ro-ilk-i7-620lm  total:1    pass:0    dwarn:0   dfail:0   fail:0   skip:0  
ro-ilk1-i5-650   total:204  pass:146  dwarn:0   dfail:0   fail:1   skip:57 
ro-ivb-i7-3770   total:102  pass:75   dwarn:0   dfail:0   fail:0   skip:26 
ro-ivb2-i7-3770  total:102  pass:79   dwarn:0   dfail:0   fail:0   skip:22 
ro-skl-i7-6700hq total:204  pass:174  dwarn:9   dfail:0   fail:0   skip:21 
ro-snb-i7-2620M  total:102  pass:72   dwarn:0   dfail:0   fail:0   skip:29 
ro-bdw-i7-5557U failed to connect after reboot

Results at /archive/results/CI_IGT_test/RO_Patchwork_1110/

357b87b drm-intel-nightly: 2016y-06m-03d-08h-46m-18s UTC integration manifest
4f42404 drm/i915/dsi: fix bxt split screen and color issue

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Re: [PATCH] drm/i915/dsi: fix bxt split screen and color issue

[Jani Nikula]

On Fri, 03 Jun 2016, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Jun 03, 2016 at 05:57:05PM +0300, Jani Nikula wrote:
>> Fix the failure mode where the display appears split, or shifted about
>> 2/3 of the screen, and the color components are cycled. Turns out we
>> were missing the crucial BXT_DEFEATURE_DPI_FIFO_CTR bit in the
>> EOT_DISABLE register.
>> 
>> Per bspec, with the bit set, the "mipi_dpf_vblank_start" signal is
>> asserted only when the complete frame is transferred in the DPHY line
>> and also the DPI FIFO is flushed out at the end of each frame.
>> 
>> The problem was mitigated by keeping the panel fitter enabled, but that
>> only limited the issue to a shift of about 0..10 pixels. With the fix
>> here, the panel fitter workaround does not seem to be needed at all.
>> 
>> While at it, set BXT_DPHY_DEFEATURE_EN in EOT_DISABLE register which is
>> also needed per the BXT DSI mode set sequence.
>> 
>> Issue: VIZ-7610
>> Cc: Mika Kahola <mika.kahola@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Ramalingam C <ramalingam.c@intel.com>
>> Cc: Uma Shankar <uma.shankar@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pushed to drm-intel-next-queued, thanks for the review.

> I also noticed that we seem to be deviating from the current sequence in
> the spec pretty much all the time. I guess it's possible the spec has
> been heavily updated since the code was written, but it might make sense
> for someone to actually go through  the thing and try to figure out what
> else we're missing and/or doing in the wrong order.

Agreed. Now we'll just have to find that Someone.

BR,
Jani.

>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
>>  drivers/gpu/drm/i915/intel_dsi.c | 6 ++++++
>>  2 files changed, 8 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 0845059b6a3b..f7b822a86915 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -8151,6 +8151,8 @@ enum skl_disp_power_wells {
>>  #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
>>  #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
>>  #define MIPI_EOT_DISABLE(port)		_MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
>> +#define  BXT_DEFEATURE_DPI_FIFO_CTR			(1 << 9)
>> +#define  BXT_DPHY_DEFEATURE_EN				(1 << 8)
>>  #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 7)
>>  #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE		(1 << 6)
>>  #define  LOW_CONTENTION_RECOVERY_DISABLE		(1 << 5)
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index c70132aa91d5..0f86da048a63 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -1172,6 +1172,12 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
>>  	if (intel_dsi->clock_stop)
>>  		tmp |= CLOCKSTOP;
>>  
>> +	if (IS_BROXTON(dev_priv)) {
>> +		tmp |= BXT_DPHY_DEFEATURE_EN;
>> +		if (!is_cmd_mode(intel_dsi))
>> +			tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
>> +	}
>> +
>>  	for_each_dsi_port(port, intel_dsi->ports) {
>>  		I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
>>  
>> -- 
>> 2.1.4

-- 
Jani Nikula, Intel Open Source Technology Center
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