* [PATCH 01/27] drm/i915/skl: Add WaDisableGafsUnitClkGating
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
@ 2016-06-07 14:18 ` Mika Kuoppala
2016-06-07 14:18 ` [PATCH 02/27] drm/i915/kbl: Init gen9 workarounds Mika Kuoppala
` (26 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:18 UTC (permalink / raw)
To: intel-gfx
We need to disable clock gating in this unit to work around
hardware issue causing possible corruption/hang.
v2: name the bit (Ville)
v3: leave the fix enabled for 2227050 and set correct bit (Matthew)
References: HSD#2227156, HSD#2227050
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8f0129d08235..49a319456c48 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6948,6 +6948,7 @@ enum skl_disp_power_wells {
#define GEN7_UCGCTL4 _MMIO(0x940c)
#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
+#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1<<14)
#define GEN6_RCGCTL1 _MMIO(0x9410)
#define GEN6_RCGCTL2 _MMIO(0x9414)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f6e6128b36ca..16e87a828643 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1118,6 +1118,9 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+ /* WaDisableGafsUnitClkGating:skl */
+ WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+
/* WaDisableLSQCROPERFforOCL:skl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
if (ret)
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 02/27] drm/i915/kbl: Init gen9 workarounds
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
2016-06-07 14:18 ` [PATCH 01/27] drm/i915/skl: Add WaDisableGafsUnitClkGating Mika Kuoppala
@ 2016-06-07 14:18 ` Mika Kuoppala
2016-06-07 14:18 ` [PATCH 03/27] drm/i915/kbl: Add REVID macro Mika Kuoppala
` (25 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:18 UTC (permalink / raw)
To: intel-gfx
Kabylake is part of gen9 family so init the generic gen9
workarounds for it.
v2: rebase
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 48 ++++++++++++++++++++++-----------
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 16e87a828643..f97f70fdda7b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -911,21 +911,21 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
uint32_t tmp;
int ret;
- /* WaEnableLbsSlaRetryTimerDecrement:skl */
+ /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
- /* WaDisableKillLogic:bxt,skl */
+ /* WaDisableKillLogic:bxt,skl,kbl */
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
ECOCHK_DIS_TLB);
- /* WaClearFlowControlGpgpuContextSave:skl,bxt */
- /* WaDisablePartialInstShootdown:skl,bxt */
+ /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
+ /* WaDisablePartialInstShootdown:skl,bxt,kbl */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
FLOW_CONTROL_ENABLE |
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
- /* Syncing dependencies between camera and graphics:skl,bxt */
+ /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
@@ -947,18 +947,18 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
*/
}
- /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
- /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt */
+ /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
+ /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
GEN9_ENABLE_YV12_BUGFIX |
GEN9_ENABLE_GPGPU_PREEMPTION);
- /* Wa4x4STCOptimizationDisable:skl,bxt */
- /* WaDisablePartialResolveInVc:skl,bxt */
+ /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
+ /* WaDisablePartialResolveInVc:skl,bxt,kbl */
WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
- /* WaCcsTlbPrefetchDisable:skl,bxt */
+ /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_CCS_TLB_PREFETCH_ENABLE);
@@ -975,15 +975,17 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
- /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
- if (IS_SKYLAKE(dev_priv) || IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
+ /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
+ if (IS_SKYLAKE(dev_priv) ||
+ IS_KABYLAKE(dev_priv) ||
+ IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
- /* WaDisableSTUnitPowerOptimization:skl,bxt */
+ /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
- /* WaOCLCoherentLineFlush:skl,bxt */
+ /* WaOCLCoherentLineFlush:skl,bxt,kbl */
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
@@ -992,12 +994,12 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
if (ret)
return ret;
- /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
+ /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
if (ret)
return ret;
- /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
+ /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
if (ret)
return ret;
@@ -1182,6 +1184,17 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
return 0;
}
+static int kbl_init_workarounds(struct intel_engine_cs *engine)
+{
+ int ret;
+
+ ret = gen9_init_workarounds(engine);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
int init_workarounds_ring(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
@@ -1203,6 +1216,9 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
if (IS_BROXTON(dev_priv))
return bxt_init_workarounds(engine);
+ if (IS_KABYLAKE(dev_priv))
+ return kbl_init_workarounds(engine);
+
return 0;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 03/27] drm/i915/kbl: Add REVID macro
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
2016-06-07 14:18 ` [PATCH 01/27] drm/i915/skl: Add WaDisableGafsUnitClkGating Mika Kuoppala
2016-06-07 14:18 ` [PATCH 02/27] drm/i915/kbl: Init gen9 workarounds Mika Kuoppala
@ 2016-06-07 14:18 ` Mika Kuoppala
2016-06-07 14:18 ` [PATCH 04/27] drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0 Mika Kuoppala
` (24 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:18 UTC (permalink / raw)
To: intel-gfx
Add REVID macro for kbl to limit wa applicability to particular
revision range.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0113207967d9..48dcde57bd23 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2717,6 +2717,12 @@ struct drm_i915_cmd_table {
#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
+#define KBL_REVID_A0 0x0
+#define KBL_REVID_B0 0x1
+
+#define IS_KBL_REVID(p, since, until) \
+ (IS_KABYLAKE(p) && IS_REVID(p, since, until))
+
/*
* The genX designation typically refers to the render engine, so render
* capability related checks should use IS_GEN, while display and other checks
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 04/27] drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (2 preceding siblings ...)
2016-06-07 14:18 ` [PATCH 03/27] drm/i915/kbl: Add REVID macro Mika Kuoppala
@ 2016-06-07 14:18 ` Mika Kuoppala
2016-06-07 14:18 ` [PATCH 05/27] drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent Mika Kuoppala
` (23 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:18 UTC (permalink / raw)
To: intel-gfx
We need this for kbl a0 boards. Note that this should be also
for bxt A0 but we omit that on purpose as bxt A0's are
out of fashion already.
References: HSD#1912158, HSD#4393097
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_gem_stolen.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f9253f2b7ba0..e9cd82290408 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -55,8 +55,10 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
return -ENODEV;
/* See the comment at the drm_mm_init() call for more about this check.
- * WaSkipStolenMemoryFirstPage:bdw,chv (incomplete) */
- if (IS_GEN8(dev_priv) && start < 4096)
+ * WaSkipStolenMemoryFirstPage:bdw,chv,kbl (incomplete)
+ */
+ if (start < 4096 && (IS_GEN8(dev_priv) ||
+ IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)))
start = 4096;
mutex_lock(&dev_priv->mm.stolen_lock);
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 05/27] drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (3 preceding siblings ...)
2016-06-07 14:18 ` [PATCH 04/27] drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0 Mika Kuoppala
@ 2016-06-07 14:18 ` Mika Kuoppala
2016-06-07 14:18 ` [PATCH 06/27] drm/i915: Mimic skl with WaForceEnableNonCoherent Mika Kuoppala
` (22 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:18 UTC (permalink / raw)
To: intel-gfx
The revision id range for this workaround has changed. So apply
it to all revids on all gen9.
References: HSD#2134449
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f97f70fdda7b..7954fe0478b9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -908,7 +908,6 @@ static int chv_init_workarounds(struct intel_engine_cs *engine)
static int gen9_init_workarounds(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- uint32_t tmp;
int ret;
/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
@@ -968,12 +967,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
PIXEL_MASK_CAMMING_DISABLE);
- /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
- tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
- if (IS_SKL_REVID(dev_priv, SKL_REVID_F0, REVID_FOREVER) ||
- IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
- tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
- WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
+ /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
+ HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
if (IS_SKYLAKE(dev_priv) ||
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 06/27] drm/i915: Mimic skl with WaForceEnableNonCoherent
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (4 preceding siblings ...)
2016-06-07 14:18 ` [PATCH 05/27] drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent Mika Kuoppala
@ 2016-06-07 14:18 ` Mika Kuoppala
2016-06-07 14:18 ` [PATCH 07/27] drm/i915/kbl: Add WaEnableGapsTsvCreditFix Mika Kuoppala
` (21 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:18 UTC (permalink / raw)
To: intel-gfx
Past evidence with system hangs and hsds tie
WaForceEnableNonCoherent and WaDisableHDCInvalidation to
WaForceContextSaveRestoreNonCoherent. Documentation
states that WaForceContextSaveRestoreNonCoherent would
not be needed on skl past E0 but evidence proved otherwise. See
commit <510650e8b2ab> ("drm/i915/skl: Fix spurious gpu hang with gt3/gt4
revs"). In this scope consider kbl to be skl with a bigger revision than
E0 so play it safe and bind these two workarounds to the
WaForceContextSaveRestoreNonCoherent, and apply to all gen9.
v2: fix comment (Matthew)
References: HSD#2134449, HSD#2131413
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 37 +++++++++++++++++++--------------
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7954fe0478b9..228c3f75d3c5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -972,6 +972,27 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
+ /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
+ * both tied to WaForceContextSaveRestoreNonCoherent
+ * in some hsds for skl. We keep the tie for all gen9. The
+ * documentation is a bit hazy and so we want to get common behaviour,
+ * even though there is no clear evidence we would need both on kbl/bxt.
+ * This area has been source of system hangs so we play it safe
+ * and mimic the skl regardless of what bspec says.
+ *
+ * Use Force Non-Coherent whenever executing a 3D context. This
+ * is a workaround for a possible hang in the unlikely event
+ * a TLB invalidation occurs during a PSD flush.
+ */
+
+ /* WaForceEnableNonCoherent:skl,bxt,kbl */
+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_FORCE_NON_COHERENT);
+
+ /* WaDisableHDCInvalidation:skl,bxt,kbl */
+ I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
+ BDW_DISABLE_HDC_INVALIDATION);
+
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
if (IS_SKYLAKE(dev_priv) ||
IS_KABYLAKE(dev_priv) ||
@@ -1089,22 +1110,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(HIZ_CHICKEN,
BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
- /* This is tied to WaForceContextSaveRestoreNonCoherent */
- if (IS_SKL_REVID(dev_priv, 0, REVID_FOREVER)) {
- /*
- *Use Force Non-Coherent whenever executing a 3D context. This
- * is a workaround for a possible hang in the unlikely event
- * a TLB invalidation occurs during a PSD flush.
- */
- /* WaForceEnableNonCoherent:skl */
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_FORCE_NON_COHERENT);
-
- /* WaDisableHDCInvalidation:skl */
- I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
- BDW_DISABLE_HDC_INVALIDATION);
- }
-
/* WaBarrierPerformanceFixDisable:skl */
if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
WA_SET_BIT_MASKED(HDC_CHICKEN0,
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 07/27] drm/i915/kbl: Add WaEnableGapsTsvCreditFix
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (5 preceding siblings ...)
2016-06-07 14:18 ` [PATCH 06/27] drm/i915: Mimic skl with WaForceEnableNonCoherent Mika Kuoppala
@ 2016-06-07 14:18 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 08/27] drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0 Mika Kuoppala
` (20 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:18 UTC (permalink / raw)
To: intel-gfx
We need this crucial workaround from skl also to all kbl revisions.
Lack of it was causing system hangs on skl enabling so this is
a must have.
v2: Don't add revid checks to gen9 init workarounds (Arun)
References: HSD#2126660
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 228c3f75d3c5..02edf85f7456 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1188,12 +1188,17 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
static int kbl_init_workarounds(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = engine->i915;
int ret;
ret = gen9_init_workarounds(engine);
if (ret)
return ret;
+ /* WaEnableGapsTsvCreditFix:kbl */
+ I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+ GEN9_GAPS_TSV_CREDIT_DISABLE));
+
return 0;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 08/27] drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (6 preceding siblings ...)
2016-06-07 14:18 ` [PATCH 07/27] drm/i915/kbl: Add WaEnableGapsTsvCreditFix Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 09/27] drm/i915/kbl: Add WaDisableSDEUnitClockGating Mika Kuoppala
` (19 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
Add this workaround for kbl revid A0 only.
v2: rebase
v3: carve out a non related workaround (Chris)
References: HSD#1911714
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 02edf85f7456..55d08fbbf8e3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1199,6 +1199,11 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
GEN9_GAPS_TSV_CREDIT_DISABLE));
+ /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
+ if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_FENCE_DEST_SLM_DISABLE);
+
return 0;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 09/27] drm/i915/kbl: Add WaDisableSDEUnitClockGating
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (7 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 08/27] drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0 Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 10/27] drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw Mika Kuoppala
` (18 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
Add this workaround until upto kbl revid B0.
References: HSD#1802092
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 08274591db7e..be8a96743e86 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6963,11 +6963,25 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
}
+static void kabylake_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /* See Bspec note for PSR2_CTL bit 31, Wa#828:kbl */
+ I915_WRITE(CHICKEN_PAR1_1,
+ I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
+
+ /* WaDisableSDEUnitClockGating:kbl */
+ if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+ I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+ GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+}
+
static void skylake_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,kbl */
+ /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl */
I915_WRITE(CHICKEN_PAR1_1,
I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
}
@@ -7433,7 +7447,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
if (IS_SKYLAKE(dev_priv))
dev_priv->display.init_clock_gating = skylake_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = skylake_init_clock_gating;
+ dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
else if (IS_BROXTON(dev_priv))
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 10/27] drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (8 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 09/27] drm/i915/kbl: Add WaDisableSDEUnitClockGating Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 11/27] drm/i915/kbl: Add WaDisableLSQCROPERFforOCL Mika Kuoppala
` (17 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
According to bspec this workaround helps to reduce lag and improve
performance on edp.
Documentation suggests this for bdw and all gen9. However evidence
shows that this register is missing on gen9 and causing unclaimed mmio
access if we access it. So apply to bdw only where the reg
exists and can hold its value.
v2: drop skl
References: HSD#2134579
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 49a319456c48..7723935d1b54 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6035,6 +6035,9 @@ enum skl_disp_power_wells {
#define FORCE_ARB_IDLE_PLANES (1 << 14)
#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
+#define CHICKEN_PAR2_1 _MMIO(0x42090)
+#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
+
#define _CHICKEN_PIPESL_1_A 0x420b0
#define _CHICKEN_PIPESL_1_B 0x420b4
#define HSW_FBCQ_DIS (1 << 22)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index be8a96743e86..45b304e844dd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7030,6 +7030,10 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
*/
I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
+ /* WaKVMNotificationOnConfigChange:bdw */
+ I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
+ | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
+
lpt_init_clock_gating(dev);
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 11/27] drm/i915/kbl: Add WaDisableLSQCROPERFforOCL
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (9 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 10/27] drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 12/27] drm/i915/gen9: Enable must set chicken bits in config0 reg Mika Kuoppala
` (16 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
Extend the scope of this workaround, already used in skl,
to also take effect in kbl.
v2: Fix KBL_REVID_E0 (Matthew)
References: HSD#2132677
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_lrc.c | 5 +++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +++++++++++++
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 48dcde57bd23..d7b5bbc0d1d4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2719,6 +2719,9 @@ struct drm_i915_cmd_table {
#define KBL_REVID_A0 0x0
#define KBL_REVID_B0 0x1
+#define KBL_REVID_C0 0x2
+#define KBL_REVID_D0 0x3
+#define KBL_REVID_E0 0x4
#define IS_KBL_REVID(p, since, until) \
(IS_KABYLAKE(p) && IS_REVID(p, since, until))
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index cbc84e62bd66..cc41b6717a5d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1075,12 +1075,13 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
/*
- * WaDisableLSQCROPERFforOCL:skl
+ * WaDisableLSQCROPERFforOCL:skl,kbl
* This WA is implemented in skl_init_clock_gating() but since
* this batch updates GEN8_L3SQCREG4 with default value we need to
* set this bit here to retain the WA during flush.
*/
- if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_E0))
+ if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_E0) ||
+ IS_KBL_REVID(engine->i915, 0, KBL_REVID_E0))
l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 55d08fbbf8e3..50379e863ae3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1204,6 +1204,19 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(HDC_CHICKEN0,
HDC_FENCE_DEST_SLM_DISABLE);
+ /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
+ * involving this register should also be added to WA batch as required.
+ */
+ if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
+ /* WaDisableLSQCROPERFforOCL:kbl */
+ I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+ GEN8_LQSC_RO_PERF_DIS);
+
+ /* WaDisableLSQCROPERFforOCL:kbl */
+ ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
+ if (ret)
+ return ret;
+
return 0;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 12/27] drm/i915/gen9: Enable must set chicken bits in config0 reg
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (10 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 11/27] drm/i915/kbl: Add WaDisableLSQCROPERFforOCL Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 13/27] drm/i915/kbl: Add WaDisableGamClockGating Mika Kuoppala
` (15 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
The bspec states that these must be set in CONFIG0 for all gen9.
v2: rebase
v3: fix spacing (Matthew)
References: HSD#2134995
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++++----------
2 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7723935d1b54..6f433de42cac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -220,6 +220,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
+#define GEN8_CONFIG0 _MMIO(0xD00)
+#define GEN9_DEFAULT_FIXES (1 << 3 | 1 << 2 | 1 << 1)
+
#define GAC_ECO_BITS _MMIO(0x14090)
#define ECOBITS_SNB_BIT (1<<13)
#define ECOBITS_PPGTT_CACHE64B (3<<8)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 45b304e844dd..64e161fda2e8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -55,14 +55,24 @@
#define INTEL_RC6p_ENABLE (1<<1)
#define INTEL_RC6pp_ENABLE (1<<2)
-static void bxt_init_clock_gating(struct drm_device *dev)
+static void gen9_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- /* See Bspec note for PSR2_CTL bit 31, Wa#828:bxt */
+ /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
I915_WRITE(CHICKEN_PAR1_1,
I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
+ I915_WRITE(GEN8_CONFIG0,
+ I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
+}
+
+static void bxt_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ gen9_init_clock_gating(dev);
+
/* WaDisableSDEUnitClockGating:bxt */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
@@ -6967,9 +6977,7 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- /* See Bspec note for PSR2_CTL bit 31, Wa#828:kbl */
- I915_WRITE(CHICKEN_PAR1_1,
- I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
+ gen9_init_clock_gating(dev);
/* WaDisableSDEUnitClockGating:kbl */
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
@@ -6979,11 +6987,7 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
static void skylake_init_clock_gating(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
-
- /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl */
- I915_WRITE(CHICKEN_PAR1_1,
- I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
+ gen9_init_clock_gating(dev);
}
static void broadwell_init_clock_gating(struct drm_device *dev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 13/27] drm/i915/kbl: Add WaDisableGamClockGating
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (11 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 12/27] drm/i915/gen9: Enable must set chicken bits in config0 reg Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 14/27] drm/i915/kbl: Add WaDisableDynamicCreditSharing Mika Kuoppala
` (14 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
According to bspec we need to disable gam unit clock gating on
on kbl revids A0 and B0.
References: HSD#2226858, HSD#1944358
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6f433de42cac..b49c39bd8abb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6938,6 +6938,7 @@ enum skl_disp_power_wells {
#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
#define GEN6_UCGCTL1 _MMIO(0x9400)
+# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 64e161fda2e8..afa5eeed5859 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6983,6 +6983,11 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+ /* WaDisableGamClockGating:kbl */
+ if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+ I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
+ GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
}
static void skylake_init_clock_gating(struct drm_device *dev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 14/27] drm/i915/kbl: Add WaDisableDynamicCreditSharing
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (12 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 13/27] drm/i915/kbl: Add WaDisableGamClockGating Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 15/27] drm/i915: Add WaInsertDummyPushConstP for bxt and kbl Mika Kuoppala
` (13 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
Bspec states that we need to turn off dynamic credit
sharing on kbl revid a0 and b0. This happens by writing bit 28
on 0x4ab8.
References: HSD#2225601, HSD#2226938, HSD#2225763
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b49c39bd8abb..eb9875883379 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1672,6 +1672,9 @@ enum skl_disp_power_wells {
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
+#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
+#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
+
#if 0
#define PRB0_TAIL _MMIO(0x2030)
#define PRB0_HEAD _MMIO(0x2034)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 50379e863ae3..d1c02ed20f37 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1199,6 +1199,11 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
GEN9_GAPS_TSV_CREDIT_DISABLE));
+ /* WaDisableDynamicCreditSharing:kbl */
+ if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+ WA_SET_BIT(GAMT_CHKN_BIT_REG,
+ GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
+
/* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
WA_SET_BIT_MASKED(HDC_CHICKEN0,
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 15/27] drm/i915: Add WaInsertDummyPushConstP for bxt and kbl
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (13 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 14/27] drm/i915/kbl: Add WaDisableDynamicCreditSharing Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 16/27] drm/i915/gen9: Add WaDisableSkipCaching Mika Kuoppala
` (12 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
Add this workaround for both bxt and kbl up to until
rev B0.
References: HSD#2136703
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eb9875883379..1a9d76dd5550 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6089,6 +6089,7 @@ enum skl_disp_power_wells {
# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
+# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
#define HIZ_CHICKEN _MMIO(0x7018)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d1c02ed20f37..a397b876da2c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1183,6 +1183,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
L3_HIGH_PRIO_CREDITS(2));
+ /* WaInsertDummyPushConstPs:bxt */
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+
return 0;
}
@@ -1217,6 +1222,11 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_RO_PERF_DIS);
+ /* WaInsertDummyPushConstPs:kbl */
+ if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+
/* WaDisableLSQCROPERFforOCL:kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
if (ret)
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 16/27] drm/i915/gen9: Add WaDisableSkipCaching
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (14 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 15/27] drm/i915: Add WaInsertDummyPushConstP for bxt and kbl Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 17/27] drm/i915/skl: Add WAC6entrylatency Mika Kuoppala
` (11 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
Make sure that we never enable skip caching on gen9 by
accident.
References: HSD#2134698
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/intel_mocs.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index b765c75f3fcd..8f96c40e415c 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -156,6 +156,16 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
"Platform that should have a MOCS table does not.\n");
}
+ /* WaDisableSkipCaching:skl,bxt,kbl */
+ if (IS_GEN9(dev_priv)) {
+ int i;
+
+ for (i = 0; i < table->size; i++)
+ if (WARN_ON(table->table[i].l3cc_value &
+ (L3_ESC(1) || L3_SCC(0x7))))
+ return false;
+ }
+
return result;
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 17/27] drm/i915/skl: Add WAC6entrylatency
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (15 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 16/27] drm/i915/gen9: Add WaDisableSkipCaching Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 18/27] drm/i915/kbl: Add WaForGAMHang Mika Kuoppala
` (10 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
This workaround is for fbc working with rc6 on skylake. Bspec
states that setting this bit needs to be coordinated with uncore
but offers no further details.
v2: rebase
References: HSD#4712857
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a9d76dd5550..e0c2bd93a0ac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2167,6 +2167,9 @@ enum skl_disp_power_wells {
#define FBC_LL_SIZE (1536)
+#define FBC_LLC_READ_CTRL _MMIO(0x9044)
+#define FBC_LLC_FULLY_OPEN (1<<30)
+
/* Framebuffer compression for GM45+ */
#define DPFC_CB_BASE _MMIO(0x3200)
#define DPFC_CONTROL _MMIO(0x3208)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index afa5eeed5859..d8eb23f0ccbf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6992,7 +6992,13 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
static void skylake_init_clock_gating(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
gen9_init_clock_gating(dev);
+
+ /* WAC6entrylatency:skl */
+ I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
+ FBC_LLC_FULLY_OPEN);
}
static void broadwell_init_clock_gating(struct drm_device *dev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 18/27] drm/i915/kbl: Add WaForGAMHang
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (16 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 17/27] drm/i915/skl: Add WAC6entrylatency Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 19/27] drm/i915/kbl: Add WaDisableGafsUnitClkGating Mika Kuoppala
` (9 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
Add this workaround for A0 and B0 revisions
References: HSD#2226935
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 36 ++++++++++++++++++++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index cc41b6717a5d..6342b5a1c14e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1652,9 +1652,10 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
struct intel_ringbuffer *ringbuf = request->ringbuf;
struct intel_engine_cs *engine = ringbuf->engine;
u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
- bool vf_flush_wa = false;
+ bool vf_flush_wa = false, dc_flush_wa = false;
u32 flags = 0;
int ret;
+ int len;
flags |= PIPE_CONTROL_CS_STALL;
@@ -1681,9 +1682,21 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
*/
if (IS_GEN9(request->i915))
vf_flush_wa = true;
+
+ /* WaForGAMHang:kbl */
+ if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
+ dc_flush_wa = true;
}
- ret = intel_ring_begin(request, vf_flush_wa ? 12 : 6);
+ len = 6;
+
+ if (vf_flush_wa)
+ len += 6;
+
+ if (dc_flush_wa)
+ len += 12;
+
+ ret = intel_ring_begin(request, len);
if (ret)
return ret;
@@ -1696,12 +1709,31 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
intel_logical_ring_emit(ringbuf, 0);
}
+ if (dc_flush_wa) {
+ intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
+ intel_logical_ring_emit(ringbuf, PIPE_CONTROL_DC_FLUSH_ENABLE);
+ intel_logical_ring_emit(ringbuf, 0);
+ intel_logical_ring_emit(ringbuf, 0);
+ intel_logical_ring_emit(ringbuf, 0);
+ intel_logical_ring_emit(ringbuf, 0);
+ }
+
intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
intel_logical_ring_emit(ringbuf, flags);
intel_logical_ring_emit(ringbuf, scratch_addr);
intel_logical_ring_emit(ringbuf, 0);
intel_logical_ring_emit(ringbuf, 0);
intel_logical_ring_emit(ringbuf, 0);
+
+ if (dc_flush_wa) {
+ intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
+ intel_logical_ring_emit(ringbuf, PIPE_CONTROL_CS_STALL);
+ intel_logical_ring_emit(ringbuf, 0);
+ intel_logical_ring_emit(ringbuf, 0);
+ intel_logical_ring_emit(ringbuf, 0);
+ intel_logical_ring_emit(ringbuf, 0);
+ }
+
intel_logical_ring_advance(ringbuf);
return 0;
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 19/27] drm/i915/kbl: Add WaDisableGafsUnitClkGating
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (17 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 18/27] drm/i915/kbl: Add WaForGAMHang Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 20/27] drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing Mika Kuoppala
` (8 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
We need to disable clock gating in this unit to work around
hardware issue causing possible corruption/hang.
v2: name the bit (Ville)
v3: leave the fix enabled for 2227050 and set correct bit (Matthew)
v4: Split out the skl part in separate commit for easier backport
References: HSD#2227156, HSD#2227050
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a397b876da2c..b6b181befa91 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1227,6 +1227,9 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+ /* WaDisableGafsUnitClkGating:kbl */
+ WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+
/* WaDisableLSQCROPERFforOCL:kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
if (ret)
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 20/27] drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (18 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 19/27] drm/i915/kbl: Add WaDisableGafsUnitClkGating Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 21/27] drm/i915/gen9: Add WaEnableChickenDCPR Mika Kuoppala
` (7 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
This is needed for all kbl revision.
v2: Don't add revid checks to generic gen9 init (Arun)
References: HSD#2135593
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b6b181befa91..9169f589cfcb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1230,6 +1230,11 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
/* WaDisableGafsUnitClkGating:kbl */
WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
+ /* WaDisableSbeCacheDispatchPortSharing:kbl */
+ WA_SET_BIT_MASKED(
+ GEN7_HALF_SLICE_CHICKEN1,
+ GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+
/* WaDisableLSQCROPERFforOCL:kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
if (ret)
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 21/27] drm/i915/gen9: Add WaEnableChickenDCPR
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (19 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 20/27] drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 22/27] drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS Mika Kuoppala
` (6 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
Workaround for display underrun issues with Y & Yf Tiling.
Set this on all gen9 as stated by bspec.
v2: proper workaround name
References: HSD#2136383, BSID#857
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e0c2bd93a0ac..550b492de863 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6067,6 +6067,9 @@ enum skl_disp_power_wells {
#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
+#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
+#define MASK_WAKEMEM (1<<13)
+
#define SKL_DFSM _MMIO(0x51000)
#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d8eb23f0ccbf..d766d1a562df 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -65,6 +65,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
I915_WRITE(GEN8_CONFIG0,
I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
+
+ /* WaEnableChickenDCPR:skl,bxt,kbl */
+ I915_WRITE(GEN8_CHICKEN_DCPR_1,
+ I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
}
static void bxt_init_clock_gating(struct drm_device *dev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 22/27] drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (20 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 21/27] drm/i915/gen9: Add WaEnableChickenDCPR Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 23/27] drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch Mika Kuoppala
` (5 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
There is ambiguity in the documentation between D0 and E0.
Extend this workaround to E0.
References: BSID#779
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9169f589cfcb..cf8d0bf29a97 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1085,7 +1085,7 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
}
- if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0)) {
+ if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {
/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
I915_WRITE(FF_SLICE_CS_CHICKEN2,
_MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 23/27] drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (21 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 22/27] drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 24/27] drm/i915/gen9: Add WaFbcTurnOffFbcWatermark Mika Kuoppala
` (4 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
This workaround for bdw and chv, is also needed for kbl A0.
References: HSD#1911519, BSID#569
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6342b5a1c14e..4fad8303648e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1255,6 +1255,22 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
return ret;
index = ret;
+ /* WaClearSlmSpaceAtContextSwitch:kbl */
+ /* Actual scratch location is at 128 bytes offset */
+ if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
+ uint32_t scratch_addr
+ = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
+
+ wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
+ wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
+ PIPE_CONTROL_GLOBAL_GTT_IVB |
+ PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_QW_WRITE));
+ wa_ctx_emit(batch, index, scratch_addr);
+ wa_ctx_emit(batch, index, 0);
+ wa_ctx_emit(batch, index, 0);
+ wa_ctx_emit(batch, index, 0);
+ }
/* Pad to end of cacheline */
while (index % CACHELINE_DWORDS)
wa_ctx_emit(batch, index, MI_NOOP);
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 24/27] drm/i915/gen9: Add WaFbcTurnOffFbcWatermark
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (22 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 23/27] drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 25/27] drm/i915/gen9: Add WaFbcWakeMemOn Mika Kuoppala
` (3 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
According to bspec this prevents screen corruption when fbc is
used.
v2: This workaround has a name, use it (Ville)
v3: remove bogus gen check on ilk/vlv wm path (Ville)
References: HSD#2135555, HSD#2137270, BSID#562
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d766d1a562df..de3dd241e151 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -69,6 +69,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
/* WaEnableChickenDCPR:skl,bxt,kbl */
I915_WRITE(GEN8_CHICKEN_DCPR_1,
I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
+
+ /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
+ I915_WRITE(DISP_ARB_CTL,
+ I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
}
static void bxt_init_clock_gating(struct drm_device *dev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 25/27] drm/i915/gen9: Add WaFbcWakeMemOn
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (23 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 24/27] drm/i915/gen9: Add WaFbcTurnOffFbcWatermark Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 26/27] drm/i195/fbc: Add WaFbcNukeOnHostModify Mika Kuoppala
` (2 subsequent siblings)
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Set bit 8 in 0x43224 to prevent screen corruption and system
hangs on high memory bandwidth conditions. The same wa also suggest
setting bit 31 on ARB_CTL. According to another workaround we gain
better idle power savings when FBC is enabled.
v2: use correct workaround name
v3: split out overlapping wa for corruption avoidance (Ville)
References: HSD#2137218, HSD#2227171, HSD#2136579, BSID#883
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 550b492de863..9206fdc3113b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6054,6 +6054,7 @@ enum skl_disp_power_wells {
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
#define DISP_ARB_CTL _MMIO(0x45000)
+#define DISP_FBC_MEMORY_WAKE (1<<31)
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
#define DISP_FBC_WM_DIS (1<<15)
#define DISP_ARB_CTL2 _MMIO(0x45004)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index de3dd241e151..8df9b5288679 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -71,8 +71,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
- I915_WRITE(DISP_ARB_CTL,
- I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
+ /* WaFbcWakeMemOn:skl,bxt,kbl */
+ I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
+ DISP_FBC_WM_DIS |
+ DISP_FBC_MEMORY_WAKE);
}
static void bxt_init_clock_gating(struct drm_device *dev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 26/27] drm/i195/fbc: Add WaFbcNukeOnHostModify
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (24 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 25/27] drm/i915/gen9: Add WaFbcWakeMemOn Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 14:19 ` [PATCH 27/27] drm/i915/gen9: Add WaFbcHighMemBwCorruptionAvoidance Mika Kuoppala
2016-06-07 14:52 ` ✓ Ro.CI.BAT: success for gen9 workarounds v3 Patchwork
27 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
Bspec states that we need to set nuke on modify all to prevent
screen corruption with fbc on skl and kbl.
v2: proper workaround name
References: HSD#2227109, HSDES#1404569388
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9206fdc3113b..f6a140b2c77c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2209,6 +2209,7 @@ enum skl_disp_power_wells {
#define ILK_DPFC_STATUS _MMIO(0x43210)
#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
#define ILK_DPFC_CHICKEN _MMIO(0x43224)
+#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
#define ILK_FBC_RT_BASE _MMIO(0x2128)
#define ILK_FBC_RT_VALID (1<<0)
#define SNB_FBC_FRONT_BUFFER (1<<1)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8df9b5288679..1464d7ba69d4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6998,6 +6998,10 @@ static void kabylake_init_clock_gating(struct drm_device *dev)
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
+
+ /* WaFbcNukeOnHostModify:kbl */
+ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+ ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
}
static void skylake_init_clock_gating(struct drm_device *dev)
@@ -7009,6 +7013,10 @@ static void skylake_init_clock_gating(struct drm_device *dev)
/* WAC6entrylatency:skl */
I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
FBC_LLC_FULLY_OPEN);
+
+ /* WaFbcNukeOnHostModify:skl */
+ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+ ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
}
static void broadwell_init_clock_gating(struct drm_device *dev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 27/27] drm/i915/gen9: Add WaFbcHighMemBwCorruptionAvoidance
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (25 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 26/27] drm/i195/fbc: Add WaFbcNukeOnHostModify Mika Kuoppala
@ 2016-06-07 14:19 ` Mika Kuoppala
2016-06-07 16:04 ` Ville Syrjälä
2016-06-07 14:52 ` ✓ Ro.CI.BAT: success for gen9 workarounds v3 Patchwork
27 siblings, 1 reply; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-07 14:19 UTC (permalink / raw)
To: intel-gfx
Add this fbc related workaround for all gen9
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6a140b2c77c..81d1896f158c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2209,6 +2209,7 @@ enum skl_disp_power_wells {
#define ILK_DPFC_STATUS _MMIO(0x43210)
#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
#define ILK_DPFC_CHICKEN _MMIO(0x43224)
+#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
#define ILK_FBC_RT_BASE _MMIO(0x2128)
#define ILK_FBC_RT_VALID (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1464d7ba69d4..658a75659657 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -75,6 +75,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
DISP_FBC_WM_DIS |
DISP_FBC_MEMORY_WAKE);
+
+ /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
+ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
+ ILK_DPFC_DISABLE_DUMMY0);
}
static void bxt_init_clock_gating(struct drm_device *dev)
--
2.7.4
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^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH 27/27] drm/i915/gen9: Add WaFbcHighMemBwCorruptionAvoidance
2016-06-07 14:19 ` [PATCH 27/27] drm/i915/gen9: Add WaFbcHighMemBwCorruptionAvoidance Mika Kuoppala
@ 2016-06-07 16:04 ` Ville Syrjälä
2016-06-08 14:29 ` Mika Kuoppala
0 siblings, 1 reply; 34+ messages in thread
From: Ville Syrjälä @ 2016-06-07 16:04 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
On Tue, Jun 07, 2016 at 05:19:19PM +0300, Mika Kuoppala wrote:
> Add this fbc related workaround for all gen9
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f6a140b2c77c..81d1896f158c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2209,6 +2209,7 @@ enum skl_disp_power_wells {
> #define ILK_DPFC_STATUS _MMIO(0x43210)
> #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
> #define ILK_DPFC_CHICKEN _MMIO(0x43224)
> +#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
> #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
> #define ILK_FBC_RT_BASE _MMIO(0x2128)
> #define ILK_FBC_RT_VALID (1<<0)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1464d7ba69d4..658a75659657 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -75,6 +75,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
> I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> DISP_FBC_WM_DIS |
> DISP_FBC_MEMORY_WAKE);
> +
> + /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
> + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> + ILK_DPFC_DISABLE_DUMMY0);
> }
>
> static void bxt_init_clock_gating(struct drm_device *dev)
> --
> 2.7.4
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 27/27] drm/i915/gen9: Add WaFbcHighMemBwCorruptionAvoidance
2016-06-07 16:04 ` Ville Syrjälä
@ 2016-06-08 14:29 ` Mika Kuoppala
0 siblings, 0 replies; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-08 14:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Ville Syrjälä <ville.syrjala@linux.intel.com> writes:
> [ text/plain ]
> On Tue, Jun 07, 2016 at 05:19:19PM +0300, Mika Kuoppala wrote:
>> Add this fbc related workaround for all gen9
>>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
All patches pushed to dinq. Ty all for review.
-Mika
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>> 2 files changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index f6a140b2c77c..81d1896f158c 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2209,6 +2209,7 @@ enum skl_disp_power_wells {
>> #define ILK_DPFC_STATUS _MMIO(0x43210)
>> #define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
>> #define ILK_DPFC_CHICKEN _MMIO(0x43224)
>> +#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
>> #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
>> #define ILK_FBC_RT_BASE _MMIO(0x2128)
>> #define ILK_FBC_RT_VALID (1<<0)
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 1464d7ba69d4..658a75659657 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -75,6 +75,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>> I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>> DISP_FBC_WM_DIS |
>> DISP_FBC_MEMORY_WAKE);
>> +
>> + /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
>> + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>> + ILK_DPFC_DISABLE_DUMMY0);
>> }
>>
>> static void bxt_init_clock_gating(struct drm_device *dev)
>> --
>> 2.7.4
>
> --
> Ville Syrjälä
> Intel OTC
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^ permalink raw reply [flat|nested] 34+ messages in thread
* ✓ Ro.CI.BAT: success for gen9 workarounds v3
2016-06-07 14:18 [PATCH 00/27] gen9 workarounds v3 Mika Kuoppala
` (26 preceding siblings ...)
2016-06-07 14:19 ` [PATCH 27/27] drm/i915/gen9: Add WaFbcHighMemBwCorruptionAvoidance Mika Kuoppala
@ 2016-06-07 14:52 ` Patchwork
2016-06-08 0:06 ` Chris Wilson
27 siblings, 1 reply; 34+ messages in thread
From: Patchwork @ 2016-06-07 14:52 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: gen9 workarounds v3
URL : https://patchwork.freedesktop.org/series/8405/
State : success
== Summary ==
Series 8405v1 gen9 workarounds v3
http://patchwork.freedesktop.org/api/1.0/series/8405/revisions/1/mbox
fi-bdw-i7-5557u total:102 pass:93 dwarn:0 dfail:0 fail:0 skip:8
fi-hsw-i7-4770k total:209 pass:190 dwarn:0 dfail:0 fail:0 skip:19
fi-skl-i5-6260u total:209 pass:198 dwarn:0 dfail:0 fail:0 skip:11
fi-skl-i7-6700k total:209 pass:184 dwarn:0 dfail:0 fail:0 skip:25
fi-snb-i7-2600 total:209 pass:170 dwarn:0 dfail:0 fail:0 skip:39
ro-bdw-i5-5250u total:49 pass:48 dwarn:0 dfail:0 fail:0 skip:1
ro-bdw-i7-5600u total:183 pass:154 dwarn:0 dfail:0 fail:0 skip:28
ro-bsw-n3050 total:208 pass:167 dwarn:0 dfail:0 fail:2 skip:39
ro-byt-n2820 total:208 pass:168 dwarn:0 dfail:0 fail:3 skip:37
ro-hsw-i3-4010u total:208 pass:185 dwarn:0 dfail:0 fail:0 skip:23
ro-hsw-i7-4770r total:183 pass:161 dwarn:0 dfail:0 fail:0 skip:21
ro-ilk1-i5-650 total:204 pass:146 dwarn:0 dfail:0 fail:1 skip:57
ro-ivb-i7-3770 total:183 pass:154 dwarn:0 dfail:0 fail:0 skip:28
ro-ivb2-i7-3770 total:183 pass:158 dwarn:0 dfail:0 fail:0 skip:24
ro-snb-i7-2620M total:183 pass:151 dwarn:0 dfail:0 fail:0 skip:31
ro-bdw-i5-5250u failed to connect after reboot
ro-bdw-i7-5557U failed to connect after reboot
Results at /archive/results/CI_IGT_test/RO_Patchwork_1130/
7a56b20 drm-intel-nightly: 2016y-06m-07d-13h-33m-10s UTC integration manifest
5b229fe drm/i915/gen9: Add WaFbcHighMemBwCorruptionAvoidance
e0cab26 drm/i195/fbc: Add WaFbcNukeOnHostModify
a9bc304 drm/i915/gen9: Add WaFbcWakeMemOn
d450b2f drm/i915/gen9: Add WaFbcTurnOffFbcWatermark
f76f7de drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch
c66f685 drm/i915/skl: Extend WaDisableChickenBitTSGBarrierAckForFFSliceCS
b294691 drm/i915/gen9: Add WaEnableChickenDCPR
ee60d11 drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing
ca24ad1 drm/i915/kbl: Add WaDisableGafsUnitClkGating
7d50be6 drm/i915/kbl: Add WaForGAMHang
7708e87 drm/i915/skl: Add WAC6entrylatency
941f192 drm/i915/gen9: Add WaDisableSkipCaching
717a20b drm/i915: Add WaInsertDummyPushConstP for bxt and kbl
ab38b16 drm/i915/kbl: Add WaDisableDynamicCreditSharing
f56a917 drm/i915/kbl: Add WaDisableGamClockGating
f745cdc drm/i915/gen9: Enable must set chicken bits in config0 reg
84ff2a1 drm/i915/kbl: Add WaDisableLSQCROPERFforOCL
7966b03 drm/i915/edp: Add WaKVMNotificationOnConfigChange:bdw
128d238 drm/i915/kbl: Add WaDisableSDEUnitClockGating
6de73a9 drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0
4139189 drm/i915/kbl: Add WaEnableGapsTsvCreditFix
83001ef drm/i915: Mimic skl with WaForceEnableNonCoherent
03b15c2 drm/i915/gen9: Always apply WaForceContextSaveRestoreNonCoherent
79e0698 drm/i915/kbl: Add WaSkipStolenMemoryFirstPage for A0
0fe1a4e drm/i915/kbl: Add REVID macro
cea5e59 drm/i915/kbl: Init gen9 workarounds
8466c32 drm/i915/skl: Add WaDisableGafsUnitClkGating
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^ permalink raw reply [flat|nested] 34+ messages in thread* Re: ✓ Ro.CI.BAT: success for gen9 workarounds v3
2016-06-07 14:52 ` ✓ Ro.CI.BAT: success for gen9 workarounds v3 Patchwork
@ 2016-06-08 0:06 ` Chris Wilson
2016-06-08 14:28 ` Mika Kuoppala
0 siblings, 1 reply; 34+ messages in thread
From: Chris Wilson @ 2016-06-08 0:06 UTC (permalink / raw)
To: intel-gfx
On Tue, Jun 07, 2016 at 02:52:18PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: gen9 workarounds v3
> URL : https://patchwork.freedesktop.org/series/8405/
> State : success
>
> == Summary ==
>
> Series 8405v1 gen9 workarounds v3
> http://patchwork.freedesktop.org/api/1.0/series/8405/revisions/1/mbox
>
>
> fi-skl-i5-6260u total:209 pass:198 dwarn:0 dfail:0 fail:0 skip:11
> fi-skl-i7-6700k total:209 pass:184 dwarn:0 dfail:0 fail:0 skip:25
Out of curiosity, how many of these w/a are exercised by mesa/piglit or
beignet test suites? If so, how many of those could we extract to igt?
i.e. are any of these w/a suitable for test cases??
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: ✓ Ro.CI.BAT: success for gen9 workarounds v3
2016-06-08 0:06 ` Chris Wilson
@ 2016-06-08 14:28 ` Mika Kuoppala
2016-06-08 14:56 ` Chris Wilson
0 siblings, 1 reply; 34+ messages in thread
From: Mika Kuoppala @ 2016-06-08 14:28 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> [ text/plain ]
> On Tue, Jun 07, 2016 at 02:52:18PM -0000, Patchwork wrote:
>> == Series Details ==
>>
>> Series: gen9 workarounds v3
>> URL : https://patchwork.freedesktop.org/series/8405/
>> State : success
>>
>> == Summary ==
>>
>> Series 8405v1 gen9 workarounds v3
>> http://patchwork.freedesktop.org/api/1.0/series/8405/revisions/1/mbox
>>
>>
>> fi-skl-i5-6260u total:209 pass:198 dwarn:0 dfail:0 fail:0 skip:11
>> fi-skl-i7-6700k total:209 pass:184 dwarn:0 dfail:0 fail:0 skip:25
>
> Out of curiosity, how many of these w/a are exercised by mesa/piglit or
> beignet test suites? If so, how many of those could we extract to igt?
> i.e. are any of these w/a suitable for test cases??
WaEnableGapsTsvCreditFix we managed to trigger with gem_ringfill.
WaForceContextSaveRestoreNonCoherent was triggered by piglit,
but it needed also mesa counterpart. So this is one candidate.
I agree that we should have igt triggering as a goal
when reading, sometimes sketchy, hsds.
Now for most part we trust only to the wording and
gem_workarounds.
-Mika
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: ✓ Ro.CI.BAT: success for gen9 workarounds v3
2016-06-08 14:28 ` Mika Kuoppala
@ 2016-06-08 14:56 ` Chris Wilson
0 siblings, 0 replies; 34+ messages in thread
From: Chris Wilson @ 2016-06-08 14:56 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
On Wed, Jun 08, 2016 at 05:28:31PM +0300, Mika Kuoppala wrote:
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > [ text/plain ]
> > On Tue, Jun 07, 2016 at 02:52:18PM -0000, Patchwork wrote:
> >> == Series Details ==
> >>
> >> Series: gen9 workarounds v3
> >> URL : https://patchwork.freedesktop.org/series/8405/
> >> State : success
> >>
> >> == Summary ==
> >>
> >> Series 8405v1 gen9 workarounds v3
> >> http://patchwork.freedesktop.org/api/1.0/series/8405/revisions/1/mbox
> >>
> >>
> >> fi-skl-i5-6260u total:209 pass:198 dwarn:0 dfail:0 fail:0 skip:11
> >> fi-skl-i7-6700k total:209 pass:184 dwarn:0 dfail:0 fail:0 skip:25
> >
> > Out of curiosity, how many of these w/a are exercised by mesa/piglit or
> > beignet test suites? If so, how many of those could we extract to igt?
> > i.e. are any of these w/a suitable for test cases??
>
> WaEnableGapsTsvCreditFix we managed to trigger with gem_ringfill.
>
> WaForceContextSaveRestoreNonCoherent was triggered by piglit,
> but it needed also mesa counterpart. So this is one candidate.
>
> I agree that we should have igt triggering as a goal
> when reading, sometimes sketchy, hsds.
It's also indicative of what behaviour we should be stressing. If it is
not possible to exercise such through our uABI that is one thing. But if
we could have detected the error, then we are missing coverage in our igt.
It is definitely a useful exercise if the test remains valid for gen+1.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 34+ messages in thread