* [PATCH] drm/i915: Unbreak interrupts on pre-gen6
@ 2016-07-12 16:24 ville.syrjala
2016-07-12 16:47 ` Chris Wilson
2016-07-12 17:09 ` ✓ Ro.CI.BAT: success for " Patchwork
0 siblings, 2 replies; 6+ messages in thread
From: ville.syrjala @ 2016-07-12 16:24 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Prior to gen6 we didn't have per-ring IMR registers, which means that
since commit 61ff75ac20ff ("drm/i915: Simplify enabling
user-interrupts with L3-remapping") we're now masking off all interrupts
when init_render_ring() gets called. That's rather rude. Let's limit
the ring IMR frobbing to machines that actually have the per-ring IMR
registers.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Fixes: 61ff75ac20ff ("drm/i915: Simplify enabling user-interrupts with L3-remapping")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 61e00bf9e87f..c8e77c082b21 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1305,7 +1305,8 @@ static int init_render_ring(struct intel_engine_cs *engine)
if (IS_GEN(dev_priv, 6, 7))
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
- I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
+ if (INTEL_INFO(dev_priv)->gen >= 6)
+ I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
return init_workarounds_ring(engine);
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] drm/i915: Unbreak interrupts on pre-gen6
2016-07-12 16:24 [PATCH] drm/i915: Unbreak interrupts on pre-gen6 ville.syrjala
@ 2016-07-12 16:47 ` Chris Wilson
2016-07-12 19:13 ` Ville Syrjälä
2016-07-13 14:06 ` Ville Syrjälä
2016-07-12 17:09 ` ✓ Ro.CI.BAT: success for " Patchwork
1 sibling, 2 replies; 6+ messages in thread
From: Chris Wilson @ 2016-07-12 16:47 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Tue, Jul 12, 2016 at 07:24:47PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Prior to gen6 we didn't have per-ring IMR registers, which means that
> since commit 61ff75ac20ff ("drm/i915: Simplify enabling
> user-interrupts with L3-remapping") we're now masking off all interrupts
> when init_render_ring() gets called.
That confused me, we're just writing to a non-existent register, so it
shouldn't have any effect.
> That's rather rude. Let's limit
> the ring IMR frobbing to machines that actually have the per-ring IMR
> registers.
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Fixes: 61ff75ac20ff ("drm/i915: Simplify enabling user-interrupts with L3-remapping")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewd-by: Chris Wilson <chris@chris-wilson.co.uk>
Did you see anything to cause concern? I've run this patch on gen2-9, so
I wonder what I missed and how.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] drm/i915: Unbreak interrupts on pre-gen6
2016-07-12 16:47 ` Chris Wilson
@ 2016-07-12 19:13 ` Ville Syrjälä
2016-07-12 19:43 ` Chris Wilson
2016-07-13 14:06 ` Ville Syrjälä
1 sibling, 1 reply; 6+ messages in thread
From: Ville Syrjälä @ 2016-07-12 19:13 UTC (permalink / raw)
To: Chris Wilson, intel-gfx, Tvrtko Ursulin
On Tue, Jul 12, 2016 at 05:47:02PM +0100, Chris Wilson wrote:
> On Tue, Jul 12, 2016 at 07:24:47PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Prior to gen6 we didn't have per-ring IMR registers, which means that
> > since commit 61ff75ac20ff ("drm/i915: Simplify enabling
> > user-interrupts with L3-remapping") we're now masking off all interrupts
> > when init_render_ring() gets called.
>
> That confused me, we're just writing to a non-existent register, so it
> shouldn't have any effect.
RING_IMR(RCS) == 0x20a8 == IMR
>
> > That's rather rude. Let's limit
> > the ring IMR frobbing to machines that actually have the per-ring IMR
> > registers.
> >
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Fixes: 61ff75ac20ff ("drm/i915: Simplify enabling user-interrupts with L3-remapping")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewd-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> Did you see anything to cause concern? I've run this patch on gen2-9, so
> I wonder what I missed and how.
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] drm/i915: Unbreak interrupts on pre-gen6
2016-07-12 19:13 ` Ville Syrjälä
@ 2016-07-12 19:43 ` Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2016-07-12 19:43 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Jul 12, 2016 at 10:13:48PM +0300, Ville Syrjälä wrote:
> On Tue, Jul 12, 2016 at 05:47:02PM +0100, Chris Wilson wrote:
> > On Tue, Jul 12, 2016 at 07:24:47PM +0300, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Prior to gen6 we didn't have per-ring IMR registers, which means that
> > > since commit 61ff75ac20ff ("drm/i915: Simplify enabling
> > > user-interrupts with L3-remapping") we're now masking off all interrupts
> > > when init_render_ring() gets called.
> >
> > That confused me, we're just writing to a non-existent register, so it
> > shouldn't have any effect.
>
> RING_IMR(RCS) == 0x20a8 == IMR
Ah (I expected the global IIR et al not to be in the ring block). And
since we unmask everything, nothing is broken at first glance.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Unbreak interrupts on pre-gen6
2016-07-12 16:47 ` Chris Wilson
2016-07-12 19:13 ` Ville Syrjälä
@ 2016-07-13 14:06 ` Ville Syrjälä
1 sibling, 0 replies; 6+ messages in thread
From: Ville Syrjälä @ 2016-07-13 14:06 UTC (permalink / raw)
To: Chris Wilson, intel-gfx, Tvrtko Ursulin
On Tue, Jul 12, 2016 at 05:47:02PM +0100, Chris Wilson wrote:
> On Tue, Jul 12, 2016 at 07:24:47PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Prior to gen6 we didn't have per-ring IMR registers, which means that
> > since commit 61ff75ac20ff ("drm/i915: Simplify enabling
> > user-interrupts with L3-remapping") we're now masking off all interrupts
> > when init_render_ring() gets called.
>
> That confused me, we're just writing to a non-existent register, so it
> shouldn't have any effect.
>
> > That's rather rude. Let's limit
> > the ring IMR frobbing to machines that actually have the per-ring IMR
> > registers.
> >
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Fixes: 61ff75ac20ff ("drm/i915: Simplify enabling user-interrupts with L3-remapping")
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewd-by: Chris Wilson <chris@chris-wilson.co.uk>
Pushed to dinq. Thanks for the review.
>
> Did you see anything to cause concern? I've run this patch on gen2-9, so
> I wonder what I missed and how.
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Ro.CI.BAT: success for drm/i915: Unbreak interrupts on pre-gen6
2016-07-12 16:24 [PATCH] drm/i915: Unbreak interrupts on pre-gen6 ville.syrjala
2016-07-12 16:47 ` Chris Wilson
@ 2016-07-12 17:09 ` Patchwork
1 sibling, 0 replies; 6+ messages in thread
From: Patchwork @ 2016-07-12 17:09 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Unbreak interrupts on pre-gen6
URL : https://patchwork.freedesktop.org/series/9762/
State : success
== Summary ==
Series 9762v1 drm/i915: Unbreak interrupts on pre-gen6
http://patchwork.freedesktop.org/api/1.0/series/9762/revisions/1/mbox
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> SKIP (ro-bdw-i7-5557U)
fi-kbl-qkkr total:237 pass:175 dwarn:29 dfail:0 fail:7 skip:26
fi-skl-i5-6260u total:237 pass:218 dwarn:0 dfail:0 fail:7 skip:12
fi-skl-i7-6700k total:237 pass:204 dwarn:0 dfail:0 fail:7 skip:26
fi-snb-i7-2600 total:237 pass:190 dwarn:0 dfail:0 fail:7 skip:40
ro-bdw-i5-5250u total:237 pass:213 dwarn:1 dfail:0 fail:7 skip:16
ro-bdw-i7-5557U total:237 pass:213 dwarn:1 dfail:0 fail:7 skip:16
ro-bdw-i7-5600u total:237 pass:199 dwarn:0 dfail:0 fail:7 skip:31
ro-bsw-n3050 total:217 pass:171 dwarn:1 dfail:0 fail:2 skip:42
ro-byt-n2820 total:237 pass:191 dwarn:0 dfail:0 fail:8 skip:38
ro-hsw-i3-4010u total:237 pass:206 dwarn:0 dfail:0 fail:7 skip:24
ro-hsw-i7-4770r total:237 pass:206 dwarn:0 dfail:0 fail:7 skip:24
ro-ilk-i7-620lm total:237 pass:166 dwarn:0 dfail:0 fail:8 skip:63
ro-ilk1-i5-650 total:232 pass:166 dwarn:0 dfail:0 fail:8 skip:58
ro-ivb-i7-3770 total:237 pass:197 dwarn:0 dfail:0 fail:7 skip:33
ro-skl3-i5-6260u total:237 pass:217 dwarn:1 dfail:0 fail:7 skip:12
ro-snb-i7-2620M total:237 pass:188 dwarn:0 dfail:0 fail:8 skip:41
Results at /archive/results/CI_IGT_test/RO_Patchwork_1476/
9561f5c drm-intel-nightly: 2016y-07m-12d-15h-14m-43s UTC integration manifest
bdf47d5 drm/i915: Unbreak interrupts on pre-gen6
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^ permalink raw reply [flat|nested] 6+ messages in thread
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2016-07-12 16:24 [PATCH] drm/i915: Unbreak interrupts on pre-gen6 ville.syrjala
2016-07-12 16:47 ` Chris Wilson
2016-07-12 19:13 ` Ville Syrjälä
2016-07-12 19:43 ` Chris Wilson
2016-07-13 14:06 ` Ville Syrjälä
2016-07-12 17:09 ` ✓ Ro.CI.BAT: success for " Patchwork
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