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From: Daniel Vetter <daniel@ffwll.ch>
To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/5] drm/i915: unify first-stage engine struct setup
Date: Wed, 13 Jul 2016 14:23:29 +0200	[thread overview]
Message-ID: <20160713122329.GI23520@phenom.ffwll.local> (raw)
In-Reply-To: <1467391635-9902-1-git-send-email-tvrtko.ursulin@linux.intel.com>

On Fri, Jul 01, 2016 at 05:47:11PM +0100, Tvrtko Ursulin wrote:
> From: Dave Gordon <david.s.gordon@intel.com>
> 
> intel_lrc.c has a table of "logical rings" (meaning engines), while
> intel_ringbuffer.c has separately open-coded initialisation for each
> engine. We can deduplicate this somewhat by using the same first-stage
> engine-setup function for both modes.
> 
> So here we expose the function that transfers information from the
> static table of (all) known engines to the dev_priv->engine array of
> engines available on this device (adjusting the names along the way)
> and then embed calls to it in both the LRC and the legacy-mode setup.
> 
> Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c        | 40 +++++++++++++++++++++------------
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 40 +++++++++------------------------
>  drivers/gpu/drm/i915/intel_ringbuffer.h |  5 +++++
>  3 files changed, 41 insertions(+), 44 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 339d8041075f..ed017f1a07a2 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1994,8 +1994,9 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>  }
>  
>  static inline void
> -logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift)
> +logical_ring_default_irqs(struct intel_engine_cs *engine)
>  {
> +	unsigned shift = engine->irq_shift;
>  	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
>  	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
>  	init_waitqueue_head(&engine->irq_queue);
> @@ -2096,14 +2097,14 @@ static int logical_render_ring_init(struct intel_engine_cs *engine)
>  	return ret;
>  }
>  
> -static const struct logical_ring_info {
> +static const struct engine_info {
>  	const char *name;
>  	unsigned exec_id;
>  	unsigned guc_id;
>  	u32 mmio_base;
>  	unsigned irq_shift;
>  	int (*init)(struct intel_engine_cs *engine);
> -} logical_rings[] = {
> +} intel_engines[] = {
>  	[RCS] = {
>  		.name = "render ring",
>  		.exec_id = I915_EXEC_RENDER,
> @@ -2146,20 +2147,31 @@ static const struct logical_ring_info {
>  	},
>  };
>  
> -static struct intel_engine_cs *
> -logical_ring_setup(struct drm_i915_private *dev_priv, enum intel_engine_id id)
> +struct intel_engine_cs *
> +intel_engine_setup(struct drm_i915_private *dev_priv,
> +		   enum intel_engine_id id)

Kerneldoc for this would be nice. Also, we now have a mess between
intel_lrc.c and intel_ringbuffer.c. Extracting intel_engine.c with the
shared bits or something similar, plus cleanup up all the docs would be
awesome as a follow up.

With the kerneldoc added:

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

>  {
> -	const struct logical_ring_info *info = &logical_rings[id];
> +	const struct engine_info *info = &intel_engines[id];
>  	struct intel_engine_cs *engine = &dev_priv->engine[id];
> -	enum forcewake_domains fw_domains;
>  
>  	engine->id = id;
> +	engine->i915 = dev_priv;
>  	engine->name = info->name;
>  	engine->exec_id = info->exec_id;
> -	engine->guc_id = info->guc_id;
> +	engine->hw_id = engine->guc_id = info->guc_id;

Optional bikeshed: s/info->guc_id/info->hw_id/ makes sense imo in the new
context. Or nuking engine->guc_id.

>  	engine->mmio_base = info->mmio_base;
> +	engine->irq_shift = info->irq_shift;
>  
> -	engine->i915 = dev_priv;
> +	return engine;
> +}
> +
> +static struct intel_engine_cs *
> +logical_ring_setup(struct drm_i915_private *dev_priv, enum intel_engine_id id)
> +{
> +	struct intel_engine_cs *engine;
> +	enum forcewake_domains fw_domains;
> +
> +	engine = intel_engine_setup(dev_priv, id);
>  
>  	/* Intentionally left blank. */
>  	engine->buffer = NULL;
> @@ -2189,7 +2201,7 @@ logical_ring_setup(struct drm_i915_private *dev_priv, enum intel_engine_id id)
>  
>  	logical_ring_init_platform_invariants(engine);
>  	logical_ring_default_vfuncs(engine);
> -	logical_ring_default_irqs(engine, info->irq_shift);
> +	logical_ring_default_irqs(engine);
>  
>  	intel_engine_init_hangcheck(engine);
>  	i915_gem_batch_pool_init(dev_priv->dev, &engine->batch_pool);
> @@ -2218,14 +2230,14 @@ int intel_logical_rings_init(struct drm_device *dev)
>  	WARN_ON(INTEL_INFO(dev_priv)->ring_mask &
>  		GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
>  
> -	for (i = 0; i < ARRAY_SIZE(logical_rings); i++) {
> +	for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
>  		if (!HAS_ENGINE(dev_priv, i))
>  			continue;
>  
> -		if (!logical_rings[i].init)
> +		if (!intel_engines[i].init)
>  			continue;
>  
> -		ret = logical_rings[i].init(logical_ring_setup(dev_priv, i));
> +		ret = intel_engines[i].init(logical_ring_setup(dev_priv, i));
>  		if (ret)
>  			goto cleanup;
>  
> @@ -2233,7 +2245,7 @@ int intel_logical_rings_init(struct drm_device *dev)
>  	}
>  
>  	/*
> -	 * Catch failures to update logical_rings table when the new engines
> +	 * Catch failures to update intel_engines table when the new engines
>  	 * are added to the driver by a warning and disabling the forgotten
>  	 * engines.
>  	 */
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 24cdc920f4b4..215424efe05c 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -3036,15 +3036,11 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
>  int intel_init_render_ring_buffer(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_engine_cs *engine = &dev_priv->engine[RCS];
> +	struct intel_engine_cs *engine;
>  	struct drm_i915_gem_object *obj;
>  	int ret;
>  
> -	engine->name = "render ring";
> -	engine->id = RCS;
> -	engine->exec_id = I915_EXEC_RENDER;
> -	engine->hw_id = 0;
> -	engine->mmio_base = RENDER_RING_BASE;
> +	engine = intel_engine_setup(dev_priv, RCS);
>  
>  	intel_ring_default_vfuncs(dev_priv, engine);
>  
> @@ -3117,17 +3113,13 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
>  int intel_init_bsd_ring_buffer(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_engine_cs *engine = &dev_priv->engine[VCS];
> +	struct intel_engine_cs *engine;
>  
> -	engine->name = "bsd ring";
> -	engine->id = VCS;
> -	engine->exec_id = I915_EXEC_BSD;
> -	engine->hw_id = 1;
> +	engine = intel_engine_setup(dev_priv, VCS);
>  
>  	intel_ring_default_vfuncs(dev_priv, engine);
>  
>  	if (INTEL_GEN(dev_priv) >= 6) {
> -		engine->mmio_base = GEN6_BSD_RING_BASE;
>  		/* gen6 bsd needs a special wa for tail updates */
>  		if (IS_GEN6(dev_priv))
>  			engine->write_tail = gen6_bsd_ring_write_tail;
> @@ -3155,13 +3147,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
>  int intel_init_bsd2_ring_buffer(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
> +	struct intel_engine_cs *engine;
>  
> -	engine->name = "bsd2 ring";
> -	engine->id = VCS2;
> -	engine->exec_id = I915_EXEC_BSD;
> -	engine->hw_id = 4;
> -	engine->mmio_base = GEN8_BSD2_RING_BASE;
> +	engine = intel_engine_setup(dev_priv, VCS2);
>  
>  	intel_ring_default_vfuncs(dev_priv, engine);
>  
> @@ -3175,13 +3163,9 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
>  int intel_init_blt_ring_buffer(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_engine_cs *engine = &dev_priv->engine[BCS];
> +	struct intel_engine_cs *engine;
>  
> -	engine->name = "blitter ring";
> -	engine->id = BCS;
> -	engine->exec_id = I915_EXEC_BLT;
> -	engine->hw_id = 2;
> -	engine->mmio_base = BLT_RING_BASE;
> +	engine = intel_engine_setup(dev_priv, BCS);
>  
>  	intel_ring_default_vfuncs(dev_priv, engine);
>  
> @@ -3198,13 +3182,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
>  int intel_init_vebox_ring_buffer(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	struct intel_engine_cs *engine = &dev_priv->engine[VECS];
> +	struct intel_engine_cs *engine;
>  
> -	engine->name = "video enhancement ring";
> -	engine->id = VECS;
> -	engine->exec_id = I915_EXEC_VEBOX;
> -	engine->hw_id = 3;
> -	engine->mmio_base = VEBOX_RING_BASE;
> +	engine = intel_engine_setup(dev_priv, VECS);
>  
>  	intel_ring_default_vfuncs(dev_priv, engine);
>  
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 113d5230a6de..1aeb00cba9e2 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -145,6 +145,7 @@ struct intel_engine_cs {
>  	unsigned int hw_id;
>  	unsigned int guc_id; /* XXX same as hw_id? */
>  	u32		mmio_base;
> +	unsigned int irq_shift;
>  	struct intel_ringbuffer *buffer;
>  	struct list_head buffers;
>  
> @@ -335,6 +336,10 @@ struct intel_engine_cs {
>  	u32 (*get_cmd_length_mask)(u32 cmd_header);
>  };
>  
> +struct intel_engine_cs *
> +intel_engine_setup(struct drm_i915_private *dev_priv,
> +		   enum intel_engine_id id);
> +
>  static inline bool
>  intel_engine_initialized(struct intel_engine_cs *engine)
>  {
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2016-07-13 12:23 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-01 16:47 [PATCH 1/5] drm/i915: unify first-stage engine struct setup Tvrtko Ursulin
2016-07-01 16:47 ` [PATCH 2/5] drm/i915: Prepare for engine init unification Tvrtko Ursulin
2016-07-01 16:47 ` [PATCH 3/5] drm/i915: Unify engine init loop Tvrtko Ursulin
2016-07-01 16:47 ` [PATCH 4/5] drm/i915: Make more use of the shared engine irq setup Tvrtko Ursulin
2016-07-13 12:30   ` Daniel Vetter
2016-07-13 13:19     ` Tvrtko Ursulin
2016-07-01 16:47 ` [PATCH 5/5] drm/i915: Simplify intel_init_ring_buffer prototype Tvrtko Ursulin
2016-07-13 12:30   ` Daniel Vetter
2016-07-01 17:08 ` ✗ Ro.CI.BAT: warning for series starting with [1/5] drm/i915: unify first-stage engine struct setup Patchwork
2016-07-13 12:23 ` Daniel Vetter [this message]
2016-07-13 13:16   ` [PATCH 1/5] " Tvrtko Ursulin
2016-07-13 13:24     ` Tvrtko Ursulin
2016-07-14 14:29       ` Daniel Vetter
2016-07-14 11:33     ` Dave Gordon
  -- strict thread matches above, loose matches on Subject: below --
2016-07-06 10:52 Tvrtko Ursulin

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