From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org,
David Weinehall <david.weinehall@intel.com>
Subject: Re: [PATCH] drm/i915: Wait up to 3ms for the pcu to ack the cdclk change request on SKL
Date: Wed, 27 Jul 2016 16:32:08 +0300 [thread overview]
Message-ID: <20160727133208.GN4329@intel.com> (raw)
In-Reply-To: <20160714143900.GG17101@phenom.ffwll.local>
On Thu, Jul 14, 2016 at 04:39:00PM +0200, Daniel Vetter wrote:
> On Wed, Jul 13, 2016 at 04:32:03PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Bspec tells us to keep bashing the PCU for up to 3ms when trying to
> > inform it about an upcoming change in the cdclk frequency. Currently
> > we only keep at it for 15*10usec (+ whatever delays gets added by
> > the sandybridge_pcode_read() itself). Let's change the limit to 3ms.
> >
> > I decided to keep 10 usec delay per iteration for now, even though
> > the spec doesn't really tell us to do that.
> >
> > Cc: David Weinehall <david.weinehall@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Needs
>
> Cc: stable@vger.kernel.org
>
> and probably also a Fixes: line?
Fixes: 5d96d8afcfbb ("drm/i915/skl: Deinit/init the display at suspend/resume")
and pushed to dinq. Thanks for the review/testing.
> -Daniel
>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 10 +---------
> > 1 file changed, 1 insertion(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index be3b2cab2640..90f26f0e2571 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5691,15 +5691,7 @@ static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
> >
> > static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
> > {
> > - unsigned int i;
> > -
> > - for (i = 0; i < 15; i++) {
> > - if (skl_cdclk_pcu_ready(dev_priv))
> > - return true;
> > - udelay(10);
> > - }
> > -
> > - return false;
> > + return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
> > }
> >
> > static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
prev parent reply other threads:[~2016-07-27 13:32 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-13 13:32 [PATCH] drm/i915: Wait up to 3ms for the pcu to ack the cdclk change request on SKL ville.syrjala
2016-07-13 13:37 ` David Weinehall
2016-07-13 14:07 ` ✗ Ro.CI.BAT: failure for " Patchwork
2016-07-18 12:57 ` Ville Syrjälä
2016-07-13 18:42 ` [PATCH] " Chris Wilson
2016-07-14 14:39 ` Daniel Vetter
2016-07-27 13:32 ` Ville Syrjälä [this message]
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