From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 12/12] drm/i915: Make sure fb offset is (macro)pixel aligned
Date: Wed, 10 Aug 2016 14:02:43 +0300 [thread overview]
Message-ID: <20160810110243.GK4329@intel.com> (raw)
In-Reply-To: <20160810100432.GX6232@phenom.ffwll.local>
On Wed, Aug 10, 2016 at 12:04:32PM +0200, Daniel Vetter wrote:
> On Wed, Aug 10, 2016 at 12:23:21PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We convert the fb->offsets[] into x/y offsets, so they must be
> > (macro)pixel aligned. Check for this, and if things look good
> > allow fb->offsets[] != 0 when creating fbs since we now handle
> > them correctly.
> >
> > v2: Move to last place in the series and improve the commit message
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v1)
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 37 +++++++++++++++++++++++++++++++++---
> > 1 file changed, 34 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index f8487bcdb271..d3de56f0e764 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15370,6 +15370,37 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
> > }
> > }
> >
> > +static int intel_fb_check_offsets(const struct drm_mode_fb_cmd2 *mode_cmd)
> > +{
> > + uint32_t format = mode_cmd->pixel_format;
> > + int num_planes = drm_format_num_planes(format);
> > + int i;
> > +
> > + for (i = 0; i < num_planes; i++) {
> > + unsigned int cpp;
> > +
> > + switch (format) {
> > + case DRM_FORMAT_YUYV:
> > + case DRM_FORMAT_UYVY:
> > + case DRM_FORMAT_YVYU:
> > + case DRM_FORMAT_VYUY:
> > + cpp = 4;
> > + break;
> > + default:
> > + cpp = drm_format_plane_cpp(format, i);
>
> I didn't ask for a helper in drm_fourcc.c for macropixel blocksize? Shame
> on me!
You did, long ago. I just couldn't be bothered to go and see what we
need to do there. Now that I do, it doesn't look like we've gained
any new formats that would need special treatment, so I suppose I
could just reuse this guy as is.
> Anyway, looks all good and I didn't spot anything else amiss while
> re-reading the series.
>
> Another wishlist item: Extracting intel_framebuffer.c might be a good
> idea.
> -Daniel
>
> > + break;
> > + }
> > +
> > + if (mode_cmd->offsets[i] % cpp) {
> > + DRM_DEBUG("fb plane %d offset 0x%08x not (macro)pixel aligned\n",
> > + i, mode_cmd->offsets[i]);
> > + return -EINVAL;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > static int intel_framebuffer_init(struct drm_device *dev,
> > struct intel_framebuffer *intel_fb,
> > struct drm_mode_fb_cmd2 *mode_cmd,
> > @@ -15514,9 +15545,9 @@ static int intel_framebuffer_init(struct drm_device *dev,
> > return -EINVAL;
> > }
> >
> > - /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
> > - if (mode_cmd->offsets[0] != 0)
> > - return -EINVAL;
> > + ret = intel_fb_check_offsets(mode_cmd);
> > + if (ret)
> > + return ret;
> >
> > drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
> > intel_fb->obj = obj;
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2016-08-10 11:03 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-10 9:23 [PATCH v5 00/12] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v5) ville.syrjala
2016-08-10 9:23 ` [PATCH v6 01/12] drm/i915: Rewrite fb rotation GTT handling ville.syrjala
2016-08-10 9:49 ` Daniel Vetter
2016-08-10 9:23 ` [PATCH v3 02/12] drm/i915: Don't pass pitch to intel_compute_page_offset() ville.syrjala
2016-08-10 9:23 ` [PATCH v2 03/12] drm/i915: Move SKL hw stride calculation into a helper ville.syrjala
2016-08-10 9:23 ` [PATCH 04/12] drm/i915: Pass around plane_state instead of fb+rotation ville.syrjala
2016-08-10 9:23 ` [PATCH v4 05/12] drm/i915: Use fb modifiers for display tiling decisions ville.syrjala
2016-08-10 9:23 ` [PATCH v3 06/12] drm/i915: Adjust obj tiling vs. fb modifier rules ville.syrjala
2016-08-10 9:43 ` Daniel Vetter
2016-08-10 9:23 ` [PATCH v2 07/12] drm/i915: Limit fb x offset due to fences ville.syrjala
2016-08-10 9:23 ` [PATCH 08/12] drm/i915: Allow calling intel_adjust_tile_offset() multiple times ville.syrjala
2016-08-10 9:46 ` Chris Wilson
2016-08-10 9:48 ` Daniel Vetter
2016-08-10 11:17 ` Ville Syrjälä
2016-08-10 9:23 ` [PATCH 09/12] drm/i915: Make intel_adjust_tile_offset() work for linear buffers ville.syrjala
2016-08-10 9:23 ` [PATCH v2 10/12] drm/i915: Compute display surface offset in the plane check hook for SKL+ ville.syrjala
2016-08-10 9:23 ` [PATCH v2 11/12] drm/i915: Deal with NV12 CbCr plane AUX surface on SKL+ ville.syrjala
2016-08-10 10:03 ` Daniel Vetter
2016-08-10 11:26 ` Ville Syrjälä
2016-08-10 9:23 ` [PATCH v2 12/12] drm/i915: Make sure fb offset is (macro)pixel aligned ville.syrjala
2016-08-10 10:04 ` Daniel Vetter
2016-08-10 11:02 ` Ville Syrjälä [this message]
2016-08-10 11:33 ` Ville Syrjälä
2016-08-11 16:37 ` Ville Syrjälä
2016-08-10 11:46 ` ✗ Ro.CI.BAT: failure for drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v5) Patchwork
2016-08-10 12:40 ` Ville Syrjälä
-- strict thread matches above, loose matches on Subject: below --
2016-05-03 15:39 [PATCH v4 00/12] drm/i915: Handle fb->offsets[] and rewrite fb rotation handling to be more generic (v4) ville.syrjala
2016-05-03 15:40 ` [PATCH v2 12/12] drm/i915: Make sure fb offset is (macro)pixel aligned ville.syrjala
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