Re: [PATCH] drm/i915: Account for TSEG size when determining 865G stolen base

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, Aug 09, 2016 at 09:53:47AM +0100, Chris Wilson wrote:
> On Mon, Aug 08, 2016 at 01:58:39PM +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Looks like the TSEG lives just above TOUD, stolen comes after TSEG.
> > 
> > The spec seems somewhat self-contradictory in places, in the ESMRAMC
> > register desctription it says:
> >  TSEG Size:
> >   10=(TOUD + 512 KB) to TOUD
> >   11 =(TOUD + 1 MB) to TOUD
> > 
> > so that agrees with TSEG being at TOUD. But the example given
> > elsehwere in the spec says:
> > 
> >  TOUD equals 62.5 MB = 03E7FFFFh
> >  TSEG selected as 512 KB in size,
> >  Graphics local memory selected as 1 MB in size
> >  General System RAM available in system = 62.5 MB
> >  General system RAM range00000000h to 03E7FFFFh
> >  TSEG address range03F80000h to 03FFFFFFh
> >  TSEG pre-allocated from03F80000h to 03FFFFFFh
> >  Graphics local memory pre-allocated from03E80000h to 03F7FFFFh
> 
> Found that example:
> 
> """
> Notes on Pre-Allocated Memory for Graphics
> 
> These register bits control the use of memory from main memory space as
> graphics local memory.  The memory for TSEG is pre-allocated first and
> then the graphics local memory is pre-allocated. 
> """
>  
> > so here we have TSEG above stolen.
> > 
> > Real world evidence agrees with the TOUD->TSEG->stolen order however, so
> > let's fix up the code to account for the TSEG size.
> > 
> > Cc: Taketo Kabe <fdporg@vega.pgw.jp>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Ingo Molnar <mingo@redhat.com>
> > Cc: "H. Peter Anvin" <hpa@zytor.com>
> > Cc: x86@kernel.org
> > Cc: stable@vger.kernel.org
> > Fixes: 0ad98c74e093 ("drm/i915: Determine the stolen memory base address on gen2")
> > Fixes: a4dff76924fe ("x86/gpu: Add Intel graphics stolen memory quirk for gen2 platforms")
> > Reported-by: Taketo Kabe <fdporg@vega.pgw.jp>
> > Tested-by: Taketo Kabe <fdporg@vega.pgw.jp>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96473
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Link: http://download.intel.com/design/chipsets/datashts/25251405.pdf
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Didn't see any objections from x86 folks, so I went and pushed this to
dinq. Thanks for the review.

-- 
Ville Syrjälä
Intel OTC