From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ander.conselvan.de.oliveira@intel.com
Subject: DP Compliance Link Training tests failures
Date: Tue, 16 Aug 2016 19:51:35 -0700 [thread overview]
Message-ID: <20160817025135.GA25031@intel.com> (raw)
I have been working on getting the instrumentation in the kernel so that we
run the DP compliance tests using DPR 120. After adding the necessary code
in the kernel, I am able to run the DP Compliance test suite against our driver.
According to the DP Spec 1.2 and the Compliance tests, for link training's clock
recovery phase after maximum volatge swing is reached or after the same voltage is tried
5 times, then in the sixth iteration it should reduce the link rate to the next lower link rate
if it is not RBR else reduce the lane count and try the clock recovery sequence again.
Also for the channel equalization phase after the loop count reaches 5, it should lower the
link rate and retry the clock recovery.
The DP compliance tests test this behaviour and fail since the driver does not fallback to
the lower link rate or the lane count as part of the link training.
Do you know how this can be changed?
Regards
Manasi
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reply other threads:[~2016-08-17 2:38 UTC|newest]
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