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From: David Weinehall <david.weinehall@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: --dry-run@freedesktop.org
Subject: [PATCH 03/12] drm/i915: HAS_POOLED_EU() fixes
Date: Mon, 29 Aug 2016 13:31:43 +0300	[thread overview]
Message-ID: <20160829103152.31282-4-david.weinehall@linux.intel.com> (raw)
In-Reply-To: <20160829103152.31282-1-david.weinehall@linux.intel.com>

Pass dev_priv to all instances of HAS_POOLED_EU(), as well as
to INTEL_INFO()->min_eu_in_pool, and make the macro
use the new non-polymorph version of INTEL_INFO().

Signed-off-by: David Weinehall <david.weinehall@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c              | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h              | 2 +-
 drivers/gpu/drm/i915/i915_gem_render_state.c | 3 ++-
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 47fe07283d88..9fb32d9d5bb8 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -350,10 +350,10 @@ static int i915_getparam(struct drm_device *dev, void *data,
 		value = 1;
 		break;
 	case I915_PARAM_HAS_POOLED_EU:
-		value = HAS_POOLED_EU(dev);
+		value = HAS_POOLED_EU(dev_priv);
 		break;
 	case I915_PARAM_MIN_EU_IN_POOL:
-		value = INTEL_INFO(dev)->min_eu_in_pool;
+		value = INTEL_INFO(dev_priv)->min_eu_in_pool;
 		break;
 	case I915_PARAM_MMAP_GTT_VERSION:
 		/* Though we've started our numbering from 1, and so class all
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 22b75b93d084..3cf5220dfae4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2809,7 +2809,7 @@ struct drm_i915_cmd_table {
 				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
 				 !IS_BROXTON(dev))
 
-#define HAS_POOLED_EU(dev)	(INTEL_INFO(dev)->has_pooled_eu)
+#define HAS_POOLED_EU(dev_priv)	(__INTEL_INFO(dev_priv)->has_pooled_eu)
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 95b7e9afd5f8..d6d239211087 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -73,6 +73,7 @@ render_state_get_rodata(const struct drm_i915_gem_request *req)
 static int render_state_setup(struct render_state *so)
 {
 	struct drm_device *dev = so->vma->vm->dev;
+	struct drm_i915_private *dev_priv = to_i915(so->vma->vm->dev);
 	const struct intel_renderstate_rodata *rodata = so->rodata;
 	const bool has_64bit_reloc = INTEL_GEN(dev) >= 8;
 	unsigned int i = 0, reloc_index = 0;
@@ -115,7 +116,7 @@ static int render_state_setup(struct render_state *so)
 
 	so->aux_batch_offset = i * sizeof(u32);
 
-	if (HAS_POOLED_EU(dev)) {
+	if (HAS_POOLED_EU(dev_priv)) {
 		/*
 		 * We always program 3x6 pool config but depending upon which
 		 * subslice is disabled HW drops down to appropriate config
-- 
2.9.3

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  parent reply	other threads:[~2016-08-29 10:32 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-29 10:31 [PATCH 00/12] Feature macro cleanup, batch 1 David Weinehall
2016-08-29 10:31 ` [PATCH 01/12] drm/i915: Transitional, non-polymorph, macros David Weinehall
2016-08-29 10:31 ` [PATCH 02/12] drm/i915: IS_MOBILE() fixes David Weinehall
2016-08-29 10:31 ` David Weinehall [this message]
2016-08-29 10:31 ` [PATCH 04/12] drm/i915: INTEL_GEN() fixes, part 1 David Weinehall
2016-08-29 10:31 ` [PATCH 05/12] drm/i915: INTEL_GEN() fixes, part 2 David Weinehall
2016-08-29 10:31 ` [PATCH 06/12] drm/i915: INTEL_GEN() fixes, part 3 David Weinehall
2016-08-29 10:31 ` [PATCH 07/12] drm/i915: INTEL_GEN() fixes, part 4 David Weinehall
2016-08-29 10:31 ` [PATCH 08/12] drm/i915: INTEL_GEN() fixes, part 5 David Weinehall
2016-08-29 10:31 ` [PATCH 09/12] drm/i915: i915_vgacntrl_reg() fixes David Weinehall
2016-08-29 10:31 ` [PATCH 10/12] drm/i915: HAS_GMCH_DISPLAY() fixes David Weinehall
2016-08-29 10:31 ` [PATCH 11/12] drm/i915: RESOURCE_STREAMER/CORE_RING_FREQ fixes David Weinehall
2016-08-29 10:31 ` [PATCH 12/12] drm/i915: INTEL_GEN() fixes, part 6 David Weinehall
2016-08-29 11:25 ` ✗ Fi.CI.BAT: warning for Feature macro cleanup, batch 1 Patchwork

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