* [PATCH] drm/i915: Add ddb size field to device info structure
@ 2016-09-14 3:04 Deepak M
2016-09-14 5:38 ` ✓ Fi.CI.BAT: success for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Deepak M @ 2016-09-14 3:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M, ander.conselvan.de.oliveira
Adding the ddb size into the devide info will avoid
platform checks while computing wm.
Suggested-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 5 +++++
drivers/gpu/drm/i915/intel_pm.c | 13 +------------
3 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1e2dda8..4518ef3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -710,6 +710,7 @@ struct intel_device_info {
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+ u16 ddb_size;
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
int trans_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d771870d..687c768 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+ .ddb_size = 896,
};
static const struct intel_device_info intel_skylake_gt3_info = {
@@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+ .ddb_size = 896,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
@@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_hw_contexts = 1,
.has_logical_ring_contexts = 1,
.has_guc = 1,
+ .ddb_size = 512,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+ .ddb_size = 896,
};
static const struct intel_device_info intel_kabylake_gt3_info = {
@@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+ .ddb_size = 896,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6af438f..7eeb73b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
}
-/*
- * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
- * different active planes.
- */
-
-#define SKL_DDB_SIZE 896 /* in blocks */
-#define BXT_DDB_SIZE 512
#define SKL_SAGV_BLOCK_TIME 30 /* µs */
/*
@@ -3057,11 +3050,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
else
*num_active = hweight32(dev_priv->active_crtcs);
- if (IS_BROXTON(dev))
- ddb_size = BXT_DDB_SIZE;
- else
- ddb_size = SKL_DDB_SIZE;
-
+ ddb_size = INTEL_INFO(dev_priv)->ddb_size;
ddb_size -= 4; /* 4 blocks for bypass path allocation */
/*
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Add ddb size field to device info structure
2016-09-14 3:04 [PATCH] drm/i915: Add ddb size field to device info structure Deepak M
@ 2016-09-14 5:38 ` Patchwork
2016-09-14 8:01 ` [PATCH] " Jani Nikula
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2016-09-14 5:38 UTC (permalink / raw)
To: Deepak M; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Add ddb size field to device info structure
URL : https://patchwork.freedesktop.org/series/12427/
State : success
== Summary ==
Series 12427v1 drm/i915: Add ddb size field to device info structure
https://patchwork.freedesktop.org/api/1.0/series/12427/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-c:
skip -> PASS (fi-hsw-4770r)
fi-bsw-n3050 total:244 pass:202 dwarn:0 dfail:0 fail:0 skip:42
fi-hsw-4770k total:244 pass:226 dwarn:0 dfail:0 fail:0 skip:18
fi-hsw-4770r total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ilk-650 total:244 pass:183 dwarn:0 dfail:0 fail:1 skip:60
fi-ivb-3520m total:244 pass:219 dwarn:0 dfail:0 fail:0 skip:25
fi-ivb-3770 total:244 pass:207 dwarn:0 dfail:0 fail:0 skip:37
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:221 dwarn:0 dfail:0 fail:1 skip:22
fi-skl-6700k total:244 pass:219 dwarn:1 dfail:0 fail:0 skip:24
fi-snb-2520m total:244 pass:208 dwarn:0 dfail:0 fail:0 skip:36
fi-snb-2600 total:244 pass:207 dwarn:0 dfail:0 fail:0 skip:37
Results at /archive/results/CI_IGT_test/Patchwork_2527/
208290026552464713d3897ab5d649f4445d5513 drm-intel-nightly: 2016y-09m-13d-14h-45m-32s UTC integration manifest
838a0e3 drm/i915: Add ddb size field to device info structure
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Add ddb size field to device info structure
2016-09-14 3:04 [PATCH] drm/i915: Add ddb size field to device info structure Deepak M
2016-09-14 5:38 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2016-09-14 8:01 ` Jani Nikula
2016-09-14 8:24 ` Deepak M
2016-09-14 8:56 ` ✓ Fi.CI.BAT: success for drm/i915: Add ddb size field to device info structure (rev2) Patchwork
2016-09-15 9:49 ` ✓ Fi.CI.BAT: success for drm/i915: Add ddb size field to device info structure (rev3) Patchwork
3 siblings, 1 reply; 9+ messages in thread
From: Jani Nikula @ 2016-09-14 8:01 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M, ander.conselvan.de.oliveira
On Wed, 14 Sep 2016, Deepak M <m.deepak@intel.com> wrote:
> Adding the ddb size into the devide info will avoid
> platform checks while computing wm.
>
> Suggested-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 5 +++++
> drivers/gpu/drm/i915/intel_pm.c | 13 +------------
> 3 files changed, 7 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1e2dda8..4518ef3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -710,6 +710,7 @@ struct intel_device_info {
> u8 ring_mask; /* Rings supported by the HW */
> u8 num_rings;
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
> + u16 ddb_size;
This could use the /* in blocks */ comment.
> /* Register offsets for the various display pipes and transcoders */
> int pipe_offsets[I915_MAX_TRANSCODERS];
> int trans_offsets[I915_MAX_TRANSCODERS];
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d771870d..687c768 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
> .gen = 9,
> .has_csr = 1,
> .has_guc = 1,
> + .ddb_size = 896,
> };
>
> static const struct intel_device_info intel_skylake_gt3_info = {
> @@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
> .gen = 9,
> .has_csr = 1,
> .has_guc = 1,
> + .ddb_size = 896,
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> };
>
> @@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
> .has_hw_contexts = 1,
> .has_logical_ring_contexts = 1,
> .has_guc = 1,
> + .ddb_size = 512,
> GEN_DEFAULT_PIPEOFFSETS,
> IVB_CURSOR_OFFSETS,
> BDW_COLORS,
> @@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
> .gen = 9,
> .has_csr = 1,
> .has_guc = 1,
> + .ddb_size = 896,
> };
>
> static const struct intel_device_info intel_kabylake_gt3_info = {
> @@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
> .gen = 9,
> .has_csr = 1,
> .has_guc = 1,
> + .ddb_size = 896,
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6af438f..7eeb73b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
> return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
> }
>
> -/*
> - * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
> - * different active planes.
> - */
> -
> -#define SKL_DDB_SIZE 896 /* in blocks */
> -#define BXT_DDB_SIZE 512
> #define SKL_SAGV_BLOCK_TIME 30 /* µs */
>
> /*
> @@ -3057,11 +3050,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
> else
> *num_active = hweight32(dev_priv->active_crtcs);
>
> - if (IS_BROXTON(dev))
> - ddb_size = BXT_DDB_SIZE;
> - else
> - ddb_size = SKL_DDB_SIZE;
> -
> + ddb_size = INTEL_INFO(dev_priv)->ddb_size;
I'd perhaps stick a WARN_ON(ddb_size == 0) here.
With those fixed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ddb_size -= 4; /* 4 blocks for bypass path allocation */
>
> /*
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] drm/i915: Add ddb size field to device info structure
2016-09-14 8:01 ` [PATCH] " Jani Nikula
@ 2016-09-14 8:24 ` Deepak M
2016-09-15 8:31 ` Jani Nikula
0 siblings, 1 reply; 9+ messages in thread
From: Deepak M @ 2016-09-14 8:24 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
Adding the ddb size into the devide info will avoid
platform checks while computing wm.
v2: Added comment and WARN_ON if ddb size is zero.(Jani)
Suggested-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 5 +++++
drivers/gpu/drm/i915/intel_pm.c | 15 +++------------
3 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1e2dda8..6014c3a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -710,6 +710,7 @@ struct intel_device_info {
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+ u16 ddb_size; /* in blocks */
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
int trans_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d771870d..687c768 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+ .ddb_size = 896,
};
static const struct intel_device_info intel_skylake_gt3_info = {
@@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+ .ddb_size = 896,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
@@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_hw_contexts = 1,
.has_logical_ring_contexts = 1,
.has_guc = 1,
+ .ddb_size = 512,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+ .ddb_size = 896,
};
static const struct intel_device_info intel_kabylake_gt3_info = {
@@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+ .ddb_size = 896,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6af438f..9c5861e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
}
-/*
- * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
- * different active planes.
- */
-
-#define SKL_DDB_SIZE 896 /* in blocks */
-#define BXT_DDB_SIZE 512
#define SKL_SAGV_BLOCK_TIME 30 /* µs */
/*
@@ -3057,13 +3050,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
else
*num_active = hweight32(dev_priv->active_crtcs);
- if (IS_BROXTON(dev))
- ddb_size = BXT_DDB_SIZE;
- else
- ddb_size = SKL_DDB_SIZE;
-
+ ddb_size = INTEL_INFO(dev_priv)->ddb_size;
ddb_size -= 4; /* 4 blocks for bypass path allocation */
+ WARN_ON(ddb_size == 0);
+
/*
* If the state doesn't change the active CRTC's, then there's
* no need to recalculate; the existing pipe allocation limits
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Add ddb size field to device info structure (rev2)
2016-09-14 3:04 [PATCH] drm/i915: Add ddb size field to device info structure Deepak M
2016-09-14 5:38 ` ✓ Fi.CI.BAT: success for " Patchwork
2016-09-14 8:01 ` [PATCH] " Jani Nikula
@ 2016-09-14 8:56 ` Patchwork
2016-09-15 9:49 ` ✓ Fi.CI.BAT: success for drm/i915: Add ddb size field to device info structure (rev3) Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2016-09-14 8:56 UTC (permalink / raw)
To: Deepak M; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Add ddb size field to device info structure (rev2)
URL : https://patchwork.freedesktop.org/series/12427/
State : success
== Summary ==
Series 12427v2 drm/i915: Add ddb size field to device info structure
https://patchwork.freedesktop.org/api/1.0/series/12427/revisions/2/mbox/
fi-bsw-n3050 total:244 pass:202 dwarn:0 dfail:0 fail:0 skip:42
fi-hsw-4770k total:244 pass:226 dwarn:0 dfail:0 fail:0 skip:18
fi-hsw-4770r total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ilk-650 total:244 pass:183 dwarn:0 dfail:0 fail:1 skip:60
fi-ivb-3520m total:244 pass:219 dwarn:0 dfail:0 fail:0 skip:25
fi-ivb-3770 total:244 pass:207 dwarn:0 dfail:0 fail:0 skip:37
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:221 dwarn:0 dfail:0 fail:1 skip:22
fi-skl-6700k total:244 pass:219 dwarn:1 dfail:0 fail:0 skip:24
fi-snb-2520m total:244 pass:208 dwarn:0 dfail:0 fail:0 skip:36
fi-snb-2600 total:244 pass:207 dwarn:0 dfail:0 fail:0 skip:37
Results at /archive/results/CI_IGT_test/Patchwork_2529/
0c7c6ebb924db723ecabc2521e2afa71beeec471 drm-intel-nightly: 2016y-09m-14d-07h-41m-42s UTC integration manifest
67b040a drm/i915: Add ddb size field to device info structure
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Add ddb size field to device info structure
2016-09-14 8:24 ` Deepak M
@ 2016-09-15 8:31 ` Jani Nikula
2016-09-15 9:31 ` Deepak M
0 siblings, 1 reply; 9+ messages in thread
From: Jani Nikula @ 2016-09-15 8:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
On Wed, 14 Sep 2016, Deepak M <m.deepak@intel.com> wrote:
> Adding the ddb size into the devide info will avoid
> platform checks while computing wm.
>
> v2: Added comment and WARN_ON if ddb size is zero.(Jani)
>
> Suggested-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 5 +++++
> drivers/gpu/drm/i915/intel_pm.c | 15 +++------------
> 3 files changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1e2dda8..6014c3a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -710,6 +710,7 @@ struct intel_device_info {
> u8 ring_mask; /* Rings supported by the HW */
> u8 num_rings;
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
> + u16 ddb_size; /* in blocks */
> /* Register offsets for the various display pipes and transcoders */
> int pipe_offsets[I915_MAX_TRANSCODERS];
> int trans_offsets[I915_MAX_TRANSCODERS];
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d771870d..687c768 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
> .gen = 9,
> .has_csr = 1,
> .has_guc = 1,
> + .ddb_size = 896,
> };
>
> static const struct intel_device_info intel_skylake_gt3_info = {
> @@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
> .gen = 9,
> .has_csr = 1,
> .has_guc = 1,
> + .ddb_size = 896,
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> };
>
> @@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
> .has_hw_contexts = 1,
> .has_logical_ring_contexts = 1,
> .has_guc = 1,
> + .ddb_size = 512,
> GEN_DEFAULT_PIPEOFFSETS,
> IVB_CURSOR_OFFSETS,
> BDW_COLORS,
> @@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
> .gen = 9,
> .has_csr = 1,
> .has_guc = 1,
> + .ddb_size = 896,
> };
>
> static const struct intel_device_info intel_kabylake_gt3_info = {
> @@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
> .gen = 9,
> .has_csr = 1,
> .has_guc = 1,
> + .ddb_size = 896,
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6af438f..9c5861e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
> return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
> }
>
> -/*
> - * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
> - * different active planes.
> - */
> -
> -#define SKL_DDB_SIZE 896 /* in blocks */
> -#define BXT_DDB_SIZE 512
> #define SKL_SAGV_BLOCK_TIME 30 /* µs */
>
> /*
> @@ -3057,13 +3050,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
> else
> *num_active = hweight32(dev_priv->active_crtcs);
>
> - if (IS_BROXTON(dev))
> - ddb_size = BXT_DDB_SIZE;
> - else
> - ddb_size = SKL_DDB_SIZE;
> -
> + ddb_size = INTEL_INFO(dev_priv)->ddb_size;
> ddb_size -= 4; /* 4 blocks for bypass path allocation */
>
> + WARN_ON(ddb_size == 0);
Please be careful. You have to stick the WARN_ON *before* you decrement
by 4.
BR,
Jani.
> +
> /*
> * If the state doesn't change the active CRTC's, then there's
> * no need to recalculate; the existing pipe allocation limits
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] drm/i915: Add ddb size field to device info structure
2016-09-15 8:31 ` Jani Nikula
@ 2016-09-15 9:31 ` Deepak M
2016-09-15 11:06 ` Jani Nikula
0 siblings, 1 reply; 9+ messages in thread
From: Deepak M @ 2016-09-15 9:31 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
Adding the ddb size into the devide info will avoid
platform checks while computing wm.
v2: Added comment and WARN_ON if ddb size is zero.(Jani)
v3: Added WARN_ON at the right place.(Jani)
Suggested-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 5 +++++
drivers/gpu/drm/i915/intel_pm.c | 13 ++-----------
3 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1e2dda8..6014c3a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -710,6 +710,7 @@ struct intel_device_info {
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+ u16 ddb_size; /* in blocks */
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
int trans_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d771870d..687c768 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+ .ddb_size = 896,
};
static const struct intel_device_info intel_skylake_gt3_info = {
@@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+ .ddb_size = 896,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
@@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_hw_contexts = 1,
.has_logical_ring_contexts = 1,
.has_guc = 1,
+ .ddb_size = 512,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
@@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+ .ddb_size = 896,
};
static const struct intel_device_info intel_kabylake_gt3_info = {
@@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
.gen = 9,
.has_csr = 1,
.has_guc = 1,
+ .ddb_size = 896,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6af438f..2df06b7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
}
-/*
- * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
- * different active planes.
- */
-
-#define SKL_DDB_SIZE 896 /* in blocks */
-#define BXT_DDB_SIZE 512
#define SKL_SAGV_BLOCK_TIME 30 /* µs */
/*
@@ -3057,10 +3050,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
else
*num_active = hweight32(dev_priv->active_crtcs);
- if (IS_BROXTON(dev))
- ddb_size = BXT_DDB_SIZE;
- else
- ddb_size = SKL_DDB_SIZE;
+ ddb_size = INTEL_INFO(dev_priv)->ddb_size;
+ WARN_ON(ddb_size == 0);
ddb_size -= 4; /* 4 blocks for bypass path allocation */
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Add ddb size field to device info structure (rev3)
2016-09-14 3:04 [PATCH] drm/i915: Add ddb size field to device info structure Deepak M
` (2 preceding siblings ...)
2016-09-14 8:56 ` ✓ Fi.CI.BAT: success for drm/i915: Add ddb size field to device info structure (rev2) Patchwork
@ 2016-09-15 9:49 ` Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2016-09-15 9:49 UTC (permalink / raw)
To: Deepak M; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Add ddb size field to device info structure (rev3)
URL : https://patchwork.freedesktop.org/series/12427/
State : success
== Summary ==
Series 12427v3 drm/i915: Add ddb size field to device info structure
https://patchwork.freedesktop.org/api/1.0/series/12427/revisions/3/mbox/
Test gem_exec_suspend:
Subgroup basic-s3:
incomplete -> PASS (fi-hsw-4770k)
fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:244 pass:202 dwarn:0 dfail:0 fail:0 skip:42
fi-byt-j1900 total:244 pass:210 dwarn:2 dfail:0 fail:1 skip:31
fi-byt-n2820 total:244 pass:208 dwarn:0 dfail:0 fail:1 skip:35
fi-hsw-4770k total:244 pass:226 dwarn:0 dfail:0 fail:0 skip:18
fi-hsw-4770r total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22
fi-ilk-650 total:244 pass:183 dwarn:0 dfail:0 fail:1 skip:60
fi-ivb-3520m total:244 pass:219 dwarn:0 dfail:0 fail:0 skip:25
fi-ivb-3770 total:244 pass:207 dwarn:0 dfail:0 fail:0 skip:37
fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:244 pass:221 dwarn:0 dfail:0 fail:1 skip:22
fi-skl-6700k total:244 pass:219 dwarn:1 dfail:0 fail:0 skip:24
fi-skl-6770hq total:244 pass:228 dwarn:1 dfail:0 fail:1 skip:14
fi-snb-2520m total:244 pass:208 dwarn:0 dfail:0 fail:0 skip:36
fi-snb-2600 total:244 pass:207 dwarn:0 dfail:0 fail:0 skip:37
Results at /archive/results/CI_IGT_test/Patchwork_2539/
9aa8c0cdbc076bcc0486d7a31922a0f77c032fe7 drm-intel-nightly: 2016y-09m-14d-09h-19m-25s UTC integration manifest
a0f1e3e drm/i915: Add ddb size field to device info structure
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: Add ddb size field to device info structure
2016-09-15 9:31 ` Deepak M
@ 2016-09-15 11:06 ` Jani Nikula
0 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2016-09-15 11:06 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak M
On Thu, 15 Sep 2016, Deepak M <m.deepak@intel.com> wrote:
> Adding the ddb size into the devide info will avoid
> platform checks while computing wm.
>
> v2: Added comment and WARN_ON if ddb size is zero.(Jani)
> v3: Added WARN_ON at the right place.(Jani)
>
> Suggested-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Signed-off-by: Deepak M <m.deepak@intel.com>
Pushed to drm-intel-next-queued, thanks for the patch.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_pci.c | 5 +++++
> drivers/gpu/drm/i915/intel_pm.c | 13 ++-----------
> 3 files changed, 8 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1e2dda8..6014c3a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -710,6 +710,7 @@ struct intel_device_info {
> u8 ring_mask; /* Rings supported by the HW */
> u8 num_rings;
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
> + u16 ddb_size; /* in blocks */
> /* Register offsets for the various display pipes and transcoders */
> int pipe_offsets[I915_MAX_TRANSCODERS];
> int trans_offsets[I915_MAX_TRANSCODERS];
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d771870d..687c768 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
> .gen = 9,
> .has_csr = 1,
> .has_guc = 1,
> + .ddb_size = 896,
> };
>
> static const struct intel_device_info intel_skylake_gt3_info = {
> @@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
> .gen = 9,
> .has_csr = 1,
> .has_guc = 1,
> + .ddb_size = 896,
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> };
>
> @@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
> .has_hw_contexts = 1,
> .has_logical_ring_contexts = 1,
> .has_guc = 1,
> + .ddb_size = 512,
> GEN_DEFAULT_PIPEOFFSETS,
> IVB_CURSOR_OFFSETS,
> BDW_COLORS,
> @@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
> .gen = 9,
> .has_csr = 1,
> .has_guc = 1,
> + .ddb_size = 896,
> };
>
> static const struct intel_device_info intel_kabylake_gt3_info = {
> @@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
> .gen = 9,
> .has_csr = 1,
> .has_guc = 1,
> + .ddb_size = 896,
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
> };
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6af438f..2df06b7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
> return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
> }
>
> -/*
> - * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
> - * different active planes.
> - */
> -
> -#define SKL_DDB_SIZE 896 /* in blocks */
> -#define BXT_DDB_SIZE 512
> #define SKL_SAGV_BLOCK_TIME 30 /* µs */
>
> /*
> @@ -3057,10 +3050,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
> else
> *num_active = hweight32(dev_priv->active_crtcs);
>
> - if (IS_BROXTON(dev))
> - ddb_size = BXT_DDB_SIZE;
> - else
> - ddb_size = SKL_DDB_SIZE;
> + ddb_size = INTEL_INFO(dev_priv)->ddb_size;
> + WARN_ON(ddb_size == 0);
>
> ddb_size -= 4; /* 4 blocks for bypass path allocation */
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-09-15 11:06 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-09-14 3:04 [PATCH] drm/i915: Add ddb size field to device info structure Deepak M
2016-09-14 5:38 ` ✓ Fi.CI.BAT: success for " Patchwork
2016-09-14 8:01 ` [PATCH] " Jani Nikula
2016-09-14 8:24 ` Deepak M
2016-09-15 8:31 ` Jani Nikula
2016-09-15 9:31 ` Deepak M
2016-09-15 11:06 ` Jani Nikula
2016-09-14 8:56 ` ✓ Fi.CI.BAT: success for drm/i915: Add ddb size field to device info structure (rev2) Patchwork
2016-09-15 9:49 ` ✓ Fi.CI.BAT: success for drm/i915: Add ddb size field to device info structure (rev3) Patchwork
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