* [PATCH 01/19] drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 10:40 ` David Weinehall
2016-10-11 13:21 ` [PATCH 02/19] drm/i915: Make INTEL_PCH_TYPE & co " Tvrtko Ursulin
` (19 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
This saves 3248 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 8 +++---
drivers/gpu/drm/i915/intel_crt.c | 10 +++----
drivers/gpu/drm/i915/intel_display.c | 49 ++++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_dp.c | 16 ++++++------
drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +--
drivers/gpu/drm/i915/intel_hdmi.c | 10 +++----
drivers/gpu/drm/i915/intel_pm.c | 4 +--
drivers/gpu/drm/i915/intel_psr.c | 8 +++---
8 files changed, 56 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54d860e1c0fc..51dd10f25f59 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2815,7 +2815,7 @@ struct drm_i915_cmd_table {
#define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst)
-#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
+#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
#define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
#define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm)
@@ -2854,8 +2854,10 @@ struct drm_i915_cmd_table {
#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
-#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
-#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
+#define HAS_PCH_LPT_LP(dev_priv) \
+ ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
+#define HAS_PCH_LPT_H(dev_priv) \
+ ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 4a7b6c595ec2..d4b9b166de5d 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -280,13 +280,13 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (HAS_PCH_SPLIT(dev))
+ if (HAS_PCH_SPLIT(dev_priv))
pipe_config->has_pch_encoder = true;
/* LPT FDI RX only supports 8bpc. */
- if (HAS_PCH_LPT(dev)) {
+ if (HAS_PCH_LPT(dev_priv)) {
if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
DRM_DEBUG_KMS("LPT only supports 24bpp\n");
return false;
@@ -296,7 +296,7 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
}
/* FDI must always be 2.7 GHz */
- if (HAS_DDI(dev))
+ if (HAS_DDI(dev_priv))
pipe_config->port_clock = 135000 * 2;
return true;
@@ -917,7 +917,7 @@ void intel_crt_init(struct drm_device *dev)
if (I915_HAS_HOTPLUG(dev) &&
!dmi_check_system(intel_spurious_crt_detect))
crt->base.hpd_pin = HPD_CRT;
- if (HAS_DDI(dev)) {
+ if (HAS_DDI(dev_priv)) {
crt->base.port = PORT_E;
crt->base.get_config = hsw_crt_get_config;
crt->base.get_hw_state = intel_ddi_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 23a6c7213eca..6e447b575413 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1187,19 +1187,17 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
onoff(state), onoff(cur_state));
}
-void assert_panel_unlocked(struct drm_i915_private *dev_priv,
- enum pipe pipe)
+void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
{
- struct drm_device *dev = &dev_priv->drm;
i915_reg_t pp_reg;
u32 val;
enum pipe panel_pipe = PIPE_A;
bool locked = true;
- if (WARN_ON(HAS_DDI(dev)))
+ if (WARN_ON(HAS_DDI(dev_priv)))
return;
- if (HAS_PCH_SPLIT(dev)) {
+ if (HAS_PCH_SPLIT(dev_priv)) {
u32 port_sel;
pp_reg = PP_CONTROL(0);
@@ -1209,7 +1207,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv,
I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
panel_pipe = PIPE_B;
/* XXX: else fix for eDP */
- } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
/* presumably write lock depends on pipe, not port select */
pp_reg = PP_CONTROL(pipe);
panel_pipe = pipe;
@@ -5698,13 +5696,13 @@ static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
enum intel_display_power_domain
intel_display_port_power_domain(struct intel_encoder *intel_encoder)
{
- struct drm_device *dev = intel_encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
struct intel_digital_port *intel_dig_port;
switch (intel_encoder->type) {
case INTEL_OUTPUT_UNKNOWN:
/* Only DDI platforms should ever use this output type */
- WARN_ON_ONCE(!HAS_DDI(dev));
+ WARN_ON_ONCE(!HAS_DDI(dev_priv));
case INTEL_OUTPUT_DP:
case INTEL_OUTPUT_HDMI:
case INTEL_OUTPUT_EDP:
@@ -5725,7 +5723,7 @@ intel_display_port_power_domain(struct intel_encoder *intel_encoder)
enum intel_display_power_domain
intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
{
- struct drm_device *dev = intel_encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
struct intel_digital_port *intel_dig_port;
switch (intel_encoder->type) {
@@ -5738,7 +5736,7 @@ intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
* what's the status of the given connectors, play safe and
* run the DP detection too.
*/
- WARN_ON_ONCE(!HAS_DDI(dev));
+ WARN_ON_ONCE(!HAS_DDI(dev_priv));
case INTEL_OUTPUT_DP:
case INTEL_OUTPUT_EDP:
intel_dig_port = enc_to_dig_port(&intel_encoder->base);
@@ -9198,7 +9196,8 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
with_spread = true;
- if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
+ if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
+ with_fdi, "LP PCH doesn't have FDI\n"))
with_fdi = false;
mutex_lock(&dev_priv->sb_lock);
@@ -9221,7 +9220,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
}
}
- reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
+ reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
@@ -9237,7 +9236,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev)
mutex_lock(&dev_priv->sb_lock);
- reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
+ reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
@@ -10205,7 +10204,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv)
DRM_DEBUG_KMS("Enabling package C8+\n");
- if (HAS_PCH_LPT_LP(dev)) {
+ if (HAS_PCH_LPT_LP(dev_priv)) {
val = I915_READ(SOUTH_DSPCLK_GATE_D);
val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
@@ -10225,7 +10224,7 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
hsw_restore_lcpll(dev_priv);
lpt_init_pch_refclk(dev);
- if (HAS_PCH_LPT_LP(dev)) {
+ if (HAS_PCH_LPT_LP(dev_priv)) {
val = I915_READ(SOUTH_DSPCLK_GATE_D);
val |= PCH_LP_PARTITION_LEVEL_DISABLE;
I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
@@ -10847,7 +10846,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
}
cntl |= pipe << 28; /* Connect to correct pipe */
- if (HAS_DDI(dev))
+ if (HAS_DDI(dev_priv))
cntl |= CURSOR_PIPE_CSC_ENABLE;
if (plane_state->base.rotation == DRM_ROTATE_180)
@@ -12747,6 +12746,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
const char *context)
{
struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_plane *plane;
struct intel_plane *intel_plane;
struct intel_plane_state *state;
@@ -12829,7 +12829,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
pipe_config->dpll_hw_state.ctrl1,
pipe_config->dpll_hw_state.cfgcr1,
pipe_config->dpll_hw_state.cfgcr2);
- } else if (HAS_DDI(dev)) {
+ } else if (HAS_DDI(dev_priv)) {
DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
pipe_config->dpll_hw_state.wrpll,
pipe_config->dpll_hw_state.spll);
@@ -12907,7 +12907,7 @@ static bool check_digital_port_conflicts(struct drm_atomic_state *state)
switch (encoder->type) {
unsigned int port_mask;
case INTEL_OUTPUT_UNKNOWN:
- if (WARN_ON(!HAS_DDI(dev)))
+ if (WARN_ON(!HAS_DDI(to_i915(dev))))
break;
case INTEL_OUTPUT_DP:
case INTEL_OUTPUT_HDMI:
@@ -13731,7 +13731,7 @@ intel_modeset_verify_disabled(struct drm_device *dev)
static void update_scanline_offset(struct intel_crtc *crtc)
{
- struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
/*
* The scanline counter increments at the leading edge of hsync.
@@ -13751,7 +13751,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
* there's an extra 1 line difference. So we need to add two instead of
* one to the value.
*/
- if (IS_GEN2(dev)) {
+ if (IS_GEN2(dev_priv)) {
const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
int vtotal;
@@ -13760,7 +13760,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
vtotal /= 2;
crtc->scanline_offset = vtotal - 1;
- } else if (HAS_DDI(dev) &&
+ } else if (HAS_DDI(dev_priv) &&
intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
crtc->scanline_offset = 2;
} else
@@ -15329,11 +15329,12 @@ static bool intel_crt_present(struct drm_device *dev)
if (IS_CHERRYVIEW(dev))
return false;
- if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
+ if (HAS_PCH_LPT_H(dev_priv) &&
+ I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
return false;
/* DDI E can't be used if DDI A requires 4 lanes */
- if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
+ if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
return false;
if (!dev_priv->vbt.int_crt_support)
@@ -15407,7 +15408,7 @@ static void intel_setup_outputs(struct drm_device *dev)
intel_ddi_init(dev, PORT_C);
intel_dsi_init(dev);
- } else if (HAS_DDI(dev)) {
+ } else if (HAS_DDI(dev_priv)) {
int found;
/*
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5992093e1814..edaf35b975c0 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1565,7 +1565,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
max_clock = common_len - 1;
- if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
+ if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
pipe_config->has_pch_encoder = true;
pipe_config->has_drrs = false;
@@ -1707,7 +1707,7 @@ found:
to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
}
- if (!HAS_DDI(dev))
+ if (!HAS_DDI(dev_priv))
intel_dp_set_clock(encoder, pipe_config);
return true;
@@ -2632,7 +2632,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
dp_train_pat & DP_TRAINING_PATTERN_MASK);
- if (HAS_DDI(dev)) {
+ if (HAS_DDI(dev_priv)) {
uint32_t temp = I915_READ(DP_TP_CTL(port));
if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
@@ -3339,7 +3339,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
uint32_t signal_levels, mask = 0;
uint8_t train_set = intel_dp->train_set[0];
- if (HAS_DDI(dev)) {
+ if (HAS_DDI(dev_priv)) {
signal_levels = ddi_signal_levels(intel_dp);
if (IS_BROXTON(dev))
@@ -3398,7 +3398,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
enum port port = intel_dig_port->port;
uint32_t val;
- if (!HAS_DDI(dev))
+ if (!HAS_DDI(dev_priv))
return;
val = I915_READ(DP_TP_CTL(port));
@@ -3433,7 +3433,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = to_i915(dev);
uint32_t DP = intel_dp->DP;
- if (WARN_ON(HAS_DDI(dev)))
+ if (WARN_ON(HAS_DDI(dev_priv)))
return;
if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
@@ -5659,7 +5659,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
else
intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
- if (HAS_DDI(dev))
+ if (HAS_DDI(dev_priv))
intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
/* Preserve the current hw state. */
@@ -5701,7 +5701,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
intel_connector_attach_encoder(intel_connector, intel_encoder);
- if (HAS_DDI(dev))
+ if (HAS_DDI(dev_priv))
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
else
intel_connector->get_hw_state = intel_connector_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 1c59ca50c430..d0c59c1793ef 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1855,7 +1855,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
dpll_mgr = &skl_pll_mgr;
else if (IS_BROXTON(dev))
dpll_mgr = &bxt_pll_mgr;
- else if (HAS_DDI(dev))
+ else if (HAS_DDI(dev_priv))
dpll_mgr = &hsw_pll_mgr;
else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
dpll_mgr = &pch_pll_mgr;
@@ -1883,7 +1883,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
/* FIXME: Move this to a more suitable place */
- if (HAS_DDI(dev))
+ if (HAS_DDI(dev_priv))
intel_ddi_pll_init(dev);
}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 8d46f5836746..09b2146f157f 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -50,7 +50,7 @@ assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
struct drm_i915_private *dev_priv = to_i915(dev);
uint32_t enabled_bits;
- enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
+ enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
"HDMI port enabled, expecting disabled\n");
@@ -1312,7 +1312,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
struct drm_connector_state *conn_state)
{
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
int clock_12bpc = clock_8bpc * 3 / 2;
@@ -1339,7 +1339,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
clock_12bpc *= 2;
}
- if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
+ if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
pipe_config->has_pch_encoder = true;
if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
@@ -1892,7 +1892,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
intel_hdmi->write_infoframe = g4x_write_infoframe;
intel_hdmi->set_infoframes = g4x_set_infoframes;
intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
- } else if (HAS_DDI(dev)) {
+ } else if (HAS_DDI(dev_priv)) {
intel_hdmi->write_infoframe = hsw_write_infoframe;
intel_hdmi->set_infoframes = hsw_set_infoframes;
intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
@@ -1906,7 +1906,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
}
- if (HAS_DDI(dev))
+ if (HAS_DDI(dev_priv))
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
else
intel_connector->get_hw_state = intel_connector_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7f1748a1e614..e7b3e6f39281 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7132,7 +7132,7 @@ static void lpt_init_clock_gating(struct drm_device *dev)
* TODO: this bit should only be enabled when really needed, then
* disabled when not needed anymore in order to save power.
*/
- if (HAS_PCH_LPT_LP(dev))
+ if (HAS_PCH_LPT_LP(dev_priv))
I915_WRITE(SOUTH_DSPCLK_GATE_D,
I915_READ(SOUTH_DSPCLK_GATE_D) |
PCH_LP_PARTITION_LEVEL_DISABLE);
@@ -7147,7 +7147,7 @@ static void lpt_suspend_hw(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- if (HAS_PCH_LPT_LP(dev)) {
+ if (HAS_PCH_LPT_LP(dev_priv)) {
uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 108ba1e5d658..9e2fbac9776e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -344,7 +344,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
* ones. Since by Display design transcoder EDP is tied to port A
* we can safely escape based on the port A.
*/
- if (HAS_DDI(dev) && dig_port->port != PORT_A) {
+ if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) {
DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
return false;
}
@@ -402,7 +402,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
lockdep_assert_held(&dev_priv->psr.lock);
/* Enable/Re-enable PSR on the host */
- if (HAS_DDI(dev))
+ if (HAS_DDI(dev_priv))
/* On HSW+ after we enable PSR on source it will activate it
* as soon as it match configure idle_frame count. So
* we just actually enable it here on activation time.
@@ -448,7 +448,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
dev_priv->psr.busy_frontbuffer_bits = 0;
- if (HAS_DDI(dev)) {
+ if (HAS_DDI(dev_priv)) {
hsw_psr_setup_vsc(intel_dp);
if (dev_priv->psr.psr2_support) {
@@ -580,7 +580,7 @@ void intel_psr_disable(struct intel_dp *intel_dp)
}
/* Disable PSR on Source */
- if (HAS_DDI(dev))
+ if (HAS_DDI(dev_priv))
hsw_psr_disable(intel_dp);
else
vlv_psr_disable(intel_dp);
--
2.7.4
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^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 01/19] drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv
2016-10-11 13:21 ` [PATCH 01/19] drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv Tvrtko Ursulin
@ 2016-10-12 10:40 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 10:40 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:34PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> This saves 3248 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
How come you didn't do HAS_PCH_LPT_{LP,H} together with
the rest of the PCH-macros, BTW?
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 8 +++---
> drivers/gpu/drm/i915/intel_crt.c | 10 +++----
> drivers/gpu/drm/i915/intel_display.c | 49 ++++++++++++++++++-----------------
> drivers/gpu/drm/i915/intel_dp.c | 16 ++++++------
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +--
> drivers/gpu/drm/i915/intel_hdmi.c | 10 +++----
> drivers/gpu/drm/i915/intel_pm.c | 4 +--
> drivers/gpu/drm/i915/intel_psr.c | 8 +++---
> 8 files changed, 56 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 54d860e1c0fc..51dd10f25f59 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2815,7 +2815,7 @@ struct drm_i915_cmd_table {
>
> #define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst)
>
> -#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
> +#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
> #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
> #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
> #define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm)
> @@ -2854,8 +2854,10 @@ struct drm_i915_cmd_table {
> #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
> #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
> #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
> -#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> -#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
> +#define HAS_PCH_LPT_LP(dev_priv) \
> + ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> +#define HAS_PCH_LPT_H(dev_priv) \
> + ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
> #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
> #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
> #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 4a7b6c595ec2..d4b9b166de5d 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -280,13 +280,13 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (HAS_PCH_SPLIT(dev))
> + if (HAS_PCH_SPLIT(dev_priv))
> pipe_config->has_pch_encoder = true;
>
> /* LPT FDI RX only supports 8bpc. */
> - if (HAS_PCH_LPT(dev)) {
> + if (HAS_PCH_LPT(dev_priv)) {
> if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
> DRM_DEBUG_KMS("LPT only supports 24bpp\n");
> return false;
> @@ -296,7 +296,7 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
> }
>
> /* FDI must always be 2.7 GHz */
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> pipe_config->port_clock = 135000 * 2;
>
> return true;
> @@ -917,7 +917,7 @@ void intel_crt_init(struct drm_device *dev)
> if (I915_HAS_HOTPLUG(dev) &&
> !dmi_check_system(intel_spurious_crt_detect))
> crt->base.hpd_pin = HPD_CRT;
> - if (HAS_DDI(dev)) {
> + if (HAS_DDI(dev_priv)) {
> crt->base.port = PORT_E;
> crt->base.get_config = hsw_crt_get_config;
> crt->base.get_hw_state = intel_ddi_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 23a6c7213eca..6e447b575413 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1187,19 +1187,17 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
> onoff(state), onoff(cur_state));
> }
>
> -void assert_panel_unlocked(struct drm_i915_private *dev_priv,
> - enum pipe pipe)
> +void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
> {
> - struct drm_device *dev = &dev_priv->drm;
> i915_reg_t pp_reg;
> u32 val;
> enum pipe panel_pipe = PIPE_A;
> bool locked = true;
>
> - if (WARN_ON(HAS_DDI(dev)))
> + if (WARN_ON(HAS_DDI(dev_priv)))
> return;
>
> - if (HAS_PCH_SPLIT(dev)) {
> + if (HAS_PCH_SPLIT(dev_priv)) {
> u32 port_sel;
>
> pp_reg = PP_CONTROL(0);
> @@ -1209,7 +1207,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv,
> I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
> panel_pipe = PIPE_B;
> /* XXX: else fix for eDP */
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> /* presumably write lock depends on pipe, not port select */
> pp_reg = PP_CONTROL(pipe);
> panel_pipe = pipe;
> @@ -5698,13 +5696,13 @@ static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
> enum intel_display_power_domain
> intel_display_port_power_domain(struct intel_encoder *intel_encoder)
> {
> - struct drm_device *dev = intel_encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
> struct intel_digital_port *intel_dig_port;
>
> switch (intel_encoder->type) {
> case INTEL_OUTPUT_UNKNOWN:
> /* Only DDI platforms should ever use this output type */
> - WARN_ON_ONCE(!HAS_DDI(dev));
> + WARN_ON_ONCE(!HAS_DDI(dev_priv));
> case INTEL_OUTPUT_DP:
> case INTEL_OUTPUT_HDMI:
> case INTEL_OUTPUT_EDP:
> @@ -5725,7 +5723,7 @@ intel_display_port_power_domain(struct intel_encoder *intel_encoder)
> enum intel_display_power_domain
> intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
> {
> - struct drm_device *dev = intel_encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
> struct intel_digital_port *intel_dig_port;
>
> switch (intel_encoder->type) {
> @@ -5738,7 +5736,7 @@ intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
> * what's the status of the given connectors, play safe and
> * run the DP detection too.
> */
> - WARN_ON_ONCE(!HAS_DDI(dev));
> + WARN_ON_ONCE(!HAS_DDI(dev_priv));
> case INTEL_OUTPUT_DP:
> case INTEL_OUTPUT_EDP:
> intel_dig_port = enc_to_dig_port(&intel_encoder->base);
> @@ -9198,7 +9196,8 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
>
> if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
> with_spread = true;
> - if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
> + if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
> + with_fdi, "LP PCH doesn't have FDI\n"))
> with_fdi = false;
>
> mutex_lock(&dev_priv->sb_lock);
> @@ -9221,7 +9220,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
> }
> }
>
> - reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
> + reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
> tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
> tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
> intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
> @@ -9237,7 +9236,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev)
>
> mutex_lock(&dev_priv->sb_lock);
>
> - reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
> + reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
> tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
> tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
> intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
> @@ -10205,7 +10204,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv)
>
> DRM_DEBUG_KMS("Enabling package C8+\n");
>
> - if (HAS_PCH_LPT_LP(dev)) {
> + if (HAS_PCH_LPT_LP(dev_priv)) {
> val = I915_READ(SOUTH_DSPCLK_GATE_D);
> val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> @@ -10225,7 +10224,7 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
> hsw_restore_lcpll(dev_priv);
> lpt_init_pch_refclk(dev);
>
> - if (HAS_PCH_LPT_LP(dev)) {
> + if (HAS_PCH_LPT_LP(dev_priv)) {
> val = I915_READ(SOUTH_DSPCLK_GATE_D);
> val |= PCH_LP_PARTITION_LEVEL_DISABLE;
> I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> @@ -10847,7 +10846,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
> }
> cntl |= pipe << 28; /* Connect to correct pipe */
>
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> cntl |= CURSOR_PIPE_CSC_ENABLE;
>
> if (plane_state->base.rotation == DRM_ROTATE_180)
> @@ -12747,6 +12746,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> const char *context)
> {
> struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_plane *plane;
> struct intel_plane *intel_plane;
> struct intel_plane_state *state;
> @@ -12829,7 +12829,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> pipe_config->dpll_hw_state.ctrl1,
> pipe_config->dpll_hw_state.cfgcr1,
> pipe_config->dpll_hw_state.cfgcr2);
> - } else if (HAS_DDI(dev)) {
> + } else if (HAS_DDI(dev_priv)) {
> DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
> pipe_config->dpll_hw_state.wrpll,
> pipe_config->dpll_hw_state.spll);
> @@ -12907,7 +12907,7 @@ static bool check_digital_port_conflicts(struct drm_atomic_state *state)
> switch (encoder->type) {
> unsigned int port_mask;
> case INTEL_OUTPUT_UNKNOWN:
> - if (WARN_ON(!HAS_DDI(dev)))
> + if (WARN_ON(!HAS_DDI(to_i915(dev))))
> break;
> case INTEL_OUTPUT_DP:
> case INTEL_OUTPUT_HDMI:
> @@ -13731,7 +13731,7 @@ intel_modeset_verify_disabled(struct drm_device *dev)
>
> static void update_scanline_offset(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> /*
> * The scanline counter increments at the leading edge of hsync.
> @@ -13751,7 +13751,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
> * there's an extra 1 line difference. So we need to add two instead of
> * one to the value.
> */
> - if (IS_GEN2(dev)) {
> + if (IS_GEN2(dev_priv)) {
> const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
> int vtotal;
>
> @@ -13760,7 +13760,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
> vtotal /= 2;
>
> crtc->scanline_offset = vtotal - 1;
> - } else if (HAS_DDI(dev) &&
> + } else if (HAS_DDI(dev_priv) &&
> intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
> crtc->scanline_offset = 2;
> } else
> @@ -15329,11 +15329,12 @@ static bool intel_crt_present(struct drm_device *dev)
> if (IS_CHERRYVIEW(dev))
> return false;
>
> - if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
> + if (HAS_PCH_LPT_H(dev_priv) &&
> + I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
> return false;
>
> /* DDI E can't be used if DDI A requires 4 lanes */
> - if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
> + if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
> return false;
>
> if (!dev_priv->vbt.int_crt_support)
> @@ -15407,7 +15408,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> intel_ddi_init(dev, PORT_C);
>
> intel_dsi_init(dev);
> - } else if (HAS_DDI(dev)) {
> + } else if (HAS_DDI(dev_priv)) {
> int found;
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5992093e1814..edaf35b975c0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1565,7 +1565,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>
> max_clock = common_len - 1;
>
> - if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
> + if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
> pipe_config->has_pch_encoder = true;
>
> pipe_config->has_drrs = false;
> @@ -1707,7 +1707,7 @@ found:
> to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
> }
>
> - if (!HAS_DDI(dev))
> + if (!HAS_DDI(dev_priv))
> intel_dp_set_clock(encoder, pipe_config);
>
> return true;
> @@ -2632,7 +2632,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
> dp_train_pat & DP_TRAINING_PATTERN_MASK);
>
> - if (HAS_DDI(dev)) {
> + if (HAS_DDI(dev_priv)) {
> uint32_t temp = I915_READ(DP_TP_CTL(port));
>
> if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
> @@ -3339,7 +3339,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> uint32_t signal_levels, mask = 0;
> uint8_t train_set = intel_dp->train_set[0];
>
> - if (HAS_DDI(dev)) {
> + if (HAS_DDI(dev_priv)) {
> signal_levels = ddi_signal_levels(intel_dp);
>
> if (IS_BROXTON(dev))
> @@ -3398,7 +3398,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
> enum port port = intel_dig_port->port;
> uint32_t val;
>
> - if (!HAS_DDI(dev))
> + if (!HAS_DDI(dev_priv))
> return;
>
> val = I915_READ(DP_TP_CTL(port));
> @@ -3433,7 +3433,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = to_i915(dev);
> uint32_t DP = intel_dp->DP;
>
> - if (WARN_ON(HAS_DDI(dev)))
> + if (WARN_ON(HAS_DDI(dev_priv)))
> return;
>
> if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
> @@ -5659,7 +5659,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> else
> intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
>
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
>
> /* Preserve the current hw state. */
> @@ -5701,7 +5701,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>
> intel_connector_attach_encoder(intel_connector, intel_encoder);
>
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
> else
> intel_connector->get_hw_state = intel_connector_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 1c59ca50c430..d0c59c1793ef 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1855,7 +1855,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> dpll_mgr = &skl_pll_mgr;
> else if (IS_BROXTON(dev))
> dpll_mgr = &bxt_pll_mgr;
> - else if (HAS_DDI(dev))
> + else if (HAS_DDI(dev_priv))
> dpll_mgr = &hsw_pll_mgr;
> else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> dpll_mgr = &pch_pll_mgr;
> @@ -1883,7 +1883,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
>
> /* FIXME: Move this to a more suitable place */
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> intel_ddi_pll_init(dev);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 8d46f5836746..09b2146f157f 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -50,7 +50,7 @@ assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
> struct drm_i915_private *dev_priv = to_i915(dev);
> uint32_t enabled_bits;
>
> - enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
> + enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
>
> WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
> "HDMI port enabled, expecting disabled\n");
> @@ -1312,7 +1312,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
> struct drm_connector_state *conn_state)
> {
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
> int clock_12bpc = clock_8bpc * 3 / 2;
> @@ -1339,7 +1339,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
> clock_12bpc *= 2;
> }
>
> - if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
> + if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
> pipe_config->has_pch_encoder = true;
>
> if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
> @@ -1892,7 +1892,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> intel_hdmi->write_infoframe = g4x_write_infoframe;
> intel_hdmi->set_infoframes = g4x_set_infoframes;
> intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
> - } else if (HAS_DDI(dev)) {
> + } else if (HAS_DDI(dev_priv)) {
> intel_hdmi->write_infoframe = hsw_write_infoframe;
> intel_hdmi->set_infoframes = hsw_set_infoframes;
> intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
> @@ -1906,7 +1906,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
> }
>
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
> else
> intel_connector->get_hw_state = intel_connector_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7f1748a1e614..e7b3e6f39281 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7132,7 +7132,7 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> * TODO: this bit should only be enabled when really needed, then
> * disabled when not needed anymore in order to save power.
> */
> - if (HAS_PCH_LPT_LP(dev))
> + if (HAS_PCH_LPT_LP(dev_priv))
> I915_WRITE(SOUTH_DSPCLK_GATE_D,
> I915_READ(SOUTH_DSPCLK_GATE_D) |
> PCH_LP_PARTITION_LEVEL_DISABLE);
> @@ -7147,7 +7147,7 @@ static void lpt_suspend_hw(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (HAS_PCH_LPT_LP(dev)) {
> + if (HAS_PCH_LPT_LP(dev_priv)) {
> uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
>
> val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 108ba1e5d658..9e2fbac9776e 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -344,7 +344,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> * ones. Since by Display design transcoder EDP is tied to port A
> * we can safely escape based on the port A.
> */
> - if (HAS_DDI(dev) && dig_port->port != PORT_A) {
> + if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) {
> DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
> return false;
> }
> @@ -402,7 +402,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
> lockdep_assert_held(&dev_priv->psr.lock);
>
> /* Enable/Re-enable PSR on the host */
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> /* On HSW+ after we enable PSR on source it will activate it
> * as soon as it match configure idle_frame count. So
> * we just actually enable it here on activation time.
> @@ -448,7 +448,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>
> dev_priv->psr.busy_frontbuffer_bits = 0;
>
> - if (HAS_DDI(dev)) {
> + if (HAS_DDI(dev_priv)) {
> hsw_psr_setup_vsc(intel_dp);
>
> if (dev_priv->psr.psr2_support) {
> @@ -580,7 +580,7 @@ void intel_psr_disable(struct intel_dp *intel_dp)
> }
>
> /* Disable PSR on Source */
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> hsw_psr_disable(intel_dp);
> else
> vlv_psr_disable(intel_dp);
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 02/19] drm/i915: Make INTEL_PCH_TYPE & co only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
2016-10-11 13:21 ` [PATCH 01/19] drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 9:33 ` David Weinehall
2016-10-11 13:21 ` [PATCH 03/19] drm/i915: Make HAS_GMCH_DISPLAY " Tvrtko Ursulin
` (18 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
This saves 1872 bytes of .rodata strings.
v2:
* Rebase.
* Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 16 ++++++------
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +--
drivers/gpu/drm/i915/i915_irq.c | 20 +++++++--------
drivers/gpu/drm/i915/intel_audio.c | 2 +-
drivers/gpu/drm/i915/intel_crt.c | 25 +++++++++---------
drivers/gpu/drm/i915/intel_display.c | 48 ++++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_dp.c | 27 ++++++++++----------
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/intel_hdmi.c | 19 +++++++-------
drivers/gpu/drm/i915/intel_i2c.c | 2 +-
drivers/gpu/drm/i915/intel_lvds.c | 22 ++++++++--------
drivers/gpu/drm/i915/intel_pm.c | 6 ++---
drivers/gpu/drm/i915/intel_sdvo.c | 12 ++++-----
14 files changed, 107 insertions(+), 100 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 51dd10f25f59..3caa1c767512 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2850,18 +2850,18 @@ struct drm_i915_cmd_table {
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
-#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
-#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
-#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
-#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
+#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
+#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
+#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
+#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
#define HAS_PCH_LPT_LP(dev_priv) \
((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
#define HAS_PCH_LPT_H(dev_priv) \
((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
-#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
-#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
-#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
-#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
+#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
+#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
+#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
+#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fdd496e6c081..6b099f0198cc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4365,7 +4365,7 @@ i915_gem_init_hw(struct drm_device *dev)
I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
- if (HAS_PCH_NOP(dev)) {
+ if (HAS_PCH_NOP(dev_priv)) {
if (IS_IVYBRIDGE(dev)) {
u32 temp = I915_READ(GEN7_MSG_CTL);
temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index b5b58692ac5a..d41517e11978 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -421,7 +421,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
for (i = 0; i < 4; i++)
err_printf(m, "GTIER gt %d: 0x%08x\n", i,
error->gtier[i]);
- } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
+ } else if (HAS_PCH_SPLIT(dev_priv) || IS_VALLEYVIEW(dev_priv))
err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
@@ -1393,7 +1393,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
error->ier = I915_READ(GEN8_DE_MISC_IER);
for (i = 0; i < 4; i++)
error->gtier[i] = I915_READ(GEN8_GT_IER(i));
- } else if (HAS_PCH_SPLIT(dev)) {
+ } else if (HAS_PCH_SPLIT(dev_priv)) {
error->ier = I915_READ(DEIER);
error->gtier[0] = I915_READ(GTIER);
} else if (IS_GEN2(dev)) {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index bd6c8b0eeaef..883474411aee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3237,12 +3237,12 @@ static void ibx_irq_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- if (HAS_PCH_NOP(dev))
+ if (HAS_PCH_NOP(dev_priv))
return;
GEN5_IRQ_RESET(SDE);
- if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
+ if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
I915_WRITE(SERR_INT, 0xffffffff);
}
@@ -3258,7 +3258,7 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- if (HAS_PCH_NOP(dev))
+ if (HAS_PCH_NOP(dev_priv))
return;
WARN_ON(I915_READ(SDEIER) != 0);
@@ -3383,7 +3383,7 @@ static void gen8_irq_reset(struct drm_device *dev)
GEN5_IRQ_RESET(GEN8_DE_MISC_);
GEN5_IRQ_RESET(GEN8_PCU_);
- if (HAS_PCH_SPLIT(dev))
+ if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_reset(dev);
}
@@ -3572,10 +3572,10 @@ static void ibx_irq_postinstall(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev);
u32 mask;
- if (HAS_PCH_NOP(dev))
+ if (HAS_PCH_NOP(dev_priv))
return;
- if (HAS_PCH_IBX(dev))
+ if (HAS_PCH_IBX(dev_priv))
mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
else
mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
@@ -3796,13 +3796,13 @@ static int gen8_irq_postinstall(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- if (HAS_PCH_SPLIT(dev))
+ if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_pre_postinstall(dev);
gen8_gt_irq_postinstall(dev_priv);
gen8_de_irq_postinstall(dev_priv);
- if (HAS_PCH_SPLIT(dev))
+ if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev);
I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
@@ -4599,11 +4599,11 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->disable_vblank = gen8_disable_vblank;
if (IS_BROXTON(dev))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
- else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
+ else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
else
dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
- } else if (HAS_PCH_SPLIT(dev)) {
+ } else if (HAS_PCH_SPLIT(dev_priv)) {
dev->driver->irq_handler = ironlake_irq_handler;
dev->driver->irq_preinstall = ironlake_irq_reset;
dev->driver->irq_postinstall = ironlake_irq_postinstall;
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 9583f432e02e..13b726916f98 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -423,7 +423,7 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
* infrastructure is not there yet.
*/
- if (HAS_PCH_IBX(connector->dev)) {
+ if (HAS_PCH_IBX(dev_priv)) {
hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
aud_config = IBX_AUD_CFG(pipe);
aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index d4b9b166de5d..f8919ef3a7af 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -84,7 +84,7 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
if (!(tmp & ADPA_DAC_ENABLE))
goto out;
- if (HAS_PCH_CPT(dev))
+ if (HAS_PCH_CPT(dev_priv))
*pipe = PORT_TO_PIPE_CPT(tmp);
else
*pipe = PORT_TO_PIPE(tmp);
@@ -165,16 +165,16 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
adpa |= ADPA_VSYNC_ACTIVE_HIGH;
/* For CPT allow 3 pipe config, for others just use A or B */
- if (HAS_PCH_LPT(dev))
+ if (HAS_PCH_LPT(dev_priv))
; /* Those bits don't exist here */
- else if (HAS_PCH_CPT(dev))
+ else if (HAS_PCH_CPT(dev_priv))
adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
else if (crtc->pipe == 0)
adpa |= ADPA_PIPE_A_SELECT;
else
adpa |= ADPA_PIPE_B_SELECT;
- if (!HAS_PCH_SPLIT(dev))
+ if (!HAS_PCH_SPLIT(dev_priv))
I915_WRITE(BCLRPAT(crtc->pipe), 0);
switch (mode) {
@@ -241,7 +241,8 @@ intel_crt_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
struct drm_device *dev = connector->dev;
- int max_dotclk = to_i915(dev)->max_dotclk_freq;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ int max_dotclk = dev_priv->max_dotclk_freq;
int max_clock;
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -250,7 +251,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
if (mode->clock < 25000)
return MODE_CLOCK_LOW;
- if (HAS_PCH_LPT(dev))
+ if (HAS_PCH_LPT(dev_priv))
max_clock = 180000;
else if (IS_VALLEYVIEW(dev))
/*
@@ -269,7 +270,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
return MODE_CLOCK_HIGH;
/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
- if (HAS_PCH_LPT(dev) &&
+ if (HAS_PCH_LPT(dev_priv) &&
(ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
return MODE_CLOCK_HIGH;
@@ -312,7 +313,7 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
/* The first time through, trigger an explicit detection cycle */
if (crt->force_hotplug_required) {
- bool turn_off_dac = HAS_PCH_SPLIT(dev);
+ bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
u32 save_adpa;
crt->force_hotplug_required = 0;
@@ -419,7 +420,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
bool ret = false;
int i, tries = 0;
- if (HAS_PCH_SPLIT(dev))
+ if (HAS_PCH_SPLIT(dev_priv))
return intel_ironlake_crt_detect_hotplug(connector);
if (IS_VALLEYVIEW(dev))
@@ -847,7 +848,7 @@ void intel_crt_init(struct drm_device *dev)
i915_reg_t adpa_reg;
u32 adpa;
- if (HAS_PCH_SPLIT(dev))
+ if (HAS_PCH_SPLIT(dev_priv))
adpa_reg = PCH_ADPA;
else if (IS_VALLEYVIEW(dev))
adpa_reg = VLV_ADPA;
@@ -907,7 +908,7 @@ void intel_crt_init(struct drm_device *dev)
crt->adpa_reg = adpa_reg;
crt->base.compute_config = intel_crt_compute_config;
- if (HAS_PCH_SPLIT(dev)) {
+ if (HAS_PCH_SPLIT(dev_priv)) {
crt->base.disable = pch_disable_crt;
crt->base.post_disable = pch_post_disable_crt;
} else {
@@ -944,7 +945,7 @@ void intel_crt_init(struct drm_device *dev)
* polarity and link reversal bits or not, instead of relying on the
* BIOS.
*/
- if (HAS_PCH_LPT(dev)) {
+ if (HAS_PCH_LPT(dev_priv)) {
u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
FDI_RX_LINK_REVERSAL_OVERRIDE;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6e447b575413..0a69e80821ee 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1784,7 +1784,6 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
- struct drm_device *dev = &dev_priv->drm;
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
i915_reg_t reg;
@@ -1797,7 +1796,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
assert_fdi_tx_enabled(dev_priv, pipe);
assert_fdi_rx_enabled(dev_priv, pipe);
- if (HAS_PCH_CPT(dev)) {
+ if (HAS_PCH_CPT(dev_priv)) {
/* Workaround: Set the timing override bit before enabling the
* pch transcoder. */
reg = TRANS_CHICKEN2(pipe);
@@ -1875,7 +1874,6 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
- struct drm_device *dev = &dev_priv->drm;
i915_reg_t reg;
uint32_t val;
@@ -1896,7 +1894,7 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
50))
DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
- if (HAS_PCH_CPT(dev)) {
+ if (HAS_PCH_CPT(dev_priv)) {
/* Workaround: Clear the timing override chicken bit again. */
reg = TRANS_CHICKEN2(pipe);
val = I915_READ(reg);
@@ -3712,7 +3710,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
if (pipe_config->pch_pfit.enabled)
skylake_pfit_enable(crtc);
- } else if (HAS_PCH_SPLIT(dev)) {
+ } else if (HAS_PCH_SPLIT(dev_priv)) {
if (pipe_config->pch_pfit.enabled)
ironlake_pfit_enable(crtc);
else if (old_crtc_state->pch_pfit.enabled)
@@ -3743,7 +3741,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
reg = FDI_RX_CTL(pipe);
temp = I915_READ(reg);
- if (HAS_PCH_CPT(dev)) {
+ if (HAS_PCH_CPT(dev_priv)) {
temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
temp |= FDI_LINK_TRAIN_NORMAL_CPT;
} else {
@@ -3901,7 +3899,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
reg = FDI_RX_CTL(pipe);
temp = I915_READ(reg);
- if (HAS_PCH_CPT(dev)) {
+ if (HAS_PCH_CPT(dev_priv)) {
temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
} else {
@@ -3954,7 +3952,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
reg = FDI_RX_CTL(pipe);
temp = I915_READ(reg);
- if (HAS_PCH_CPT(dev)) {
+ if (HAS_PCH_CPT(dev_priv)) {
temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
} else {
@@ -4208,7 +4206,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
udelay(100);
/* Ironlake workaround, disable clock pointer after downing FDI */
- if (HAS_PCH_IBX(dev))
+ if (HAS_PCH_IBX(dev_priv))
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
/* still set train pattern 1 */
@@ -4220,7 +4218,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
reg = FDI_RX_CTL(pipe);
temp = I915_READ(reg);
- if (HAS_PCH_CPT(dev)) {
+ if (HAS_PCH_CPT(dev_priv)) {
temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
} else {
@@ -4556,7 +4554,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
/* We need to program the right clock selection before writing the pixel
* mutliplier into the DPLL. */
- if (HAS_PCH_CPT(dev)) {
+ if (HAS_PCH_CPT(dev_priv)) {
u32 sel;
temp = I915_READ(PCH_DPLL_SEL);
@@ -4586,7 +4584,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
intel_fdi_normal_train(crtc);
/* For PCH DP, enable TRANS_DP_CTL */
- if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
+ if (HAS_PCH_CPT(dev_priv) &&
+ intel_crtc_has_dp_encoder(intel_crtc->config)) {
const struct drm_display_mode *adjusted_mode =
&intel_crtc->config->base.adjusted_mode;
u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
@@ -5380,7 +5379,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_enable(crtc, pipe_config, old_state);
- if (HAS_PCH_CPT(dev))
+ if (HAS_PCH_CPT(dev_priv))
cpt_verify_modeset(dev, intel_crtc->pipe);
/* Must wait for vblank to avoid spurious PCH FIFO underruns */
@@ -5562,7 +5561,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (intel_crtc->config->has_pch_encoder) {
ironlake_disable_pch_transcoder(dev_priv, pipe);
- if (HAS_PCH_CPT(dev)) {
+ if (HAS_PCH_CPT(dev_priv)) {
i915_reg_t reg;
u32 temp;
@@ -8948,7 +8947,7 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
}
}
- if (HAS_PCH_IBX(dev)) {
+ if (HAS_PCH_IBX(dev_priv)) {
has_ck505 = dev_priv->vbt.display_clock_mode;
can_ssc = has_ck505;
} else {
@@ -9344,9 +9343,11 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
*/
void intel_init_pch_refclk(struct drm_device *dev)
{
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
ironlake_init_pch_refclk(dev);
- else if (HAS_PCH_LPT(dev))
+ else if (HAS_PCH_LPT(dev_priv))
lpt_init_pch_refclk(dev);
}
@@ -9475,7 +9476,7 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if ((intel_panel_use_ssc(dev_priv) &&
dev_priv->vbt.lvds_ssc_freq == 100000) ||
- (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
+ (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
factor = 25;
} else if (crtc_state->sdvo_tv_clock)
factor = 20;
@@ -11313,7 +11314,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
return dev_priv->vbt.lvds_ssc_freq;
- else if (HAS_PCH_SPLIT(dev))
+ else if (HAS_PCH_SPLIT(dev_priv))
return 120000;
else if (!IS_GEN2(dev))
return 96000;
@@ -14898,6 +14899,7 @@ const struct drm_plane_funcs intel_plane_funcs = {
static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
int pipe)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_plane *primary = NULL;
struct intel_plane_state *state = NULL;
const uint32_t *intel_primary_formats;
@@ -14932,7 +14934,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
primary->update_plane = skylake_update_primary_plane;
primary->disable_plane = skylake_disable_primary_plane;
- } else if (HAS_PCH_SPLIT(dev)) {
+ } else if (HAS_PCH_SPLIT(dev_priv)) {
intel_primary_formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
@@ -15440,7 +15442,7 @@ static void intel_setup_outputs(struct drm_device *dev)
dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
intel_ddi_init(dev, PORT_E);
- } else if (HAS_PCH_SPLIT(dev)) {
+ } else if (HAS_PCH_SPLIT(dev_priv)) {
int found;
dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
@@ -16359,7 +16361,7 @@ void intel_modeset_init(struct drm_device *dev)
* BIOS isn't using it, don't assume it will work even if the VBT
* indicates as much.
*/
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
+ if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
DREF_SSC1_ENABLE);
@@ -16908,7 +16910,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
vlv_wm_get_hw_state(dev);
else if (IS_GEN9(dev))
skl_wm_get_hw_state(dev);
- else if (HAS_PCH_SPLIT(dev))
+ else if (HAS_PCH_SPLIT(dev_priv))
ilk_wm_get_hw_state(dev);
for_each_intel_crtc(dev, crtc) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index edaf35b975c0..0b6f1bab671d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1336,13 +1336,14 @@ intel_dp_set_clock(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
const struct dp_link_dpll *divisor = NULL;
int i, count = 0;
if (IS_G4X(dev)) {
divisor = gen4_dpll;
count = ARRAY_SIZE(gen4_dpll);
- } else if (HAS_PCH_SPLIT(dev)) {
+ } else if (HAS_PCH_SPLIT(dev_priv)) {
divisor = pch_dpll;
count = ARRAY_SIZE(pch_dpll);
} else if (IS_CHERRYVIEW(dev)) {
@@ -1776,7 +1777,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
intel_dp->DP |= DP_ENHANCED_FRAMING;
intel_dp->DP |= crtc->pipe << 29;
- } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
+ } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
u32 trans_dp;
intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
@@ -1788,7 +1789,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
trans_dp &= ~TRANS_DP_ENH_FRAMING;
I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
} else {
- if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
+ if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev) &&
!IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
intel_dp->DP |= DP_COLOR_RANGE_16_235;
@@ -2442,7 +2443,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
if (IS_GEN7(dev) && port == PORT_A) {
*pipe = PORT_TO_PIPE_CPT(tmp);
- } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
+ } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
enum pipe p;
for_each_pipe(dev_priv, p) {
@@ -2485,7 +2486,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
- if (HAS_PCH_CPT(dev) && port != PORT_A) {
+ if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
@@ -2511,8 +2512,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
pipe_config->base.adjusted_mode.flags |= flags;
- if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
- !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
+ if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
+ !IS_CHERRYVIEW(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
pipe_config->limited_color_range = true;
pipe_config->lane_count =
@@ -2659,7 +2660,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
I915_WRITE(DP_TP_CTL(port), temp);
} else if ((IS_GEN7(dev) && port == PORT_A) ||
- (HAS_PCH_CPT(dev) && port != PORT_A)) {
+ (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
*DP &= ~DP_LINK_TRAIN_MASK_CPT;
switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
@@ -2989,7 +2990,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (IS_GEN7(dev) && port == PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
- else if (HAS_PCH_CPT(dev) && port != PORT_A)
+ else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
@@ -3442,7 +3443,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("\n");
if ((IS_GEN7(dev) && port == PORT_A) ||
- (HAS_PCH_CPT(dev) && port != PORT_A)) {
+ (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
DP &= ~DP_LINK_TRAIN_MASK_CPT;
DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
} else {
@@ -3464,7 +3465,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
* to transcoder A after disabling it to allow the
* matching HDMI port to be enabled on transcoder A.
*/
- if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
+ if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
/*
* We get CPU/PCH FIFO underruns on the other pipe when
* doing the workaround. Sweep them under the rug.
@@ -5085,7 +5086,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
* power sequencer any more. */
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
port_sel = PANEL_PORT_SELECT_VLV(port);
- } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
+ } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
if (port == PORT_A)
port_sel = PANEL_PORT_SELECT_DPA;
else
@@ -5649,7 +5650,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
- else if (HAS_PCH_SPLIT(dev))
+ else if (HAS_PCH_SPLIT(dev_priv))
intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
else
intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index d0c59c1793ef..c37ce1263142 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1857,7 +1857,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
dpll_mgr = &bxt_pll_mgr;
else if (HAS_DDI(dev_priv))
dpll_mgr = &hsw_pll_mgr;
- else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+ else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
dpll_mgr = &pch_pll_mgr;
if (!dpll_mgr) {
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 09b2146f157f..397e10f4b6f0 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -864,7 +864,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
hdmi_val = SDVO_ENCODING_HDMI;
- if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
+ if (!HAS_PCH_SPLIT(dev_priv) && crtc->config->limited_color_range)
hdmi_val |= HDMI_COLOR_RANGE_16_235;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
@@ -879,7 +879,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
if (crtc->config->has_hdmi_sink)
hdmi_val |= HDMI_MODE_SELECT_HDMI;
- if (HAS_PCH_CPT(dev))
+ if (HAS_PCH_CPT(dev_priv))
hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
else if (IS_CHERRYVIEW(dev))
hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
@@ -911,7 +911,7 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
if (!(tmp & SDVO_ENABLE))
goto out;
- if (HAS_PCH_CPT(dev))
+ if (HAS_PCH_CPT(dev_priv))
*pipe = PORT_TO_PIPE_CPT(tmp);
else if (IS_CHERRYVIEW(dev))
*pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
@@ -956,7 +956,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
if (tmp & SDVO_AUDIO_ENABLE)
pipe_config->has_audio = true;
- if (!HAS_PCH_SPLIT(dev) &&
+ if (!HAS_PCH_SPLIT(dev_priv) &&
tmp & HDMI_COLOR_RANGE_16_235)
pipe_config->limited_color_range = true;
@@ -1141,7 +1141,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder,
* to transcoder A after disabling it to allow the
* matching DP port to be enabled on transcoder A.
*/
- if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
+ if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
/*
* We get CPU/PCH FIFO underruns on the other pipe when
* doing the workaround. Sweep them under the rug.
@@ -1896,7 +1896,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
intel_hdmi->write_infoframe = hsw_write_infoframe;
intel_hdmi->set_infoframes = hsw_set_infoframes;
intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
- } else if (HAS_PCH_IBX(dev)) {
+ } else if (HAS_PCH_IBX(dev_priv)) {
intel_hdmi->write_infoframe = ibx_write_infoframe;
intel_hdmi->set_infoframes = ibx_set_infoframes;
intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
@@ -1929,6 +1929,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
void intel_hdmi_init(struct drm_device *dev,
i915_reg_t hdmi_reg, enum port port)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_digital_port *intel_dig_port;
struct intel_encoder *intel_encoder;
struct intel_connector *intel_connector;
@@ -1949,7 +1950,7 @@ void intel_hdmi_init(struct drm_device *dev,
DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port));
intel_encoder->compute_config = intel_hdmi_compute_config;
- if (HAS_PCH_SPLIT(dev)) {
+ if (HAS_PCH_SPLIT(dev_priv)) {
intel_encoder->disable = pch_disable_hdmi;
intel_encoder->post_disable = pch_post_disable_hdmi;
} else {
@@ -1970,9 +1971,9 @@ void intel_hdmi_init(struct drm_device *dev,
intel_encoder->post_disable = vlv_hdmi_post_disable;
} else {
intel_encoder->pre_enable = intel_hdmi_pre_enable;
- if (HAS_PCH_CPT(dev))
+ if (HAS_PCH_CPT(dev_priv))
intel_encoder->enable = cpt_enable_hdmi;
- else if (HAS_PCH_IBX(dev))
+ else if (HAS_PCH_IBX(dev_priv))
intel_encoder->enable = ibx_enable_hdmi;
else
intel_encoder->enable = g4x_enable_hdmi;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 79aab9ad6faa..1410330ec9bb 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -633,7 +633,7 @@ int intel_setup_gmbus(struct drm_device *dev)
unsigned int pin;
int ret;
- if (HAS_PCH_NOP(dev))
+ if (HAS_PCH_NOP(dev_priv))
return 0;
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 2e943bd1c3cf..baaf2ed897ef 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -106,7 +106,7 @@ static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
if (!(tmp & LVDS_PORT_EN))
goto out;
- if (HAS_PCH_CPT(dev))
+ if (HAS_PCH_CPT(dev_priv))
*pipe = PORT_TO_PIPE_CPT(tmp);
else
*pipe = PORT_TO_PIPE(tmp);
@@ -396,7 +396,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
- struct drm_device *dev = intel_encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
struct intel_lvds_encoder *lvds_encoder =
to_lvds_encoder(&intel_encoder->base);
struct intel_connector *intel_connector =
@@ -406,7 +406,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
unsigned int lvds_bpp;
/* Should never happen!! */
- if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
+ if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
DRM_ERROR("Can't support LVDS on pipe A\n");
return false;
}
@@ -431,7 +431,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
adjusted_mode);
- if (HAS_PCH_SPLIT(dev)) {
+ if (HAS_PCH_SPLIT(dev_priv)) {
pipe_config->has_pch_encoder = true;
intel_pch_panel_fitting(intel_crtc, pipe_config,
@@ -566,7 +566,7 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
* and as part of the cleanup in the hw state restore we also redisable
* the vga plane.
*/
- if (!HAS_PCH_SPLIT(dev))
+ if (!HAS_PCH_SPLIT(dev_priv))
intel_display_resume(dev);
dev_priv->modeset_restore = MODESET_DONE;
@@ -951,9 +951,11 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
static bool intel_lvds_supported(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
/* With the introduction of the PCH we gained a dedicated
* LVDS presence pin, use it. */
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+ if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
return true;
/* Otherwise LVDS was only attached to mobile products,
@@ -997,14 +999,14 @@ void intel_lvds_init(struct drm_device *dev)
if (dmi_check_system(intel_no_lvds))
return;
- if (HAS_PCH_SPLIT(dev))
+ if (HAS_PCH_SPLIT(dev_priv))
lvds_reg = PCH_LVDS;
else
lvds_reg = LVDS;
lvds = I915_READ(lvds_reg);
- if (HAS_PCH_SPLIT(dev)) {
+ if (HAS_PCH_SPLIT(dev_priv)) {
if ((lvds & LVDS_DETECTED) == 0)
return;
if (dev_priv->vbt.edp.support) {
@@ -1068,7 +1070,7 @@ void intel_lvds_init(struct drm_device *dev)
intel_encoder->type = INTEL_OUTPUT_LVDS;
intel_encoder->port = PORT_NONE;
intel_encoder->cloneable = 0;
- if (HAS_PCH_SPLIT(dev))
+ if (HAS_PCH_SPLIT(dev_priv))
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
else if (IS_GEN4(dev))
intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
@@ -1158,7 +1160,7 @@ void intel_lvds_init(struct drm_device *dev)
*/
/* Ironlake: FIXME if still fail, not try pipe mode now */
- if (HAS_PCH_SPLIT(dev))
+ if (HAS_PCH_SPLIT(dev_priv))
goto failed;
pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e7b3e6f39281..86051ef2716e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7413,7 +7413,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
snpcr |= GEN6_MBC_SNPCR_MED;
I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
- if (!HAS_PCH_NOP(dev))
+ if (!HAS_PCH_NOP(dev_priv))
cpt_init_clock_gating(dev);
gen6_check_mch_setup(dev);
@@ -7656,7 +7656,7 @@ void intel_init_clock_gating(struct drm_device *dev)
void intel_suspend_hw(struct drm_device *dev)
{
- if (HAS_PCH_LPT(dev))
+ if (HAS_PCH_LPT(to_i915(dev)))
lpt_suspend_hw(dev);
}
@@ -7732,7 +7732,7 @@ void intel_init_pm(struct drm_device *dev)
skl_setup_wm_latency(dev);
dev_priv->display.update_wm = skl_update_wm;
dev_priv->display.compute_global_watermarks = skl_compute_wm;
- } else if (HAS_PCH_SPLIT(dev)) {
+ } else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev);
if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index a061b0029797..0d9114f9ce27 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -251,7 +251,7 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
* HW workaround, need to write this twice for issue
* that may result in first write getting masked.
*/
- if (HAS_PCH_IBX(dev)) {
+ if (HAS_PCH_IBX(dev_priv)) {
I915_WRITE(intel_sdvo->sdvo_reg, val);
POSTING_READ(intel_sdvo->sdvo_reg);
}
@@ -1133,7 +1133,7 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
pipe_config->pipe_bpp = 8*3;
- if (HAS_PCH_SPLIT(encoder->base.dev))
+ if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
pipe_config->has_pch_encoder = true;
/* We need to construct preferred input timings based on our
@@ -1273,7 +1273,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
/* The real mode polarity is set by the SDVO commands, using
* struct intel_sdvo_dtd. */
sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
- if (!HAS_PCH_SPLIT(dev) && crtc_state->limited_color_range)
+ if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
sdvox |= HDMI_COLOR_RANGE_16_235;
if (INTEL_INFO(dev)->gen < 5)
sdvox |= SDVO_BORDER_ENABLE;
@@ -1286,7 +1286,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
}
- if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_CPT)
sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
else
sdvox |= SDVO_PIPE_SEL(crtc->pipe);
@@ -1339,7 +1339,7 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
return false;
- if (HAS_PCH_CPT(dev))
+ if (HAS_PCH_CPT(dev_priv))
*pipe = PORT_TO_PIPE_CPT(tmp);
else
*pipe = PORT_TO_PIPE(tmp);
@@ -2997,7 +2997,7 @@ bool intel_sdvo_init(struct drm_device *dev,
}
intel_encoder->compute_config = intel_sdvo_compute_config;
- if (HAS_PCH_SPLIT(dev)) {
+ if (HAS_PCH_SPLIT(dev_priv)) {
intel_encoder->disable = pch_disable_sdvo;
intel_encoder->post_disable = pch_post_disable_sdvo;
} else {
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 02/19] drm/i915: Make INTEL_PCH_TYPE & co only take dev_priv
2016-10-11 13:21 ` [PATCH 02/19] drm/i915: Make INTEL_PCH_TYPE & co " Tvrtko Ursulin
@ 2016-10-12 9:33 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 9:33 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:35PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> This saves 1872 bytes of .rodata strings.
>
> v2:
> * Rebase.
> * Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 16 ++++++------
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 4 +--
> drivers/gpu/drm/i915/i915_irq.c | 20 +++++++--------
> drivers/gpu/drm/i915/intel_audio.c | 2 +-
> drivers/gpu/drm/i915/intel_crt.c | 25 +++++++++---------
> drivers/gpu/drm/i915/intel_display.c | 48 ++++++++++++++++++-----------------
> drivers/gpu/drm/i915/intel_dp.c | 27 ++++++++++----------
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/intel_hdmi.c | 19 +++++++-------
> drivers/gpu/drm/i915/intel_i2c.c | 2 +-
> drivers/gpu/drm/i915/intel_lvds.c | 22 ++++++++--------
> drivers/gpu/drm/i915/intel_pm.c | 6 ++---
> drivers/gpu/drm/i915/intel_sdvo.c | 12 ++++-----
> 14 files changed, 107 insertions(+), 100 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 51dd10f25f59..3caa1c767512 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2850,18 +2850,18 @@ struct drm_i915_cmd_table {
> #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
> #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
>
> -#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
> -#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
> -#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
> -#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
> +#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> +#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
> +#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
> +#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
> #define HAS_PCH_LPT_LP(dev_priv) \
> ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> #define HAS_PCH_LPT_H(dev_priv) \
> ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
> -#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
> -#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
> -#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
> -#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
> +#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
> +#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
> +#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
> +#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
>
> #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index fdd496e6c081..6b099f0198cc 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4365,7 +4365,7 @@ i915_gem_init_hw(struct drm_device *dev)
> I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
> LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>
> - if (HAS_PCH_NOP(dev)) {
> + if (HAS_PCH_NOP(dev_priv)) {
> if (IS_IVYBRIDGE(dev)) {
> u32 temp = I915_READ(GEN7_MSG_CTL);
> temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index b5b58692ac5a..d41517e11978 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -421,7 +421,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> for (i = 0; i < 4; i++)
> err_printf(m, "GTIER gt %d: 0x%08x\n", i,
> error->gtier[i]);
> - } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
> + } else if (HAS_PCH_SPLIT(dev_priv) || IS_VALLEYVIEW(dev_priv))
> err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
> err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
> err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
> @@ -1393,7 +1393,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> error->ier = I915_READ(GEN8_DE_MISC_IER);
> for (i = 0; i < 4; i++)
> error->gtier[i] = I915_READ(GEN8_GT_IER(i));
> - } else if (HAS_PCH_SPLIT(dev)) {
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> error->ier = I915_READ(DEIER);
> error->gtier[0] = I915_READ(GTIER);
> } else if (IS_GEN2(dev)) {
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index bd6c8b0eeaef..883474411aee 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3237,12 +3237,12 @@ static void ibx_irq_reset(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (HAS_PCH_NOP(dev))
> + if (HAS_PCH_NOP(dev_priv))
> return;
>
> GEN5_IRQ_RESET(SDE);
>
> - if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
> + if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
> I915_WRITE(SERR_INT, 0xffffffff);
> }
>
> @@ -3258,7 +3258,7 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (HAS_PCH_NOP(dev))
> + if (HAS_PCH_NOP(dev_priv))
> return;
>
> WARN_ON(I915_READ(SDEIER) != 0);
> @@ -3383,7 +3383,7 @@ static void gen8_irq_reset(struct drm_device *dev)
> GEN5_IRQ_RESET(GEN8_DE_MISC_);
> GEN5_IRQ_RESET(GEN8_PCU_);
>
> - if (HAS_PCH_SPLIT(dev))
> + if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_reset(dev);
> }
>
> @@ -3572,10 +3572,10 @@ static void ibx_irq_postinstall(struct drm_device *dev)
> struct drm_i915_private *dev_priv = to_i915(dev);
> u32 mask;
>
> - if (HAS_PCH_NOP(dev))
> + if (HAS_PCH_NOP(dev_priv))
> return;
>
> - if (HAS_PCH_IBX(dev))
> + if (HAS_PCH_IBX(dev_priv))
> mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
> else
> mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
> @@ -3796,13 +3796,13 @@ static int gen8_irq_postinstall(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (HAS_PCH_SPLIT(dev))
> + if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_pre_postinstall(dev);
>
> gen8_gt_irq_postinstall(dev_priv);
> gen8_de_irq_postinstall(dev_priv);
>
> - if (HAS_PCH_SPLIT(dev))
> + if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_postinstall(dev);
>
> I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
> @@ -4599,11 +4599,11 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev->driver->disable_vblank = gen8_disable_vblank;
> if (IS_BROXTON(dev))
> dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> - else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
> + else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
> dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> else
> dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
> - } else if (HAS_PCH_SPLIT(dev)) {
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> dev->driver->irq_handler = ironlake_irq_handler;
> dev->driver->irq_preinstall = ironlake_irq_reset;
> dev->driver->irq_postinstall = ironlake_irq_postinstall;
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 9583f432e02e..13b726916f98 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -423,7 +423,7 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
> * infrastructure is not there yet.
> */
>
> - if (HAS_PCH_IBX(connector->dev)) {
> + if (HAS_PCH_IBX(dev_priv)) {
> hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
> aud_config = IBX_AUD_CFG(pipe);
> aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index d4b9b166de5d..f8919ef3a7af 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -84,7 +84,7 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
> if (!(tmp & ADPA_DAC_ENABLE))
> goto out;
>
> - if (HAS_PCH_CPT(dev))
> + if (HAS_PCH_CPT(dev_priv))
> *pipe = PORT_TO_PIPE_CPT(tmp);
> else
> *pipe = PORT_TO_PIPE(tmp);
> @@ -165,16 +165,16 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
> adpa |= ADPA_VSYNC_ACTIVE_HIGH;
>
> /* For CPT allow 3 pipe config, for others just use A or B */
> - if (HAS_PCH_LPT(dev))
> + if (HAS_PCH_LPT(dev_priv))
> ; /* Those bits don't exist here */
> - else if (HAS_PCH_CPT(dev))
> + else if (HAS_PCH_CPT(dev_priv))
> adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
> else if (crtc->pipe == 0)
> adpa |= ADPA_PIPE_A_SELECT;
> else
> adpa |= ADPA_PIPE_B_SELECT;
>
> - if (!HAS_PCH_SPLIT(dev))
> + if (!HAS_PCH_SPLIT(dev_priv))
> I915_WRITE(BCLRPAT(crtc->pipe), 0);
>
> switch (mode) {
> @@ -241,7 +241,8 @@ intel_crt_mode_valid(struct drm_connector *connector,
> struct drm_display_mode *mode)
> {
> struct drm_device *dev = connector->dev;
> - int max_dotclk = to_i915(dev)->max_dotclk_freq;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + int max_dotclk = dev_priv->max_dotclk_freq;
> int max_clock;
>
> if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> @@ -250,7 +251,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
> if (mode->clock < 25000)
> return MODE_CLOCK_LOW;
>
> - if (HAS_PCH_LPT(dev))
> + if (HAS_PCH_LPT(dev_priv))
> max_clock = 180000;
> else if (IS_VALLEYVIEW(dev))
> /*
> @@ -269,7 +270,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
> return MODE_CLOCK_HIGH;
>
> /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
> - if (HAS_PCH_LPT(dev) &&
> + if (HAS_PCH_LPT(dev_priv) &&
> (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
> return MODE_CLOCK_HIGH;
>
> @@ -312,7 +313,7 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
>
> /* The first time through, trigger an explicit detection cycle */
> if (crt->force_hotplug_required) {
> - bool turn_off_dac = HAS_PCH_SPLIT(dev);
> + bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
> u32 save_adpa;
>
> crt->force_hotplug_required = 0;
> @@ -419,7 +420,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
> bool ret = false;
> int i, tries = 0;
>
> - if (HAS_PCH_SPLIT(dev))
> + if (HAS_PCH_SPLIT(dev_priv))
> return intel_ironlake_crt_detect_hotplug(connector);
>
> if (IS_VALLEYVIEW(dev))
> @@ -847,7 +848,7 @@ void intel_crt_init(struct drm_device *dev)
> i915_reg_t adpa_reg;
> u32 adpa;
>
> - if (HAS_PCH_SPLIT(dev))
> + if (HAS_PCH_SPLIT(dev_priv))
> adpa_reg = PCH_ADPA;
> else if (IS_VALLEYVIEW(dev))
> adpa_reg = VLV_ADPA;
> @@ -907,7 +908,7 @@ void intel_crt_init(struct drm_device *dev)
> crt->adpa_reg = adpa_reg;
>
> crt->base.compute_config = intel_crt_compute_config;
> - if (HAS_PCH_SPLIT(dev)) {
> + if (HAS_PCH_SPLIT(dev_priv)) {
> crt->base.disable = pch_disable_crt;
> crt->base.post_disable = pch_post_disable_crt;
> } else {
> @@ -944,7 +945,7 @@ void intel_crt_init(struct drm_device *dev)
> * polarity and link reversal bits or not, instead of relying on the
> * BIOS.
> */
> - if (HAS_PCH_LPT(dev)) {
> + if (HAS_PCH_LPT(dev_priv)) {
> u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
> FDI_RX_LINK_REVERSAL_OVERRIDE;
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6e447b575413..0a69e80821ee 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1784,7 +1784,6 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> - struct drm_device *dev = &dev_priv->drm;
> struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> i915_reg_t reg;
> @@ -1797,7 +1796,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> assert_fdi_tx_enabled(dev_priv, pipe);
> assert_fdi_rx_enabled(dev_priv, pipe);
>
> - if (HAS_PCH_CPT(dev)) {
> + if (HAS_PCH_CPT(dev_priv)) {
> /* Workaround: Set the timing override bit before enabling the
> * pch transcoder. */
> reg = TRANS_CHICKEN2(pipe);
> @@ -1875,7 +1874,6 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> - struct drm_device *dev = &dev_priv->drm;
> i915_reg_t reg;
> uint32_t val;
>
> @@ -1896,7 +1894,7 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
> 50))
> DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
>
> - if (HAS_PCH_CPT(dev)) {
> + if (HAS_PCH_CPT(dev_priv)) {
> /* Workaround: Clear the timing override chicken bit again. */
> reg = TRANS_CHICKEN2(pipe);
> val = I915_READ(reg);
> @@ -3712,7 +3710,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
>
> if (pipe_config->pch_pfit.enabled)
> skylake_pfit_enable(crtc);
> - } else if (HAS_PCH_SPLIT(dev)) {
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> if (pipe_config->pch_pfit.enabled)
> ironlake_pfit_enable(crtc);
> else if (old_crtc_state->pch_pfit.enabled)
> @@ -3743,7 +3741,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
>
> reg = FDI_RX_CTL(pipe);
> temp = I915_READ(reg);
> - if (HAS_PCH_CPT(dev)) {
> + if (HAS_PCH_CPT(dev_priv)) {
> temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
> temp |= FDI_LINK_TRAIN_NORMAL_CPT;
> } else {
> @@ -3901,7 +3899,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
>
> reg = FDI_RX_CTL(pipe);
> temp = I915_READ(reg);
> - if (HAS_PCH_CPT(dev)) {
> + if (HAS_PCH_CPT(dev_priv)) {
> temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
> temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
> } else {
> @@ -3954,7 +3952,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
>
> reg = FDI_RX_CTL(pipe);
> temp = I915_READ(reg);
> - if (HAS_PCH_CPT(dev)) {
> + if (HAS_PCH_CPT(dev_priv)) {
> temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
> temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
> } else {
> @@ -4208,7 +4206,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
> udelay(100);
>
> /* Ironlake workaround, disable clock pointer after downing FDI */
> - if (HAS_PCH_IBX(dev))
> + if (HAS_PCH_IBX(dev_priv))
> I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
>
> /* still set train pattern 1 */
> @@ -4220,7 +4218,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
>
> reg = FDI_RX_CTL(pipe);
> temp = I915_READ(reg);
> - if (HAS_PCH_CPT(dev)) {
> + if (HAS_PCH_CPT(dev_priv)) {
> temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
> temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
> } else {
> @@ -4556,7 +4554,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>
> /* We need to program the right clock selection before writing the pixel
> * mutliplier into the DPLL. */
> - if (HAS_PCH_CPT(dev)) {
> + if (HAS_PCH_CPT(dev_priv)) {
> u32 sel;
>
> temp = I915_READ(PCH_DPLL_SEL);
> @@ -4586,7 +4584,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> intel_fdi_normal_train(crtc);
>
> /* For PCH DP, enable TRANS_DP_CTL */
> - if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
> + if (HAS_PCH_CPT(dev_priv) &&
> + intel_crtc_has_dp_encoder(intel_crtc->config)) {
> const struct drm_display_mode *adjusted_mode =
> &intel_crtc->config->base.adjusted_mode;
> u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
> @@ -5380,7 +5379,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_encoders_enable(crtc, pipe_config, old_state);
>
> - if (HAS_PCH_CPT(dev))
> + if (HAS_PCH_CPT(dev_priv))
> cpt_verify_modeset(dev, intel_crtc->pipe);
>
> /* Must wait for vblank to avoid spurious PCH FIFO underruns */
> @@ -5562,7 +5561,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
> if (intel_crtc->config->has_pch_encoder) {
> ironlake_disable_pch_transcoder(dev_priv, pipe);
>
> - if (HAS_PCH_CPT(dev)) {
> + if (HAS_PCH_CPT(dev_priv)) {
> i915_reg_t reg;
> u32 temp;
>
> @@ -8948,7 +8947,7 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
> }
> }
>
> - if (HAS_PCH_IBX(dev)) {
> + if (HAS_PCH_IBX(dev_priv)) {
> has_ck505 = dev_priv->vbt.display_clock_mode;
> can_ssc = has_ck505;
> } else {
> @@ -9344,9 +9343,11 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
> */
> void intel_init_pch_refclk(struct drm_device *dev)
> {
> - if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> + if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
> ironlake_init_pch_refclk(dev);
> - else if (HAS_PCH_LPT(dev))
> + else if (HAS_PCH_LPT(dev_priv))
> lpt_init_pch_refclk(dev);
> }
>
> @@ -9475,7 +9476,7 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
> if ((intel_panel_use_ssc(dev_priv) &&
> dev_priv->vbt.lvds_ssc_freq == 100000) ||
> - (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
> + (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
> factor = 25;
> } else if (crtc_state->sdvo_tv_clock)
> factor = 20;
> @@ -11313,7 +11314,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
>
> if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
> return dev_priv->vbt.lvds_ssc_freq;
> - else if (HAS_PCH_SPLIT(dev))
> + else if (HAS_PCH_SPLIT(dev_priv))
> return 120000;
> else if (!IS_GEN2(dev))
> return 96000;
> @@ -14898,6 +14899,7 @@ const struct drm_plane_funcs intel_plane_funcs = {
> static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
> int pipe)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_plane *primary = NULL;
> struct intel_plane_state *state = NULL;
> const uint32_t *intel_primary_formats;
> @@ -14932,7 +14934,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
>
> primary->update_plane = skylake_update_primary_plane;
> primary->disable_plane = skylake_disable_primary_plane;
> - } else if (HAS_PCH_SPLIT(dev)) {
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> intel_primary_formats = i965_primary_formats;
> num_formats = ARRAY_SIZE(i965_primary_formats);
>
> @@ -15440,7 +15442,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
> intel_ddi_init(dev, PORT_E);
>
> - } else if (HAS_PCH_SPLIT(dev)) {
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> int found;
> dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
>
> @@ -16359,7 +16361,7 @@ void intel_modeset_init(struct drm_device *dev)
> * BIOS isn't using it, don't assume it will work even if the VBT
> * indicates as much.
> */
> - if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
> + if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
> bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
> DREF_SSC1_ENABLE);
>
> @@ -16908,7 +16910,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
> vlv_wm_get_hw_state(dev);
> else if (IS_GEN9(dev))
> skl_wm_get_hw_state(dev);
> - else if (HAS_PCH_SPLIT(dev))
> + else if (HAS_PCH_SPLIT(dev_priv))
> ilk_wm_get_hw_state(dev);
>
> for_each_intel_crtc(dev, crtc) {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index edaf35b975c0..0b6f1bab671d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1336,13 +1336,14 @@ intel_dp_set_clock(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> const struct dp_link_dpll *divisor = NULL;
> int i, count = 0;
>
> if (IS_G4X(dev)) {
> divisor = gen4_dpll;
> count = ARRAY_SIZE(gen4_dpll);
> - } else if (HAS_PCH_SPLIT(dev)) {
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> divisor = pch_dpll;
> count = ARRAY_SIZE(pch_dpll);
> } else if (IS_CHERRYVIEW(dev)) {
> @@ -1776,7 +1777,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
> intel_dp->DP |= DP_ENHANCED_FRAMING;
>
> intel_dp->DP |= crtc->pipe << 29;
> - } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
> + } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
> u32 trans_dp;
>
> intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
> @@ -1788,7 +1789,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
> trans_dp &= ~TRANS_DP_ENH_FRAMING;
> I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
> } else {
> - if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
> + if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev) &&
> !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
> intel_dp->DP |= DP_COLOR_RANGE_16_235;
>
> @@ -2442,7 +2443,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
>
> if (IS_GEN7(dev) && port == PORT_A) {
> *pipe = PORT_TO_PIPE_CPT(tmp);
> - } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
> + } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
> enum pipe p;
>
> for_each_pipe(dev_priv, p) {
> @@ -2485,7 +2486,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>
> pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
>
> - if (HAS_PCH_CPT(dev) && port != PORT_A) {
> + if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
> u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
>
> if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
> @@ -2511,8 +2512,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>
> pipe_config->base.adjusted_mode.flags |= flags;
>
> - if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
> - !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
> + if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> + !IS_CHERRYVIEW(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
> pipe_config->limited_color_range = true;
>
> pipe_config->lane_count =
> @@ -2659,7 +2660,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> I915_WRITE(DP_TP_CTL(port), temp);
>
> } else if ((IS_GEN7(dev) && port == PORT_A) ||
> - (HAS_PCH_CPT(dev) && port != PORT_A)) {
> + (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> *DP &= ~DP_LINK_TRAIN_MASK_CPT;
>
> switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> @@ -2989,7 +2990,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (IS_GEN7(dev) && port == PORT_A)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> - else if (HAS_PCH_CPT(dev) && port != PORT_A)
> + else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> @@ -3442,7 +3443,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
> DRM_DEBUG_KMS("\n");
>
> if ((IS_GEN7(dev) && port == PORT_A) ||
> - (HAS_PCH_CPT(dev) && port != PORT_A)) {
> + (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> DP &= ~DP_LINK_TRAIN_MASK_CPT;
> DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
> } else {
> @@ -3464,7 +3465,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
> * to transcoder A after disabling it to allow the
> * matching HDMI port to be enabled on transcoder A.
> */
> - if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
> + if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
> /*
> * We get CPU/PCH FIFO underruns on the other pipe when
> * doing the workaround. Sweep them under the rug.
> @@ -5085,7 +5086,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> * power sequencer any more. */
> if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> port_sel = PANEL_PORT_SELECT_VLV(port);
> - } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
> + } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
> if (port == PORT_A)
> port_sel = PANEL_PORT_SELECT_DPA;
> else
> @@ -5649,7 +5650,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
> else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
> - else if (HAS_PCH_SPLIT(dev))
> + else if (HAS_PCH_SPLIT(dev_priv))
> intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
> else
> intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index d0c59c1793ef..c37ce1263142 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1857,7 +1857,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> dpll_mgr = &bxt_pll_mgr;
> else if (HAS_DDI(dev_priv))
> dpll_mgr = &hsw_pll_mgr;
> - else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> + else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
> dpll_mgr = &pch_pll_mgr;
>
> if (!dpll_mgr) {
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 09b2146f157f..397e10f4b6f0 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -864,7 +864,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
> intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
>
> hdmi_val = SDVO_ENCODING_HDMI;
> - if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
> + if (!HAS_PCH_SPLIT(dev_priv) && crtc->config->limited_color_range)
> hdmi_val |= HDMI_COLOR_RANGE_16_235;
> if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
> @@ -879,7 +879,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
> if (crtc->config->has_hdmi_sink)
> hdmi_val |= HDMI_MODE_SELECT_HDMI;
>
> - if (HAS_PCH_CPT(dev))
> + if (HAS_PCH_CPT(dev_priv))
> hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
> else if (IS_CHERRYVIEW(dev))
> hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
> @@ -911,7 +911,7 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
> if (!(tmp & SDVO_ENABLE))
> goto out;
>
> - if (HAS_PCH_CPT(dev))
> + if (HAS_PCH_CPT(dev_priv))
> *pipe = PORT_TO_PIPE_CPT(tmp);
> else if (IS_CHERRYVIEW(dev))
> *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
> @@ -956,7 +956,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
> if (tmp & SDVO_AUDIO_ENABLE)
> pipe_config->has_audio = true;
>
> - if (!HAS_PCH_SPLIT(dev) &&
> + if (!HAS_PCH_SPLIT(dev_priv) &&
> tmp & HDMI_COLOR_RANGE_16_235)
> pipe_config->limited_color_range = true;
>
> @@ -1141,7 +1141,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder,
> * to transcoder A after disabling it to allow the
> * matching DP port to be enabled on transcoder A.
> */
> - if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
> + if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
> /*
> * We get CPU/PCH FIFO underruns on the other pipe when
> * doing the workaround. Sweep them under the rug.
> @@ -1896,7 +1896,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> intel_hdmi->write_infoframe = hsw_write_infoframe;
> intel_hdmi->set_infoframes = hsw_set_infoframes;
> intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
> - } else if (HAS_PCH_IBX(dev)) {
> + } else if (HAS_PCH_IBX(dev_priv)) {
> intel_hdmi->write_infoframe = ibx_write_infoframe;
> intel_hdmi->set_infoframes = ibx_set_infoframes;
> intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
> @@ -1929,6 +1929,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> void intel_hdmi_init(struct drm_device *dev,
> i915_reg_t hdmi_reg, enum port port)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_digital_port *intel_dig_port;
> struct intel_encoder *intel_encoder;
> struct intel_connector *intel_connector;
> @@ -1949,7 +1950,7 @@ void intel_hdmi_init(struct drm_device *dev,
> DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port));
>
> intel_encoder->compute_config = intel_hdmi_compute_config;
> - if (HAS_PCH_SPLIT(dev)) {
> + if (HAS_PCH_SPLIT(dev_priv)) {
> intel_encoder->disable = pch_disable_hdmi;
> intel_encoder->post_disable = pch_post_disable_hdmi;
> } else {
> @@ -1970,9 +1971,9 @@ void intel_hdmi_init(struct drm_device *dev,
> intel_encoder->post_disable = vlv_hdmi_post_disable;
> } else {
> intel_encoder->pre_enable = intel_hdmi_pre_enable;
> - if (HAS_PCH_CPT(dev))
> + if (HAS_PCH_CPT(dev_priv))
> intel_encoder->enable = cpt_enable_hdmi;
> - else if (HAS_PCH_IBX(dev))
> + else if (HAS_PCH_IBX(dev_priv))
> intel_encoder->enable = ibx_enable_hdmi;
> else
> intel_encoder->enable = g4x_enable_hdmi;
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 79aab9ad6faa..1410330ec9bb 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -633,7 +633,7 @@ int intel_setup_gmbus(struct drm_device *dev)
> unsigned int pin;
> int ret;
>
> - if (HAS_PCH_NOP(dev))
> + if (HAS_PCH_NOP(dev_priv))
> return 0;
>
> if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 2e943bd1c3cf..baaf2ed897ef 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -106,7 +106,7 @@ static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
> if (!(tmp & LVDS_PORT_EN))
> goto out;
>
> - if (HAS_PCH_CPT(dev))
> + if (HAS_PCH_CPT(dev_priv))
> *pipe = PORT_TO_PIPE_CPT(tmp);
> else
> *pipe = PORT_TO_PIPE(tmp);
> @@ -396,7 +396,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
> {
> - struct drm_device *dev = intel_encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
> struct intel_lvds_encoder *lvds_encoder =
> to_lvds_encoder(&intel_encoder->base);
> struct intel_connector *intel_connector =
> @@ -406,7 +406,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
> unsigned int lvds_bpp;
>
> /* Should never happen!! */
> - if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
> + if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
> DRM_ERROR("Can't support LVDS on pipe A\n");
> return false;
> }
> @@ -431,7 +431,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
> intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
> adjusted_mode);
>
> - if (HAS_PCH_SPLIT(dev)) {
> + if (HAS_PCH_SPLIT(dev_priv)) {
> pipe_config->has_pch_encoder = true;
>
> intel_pch_panel_fitting(intel_crtc, pipe_config,
> @@ -566,7 +566,7 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
> * and as part of the cleanup in the hw state restore we also redisable
> * the vga plane.
> */
> - if (!HAS_PCH_SPLIT(dev))
> + if (!HAS_PCH_SPLIT(dev_priv))
> intel_display_resume(dev);
>
> dev_priv->modeset_restore = MODESET_DONE;
> @@ -951,9 +951,11 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
>
> static bool intel_lvds_supported(struct drm_device *dev)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> /* With the introduction of the PCH we gained a dedicated
> * LVDS presence pin, use it. */
> - if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> + if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
> return true;
>
> /* Otherwise LVDS was only attached to mobile products,
> @@ -997,14 +999,14 @@ void intel_lvds_init(struct drm_device *dev)
> if (dmi_check_system(intel_no_lvds))
> return;
>
> - if (HAS_PCH_SPLIT(dev))
> + if (HAS_PCH_SPLIT(dev_priv))
> lvds_reg = PCH_LVDS;
> else
> lvds_reg = LVDS;
>
> lvds = I915_READ(lvds_reg);
>
> - if (HAS_PCH_SPLIT(dev)) {
> + if (HAS_PCH_SPLIT(dev_priv)) {
> if ((lvds & LVDS_DETECTED) == 0)
> return;
> if (dev_priv->vbt.edp.support) {
> @@ -1068,7 +1070,7 @@ void intel_lvds_init(struct drm_device *dev)
> intel_encoder->type = INTEL_OUTPUT_LVDS;
> intel_encoder->port = PORT_NONE;
> intel_encoder->cloneable = 0;
> - if (HAS_PCH_SPLIT(dev))
> + if (HAS_PCH_SPLIT(dev_priv))
> intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
> else if (IS_GEN4(dev))
> intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
> @@ -1158,7 +1160,7 @@ void intel_lvds_init(struct drm_device *dev)
> */
>
> /* Ironlake: FIXME if still fail, not try pipe mode now */
> - if (HAS_PCH_SPLIT(dev))
> + if (HAS_PCH_SPLIT(dev_priv))
> goto failed;
>
> pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e7b3e6f39281..86051ef2716e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7413,7 +7413,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> snpcr |= GEN6_MBC_SNPCR_MED;
> I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
>
> - if (!HAS_PCH_NOP(dev))
> + if (!HAS_PCH_NOP(dev_priv))
> cpt_init_clock_gating(dev);
>
> gen6_check_mch_setup(dev);
> @@ -7656,7 +7656,7 @@ void intel_init_clock_gating(struct drm_device *dev)
>
> void intel_suspend_hw(struct drm_device *dev)
> {
> - if (HAS_PCH_LPT(dev))
> + if (HAS_PCH_LPT(to_i915(dev)))
> lpt_suspend_hw(dev);
> }
>
> @@ -7732,7 +7732,7 @@ void intel_init_pm(struct drm_device *dev)
> skl_setup_wm_latency(dev);
> dev_priv->display.update_wm = skl_update_wm;
> dev_priv->display.compute_global_watermarks = skl_compute_wm;
> - } else if (HAS_PCH_SPLIT(dev)) {
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> ilk_setup_wm_latency(dev);
>
> if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index a061b0029797..0d9114f9ce27 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -251,7 +251,7 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
> * HW workaround, need to write this twice for issue
> * that may result in first write getting masked.
> */
> - if (HAS_PCH_IBX(dev)) {
> + if (HAS_PCH_IBX(dev_priv)) {
> I915_WRITE(intel_sdvo->sdvo_reg, val);
> POSTING_READ(intel_sdvo->sdvo_reg);
> }
> @@ -1133,7 +1133,7 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
> DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
> pipe_config->pipe_bpp = 8*3;
>
> - if (HAS_PCH_SPLIT(encoder->base.dev))
> + if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
> pipe_config->has_pch_encoder = true;
>
> /* We need to construct preferred input timings based on our
> @@ -1273,7 +1273,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
> /* The real mode polarity is set by the SDVO commands, using
> * struct intel_sdvo_dtd. */
> sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
> - if (!HAS_PCH_SPLIT(dev) && crtc_state->limited_color_range)
> + if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
> sdvox |= HDMI_COLOR_RANGE_16_235;
> if (INTEL_INFO(dev)->gen < 5)
> sdvox |= SDVO_BORDER_ENABLE;
> @@ -1286,7 +1286,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
> sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
> }
>
> - if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_CPT)
> sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
> else
> sdvox |= SDVO_PIPE_SEL(crtc->pipe);
> @@ -1339,7 +1339,7 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
> if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
> return false;
>
> - if (HAS_PCH_CPT(dev))
> + if (HAS_PCH_CPT(dev_priv))
> *pipe = PORT_TO_PIPE_CPT(tmp);
> else
> *pipe = PORT_TO_PIPE(tmp);
> @@ -2997,7 +2997,7 @@ bool intel_sdvo_init(struct drm_device *dev,
> }
>
> intel_encoder->compute_config = intel_sdvo_compute_config;
> - if (HAS_PCH_SPLIT(dev)) {
> + if (HAS_PCH_SPLIT(dev_priv)) {
> intel_encoder->disable = pch_disable_sdvo;
> intel_encoder->post_disable = pch_post_disable_sdvo;
> } else {
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 03/19] drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
2016-10-11 13:21 ` [PATCH 01/19] drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv Tvrtko Ursulin
2016-10-11 13:21 ` [PATCH 02/19] drm/i915: Make INTEL_PCH_TYPE & co " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 8:17 ` David Weinehall
2016-10-11 13:21 ` [PATCH 04/19] drm/i915: Make HAS_RUNTIME_PM " Tvrtko Ursulin
` (17 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
More .rodata string saving by avoid __I915__ magic inside WARNs.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_color.c | 6 +++---
drivers/gpu/drm/i915/intel_display.c | 8 ++++----
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_dsi.c | 2 +-
drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
drivers/gpu/drm/i915/intel_hdmi.c | 5 +++--
7 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3caa1c767512..1a4698e665be 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2863,7 +2863,7 @@ struct drm_i915_cmd_table {
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
-#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
+#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 95a72771eea6..5362c07932d3 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -273,7 +273,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
enum pipe pipe = intel_crtc->pipe;
int i;
- if (HAS_GMCH_DISPLAY(dev)) {
+ if (HAS_GMCH_DISPLAY(dev_priv)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
assert_dsi_pll_enabled(dev_priv);
else
@@ -288,7 +288,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
(drm_color_lut_extract(lut[i].green, 8) << 8) |
drm_color_lut_extract(lut[i].blue, 8);
- if (HAS_GMCH_DISPLAY(dev))
+ if (HAS_GMCH_DISPLAY(dev_priv))
I915_WRITE(PALETTE(pipe, i), word);
else
I915_WRITE(LGC_PALETTE(pipe, i), word);
@@ -297,7 +297,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
for (i = 0; i < 256; i++) {
uint32_t word = (i << 16) | (i << 8) | i;
- if (HAS_GMCH_DISPLAY(dev))
+ if (HAS_GMCH_DISPLAY(dev_priv))
I915_WRITE(PALETTE(pipe, i), word);
else
I915_WRITE(LGC_PALETTE(pipe, i), word);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0a69e80821ee..b7685936d324 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5036,7 +5036,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
* event which is after the vblank start event, so we need to have a
* wait-for-vblank between disabling the plane and the pipe.
*/
- if (HAS_GMCH_DISPLAY(dev)) {
+ if (HAS_GMCH_DISPLAY(dev_priv)) {
intel_set_memory_cxsr(dev_priv, false);
dev_priv->wm.vlv.cxsr = false;
intel_wait_for_vblank(dev, pipe);
@@ -5101,7 +5101,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
intel_pre_disable_primary(&crtc->base);
}
- if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
+ if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
crtc->wm.cxsr_allowed = false;
/*
@@ -10895,7 +10895,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
pos |= y << CURSOR_Y_SHIFT;
/* ILK+ do this automagically */
- if (HAS_GMCH_DISPLAY(dev) &&
+ if (HAS_GMCH_DISPLAY(dev_priv) &&
plane_state->base.rotation == DRM_ROTATE_180) {
base += (plane_state->base.crtc_h *
plane_state->base.crtc_w - 1) * 4;
@@ -16593,7 +16593,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
if (crtc->active && !intel_crtc_has_encoders(crtc))
intel_crtc_disable_noatomic(&crtc->base);
- if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
+ if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
/*
* We start out with underrun reporting disabled to avoid races.
* For correct bookkeeping mark this on active crtcs.
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0b6f1bab671d..51d92a9c6cb1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1583,7 +1583,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
return ret;
}
- if (HAS_GMCH_DISPLAY(dev))
+ if (HAS_GMCH_DISPLAY(dev_priv))
intel_gmch_panel_fitting(intel_crtc, pipe_config,
intel_connector->panel.fitting_mode);
else
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 727adaace96c..5b1e445a80d0 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -1346,7 +1346,7 @@ static int intel_dsi_set_property(struct drm_connector *connector,
DRM_DEBUG_KMS("no scaling not supported\n");
return -EINVAL;
}
- if (HAS_GMCH_DISPLAY(dev) &&
+ if (HAS_GMCH_DISPLAY(to_i915(dev)) &&
val == DRM_MODE_SCALE_CENTER) {
DRM_DEBUG_KMS("centering not supported\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index ebb4fed8322e..076893cc3890 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -254,7 +254,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
old = !intel_crtc->cpu_fifo_underrun_disabled;
intel_crtc->cpu_fifo_underrun_disabled = !enable;
- if (HAS_GMCH_DISPLAY(dev))
+ if (HAS_GMCH_DISPLAY(dev_priv))
i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
else if (IS_GEN5(dev) || IS_GEN6(dev))
ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 397e10f4b6f0..ad3ff4fe63cf 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1265,6 +1265,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
{
struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
struct drm_device *dev = intel_hdmi_to_dev(hdmi);
+ struct drm_i915_private *dev_priv = to_i915(dev);
enum drm_mode_status status;
int clock;
int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
@@ -1287,7 +1288,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
status = hdmi_port_clock_valid(hdmi, clock, true);
/* if we can't do 8bpc we may still be able to do 12bpc */
- if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
+ if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK)
status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
return status;
@@ -1297,7 +1298,7 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
{
struct drm_device *dev = crtc_state->base.crtc->dev;
- if (HAS_GMCH_DISPLAY(dev))
+ if (HAS_GMCH_DISPLAY(to_i915(dev)))
return false;
/*
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 03/19] drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv
2016-10-11 13:21 ` [PATCH 03/19] drm/i915: Make HAS_GMCH_DISPLAY " Tvrtko Ursulin
@ 2016-10-12 8:17 ` David Weinehall
2016-10-12 8:43 ` Tvrtko Ursulin
0 siblings, 1 reply; 46+ messages in thread
From: David Weinehall @ 2016-10-12 8:17 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:36PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> More .rodata string saving by avoid __I915__ magic inside WARNs.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Note that once this patch series goes in (or before),
we should have a patch that turns intel_hdmi_to_dev() into
intel_hdmi_to_dev_priv(). If you look at the code in
intel_hdmi.c, almost every (after the dev -> dev_priv transition
I think it's every) instance where it's used converts
dev immediately further to dev_priv.
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_color.c | 6 +++---
> drivers/gpu/drm/i915/intel_display.c | 8 ++++----
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/intel_dsi.c | 2 +-
> drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
> drivers/gpu/drm/i915/intel_hdmi.c | 5 +++--
> 7 files changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3caa1c767512..1a4698e665be 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2863,7 +2863,7 @@ struct drm_i915_cmd_table {
> #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
> #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
>
> -#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
> +#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
>
> /* DPF == dynamic parity feature */
> #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 95a72771eea6..5362c07932d3 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -273,7 +273,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
> enum pipe pipe = intel_crtc->pipe;
> int i;
>
> - if (HAS_GMCH_DISPLAY(dev)) {
> + if (HAS_GMCH_DISPLAY(dev_priv)) {
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> assert_dsi_pll_enabled(dev_priv);
> else
> @@ -288,7 +288,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
> (drm_color_lut_extract(lut[i].green, 8) << 8) |
> drm_color_lut_extract(lut[i].blue, 8);
>
> - if (HAS_GMCH_DISPLAY(dev))
> + if (HAS_GMCH_DISPLAY(dev_priv))
> I915_WRITE(PALETTE(pipe, i), word);
> else
> I915_WRITE(LGC_PALETTE(pipe, i), word);
> @@ -297,7 +297,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
> for (i = 0; i < 256; i++) {
> uint32_t word = (i << 16) | (i << 8) | i;
>
> - if (HAS_GMCH_DISPLAY(dev))
> + if (HAS_GMCH_DISPLAY(dev_priv))
> I915_WRITE(PALETTE(pipe, i), word);
> else
> I915_WRITE(LGC_PALETTE(pipe, i), word);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0a69e80821ee..b7685936d324 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5036,7 +5036,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
> * event which is after the vblank start event, so we need to have a
> * wait-for-vblank between disabling the plane and the pipe.
> */
> - if (HAS_GMCH_DISPLAY(dev)) {
> + if (HAS_GMCH_DISPLAY(dev_priv)) {
> intel_set_memory_cxsr(dev_priv, false);
> dev_priv->wm.vlv.cxsr = false;
> intel_wait_for_vblank(dev, pipe);
> @@ -5101,7 +5101,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
> intel_pre_disable_primary(&crtc->base);
> }
>
> - if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
> + if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
> crtc->wm.cxsr_allowed = false;
>
> /*
> @@ -10895,7 +10895,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
> pos |= y << CURSOR_Y_SHIFT;
>
> /* ILK+ do this automagically */
> - if (HAS_GMCH_DISPLAY(dev) &&
> + if (HAS_GMCH_DISPLAY(dev_priv) &&
> plane_state->base.rotation == DRM_ROTATE_180) {
> base += (plane_state->base.crtc_h *
> plane_state->base.crtc_w - 1) * 4;
> @@ -16593,7 +16593,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
> if (crtc->active && !intel_crtc_has_encoders(crtc))
> intel_crtc_disable_noatomic(&crtc->base);
>
> - if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
> + if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
> /*
> * We start out with underrun reporting disabled to avoid races.
> * For correct bookkeeping mark this on active crtcs.
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 0b6f1bab671d..51d92a9c6cb1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1583,7 +1583,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> return ret;
> }
>
> - if (HAS_GMCH_DISPLAY(dev))
> + if (HAS_GMCH_DISPLAY(dev_priv))
> intel_gmch_panel_fitting(intel_crtc, pipe_config,
> intel_connector->panel.fitting_mode);
> else
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 727adaace96c..5b1e445a80d0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -1346,7 +1346,7 @@ static int intel_dsi_set_property(struct drm_connector *connector,
> DRM_DEBUG_KMS("no scaling not supported\n");
> return -EINVAL;
> }
> - if (HAS_GMCH_DISPLAY(dev) &&
> + if (HAS_GMCH_DISPLAY(to_i915(dev)) &&
> val == DRM_MODE_SCALE_CENTER) {
> DRM_DEBUG_KMS("centering not supported\n");
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> index ebb4fed8322e..076893cc3890 100644
> --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> @@ -254,7 +254,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
> old = !intel_crtc->cpu_fifo_underrun_disabled;
> intel_crtc->cpu_fifo_underrun_disabled = !enable;
>
> - if (HAS_GMCH_DISPLAY(dev))
> + if (HAS_GMCH_DISPLAY(dev_priv))
> i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
> else if (IS_GEN5(dev) || IS_GEN6(dev))
> ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 397e10f4b6f0..ad3ff4fe63cf 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1265,6 +1265,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
> {
> struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
> struct drm_device *dev = intel_hdmi_to_dev(hdmi);
> + struct drm_i915_private *dev_priv = to_i915(dev);
> enum drm_mode_status status;
> int clock;
> int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
> @@ -1287,7 +1288,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
> status = hdmi_port_clock_valid(hdmi, clock, true);
>
> /* if we can't do 8bpc we may still be able to do 12bpc */
> - if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
> + if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK)
> status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
>
> return status;
> @@ -1297,7 +1298,7 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
> {
> struct drm_device *dev = crtc_state->base.crtc->dev;
>
> - if (HAS_GMCH_DISPLAY(dev))
> + if (HAS_GMCH_DISPLAY(to_i915(dev)))
> return false;
>
> /*
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH 03/19] drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv
2016-10-12 8:17 ` David Weinehall
@ 2016-10-12 8:43 ` Tvrtko Ursulin
2016-10-12 10:04 ` David Weinehall
0 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-12 8:43 UTC (permalink / raw)
To: Tvrtko Ursulin, Intel-gfx, David Weinehall
[-- Attachment #1.1: Type: text/plain, Size: 8743 bytes --]
On 12/10/2016 09:17, David Weinehall wrote:
> On Tue, Oct 11, 2016 at 02:21:36PM +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin<tvrtko.ursulin@intel.com>
>>
>> More .rodata string saving by avoid __I915__ magic inside WARNs.
>>
>> v2: Add parantheses around dev_priv. (Ville Syrjala)
>>
>> Signed-off-by: Tvrtko Ursulin<tvrtko.ursulin@intel.com>
> Reviewed-by: David Weinehall<david.weinehall@linux.intel.com>
>
> Note that once this patch series goes in (or before),
> we should have a patch that turns intel_hdmi_to_dev() into
> intel_hdmi_to_dev_priv(). If you look at the code in
> intel_hdmi.c, almost every (after the dev -> dev_priv transition
> I think it's every) instance where it's used converts
> dev immediately further to dev_priv.
Agreed, but best left for later I think. And there is more of those
opportunities throughout the code which I spotted while doing this.
Regards,
Tvrtko
P.S. For some reason reply to all from thunderbird keeps dropping you
from the recipients. I might forget to manually add you.
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 +-
>> drivers/gpu/drm/i915/intel_color.c | 6 +++---
>> drivers/gpu/drm/i915/intel_display.c | 8 ++++----
>> drivers/gpu/drm/i915/intel_dp.c | 2 +-
>> drivers/gpu/drm/i915/intel_dsi.c | 2 +-
>> drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
>> drivers/gpu/drm/i915/intel_hdmi.c | 5 +++--
>> 7 files changed, 14 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 3caa1c767512..1a4698e665be 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2863,7 +2863,7 @@ struct drm_i915_cmd_table {
>> #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
>> #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
>>
>> -#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
>> +#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
>>
>> /* DPF == dynamic parity feature */
>> #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
>> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>> index 95a72771eea6..5362c07932d3 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -273,7 +273,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
>> enum pipe pipe = intel_crtc->pipe;
>> int i;
>>
>> - if (HAS_GMCH_DISPLAY(dev)) {
>> + if (HAS_GMCH_DISPLAY(dev_priv)) {
>> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
>> assert_dsi_pll_enabled(dev_priv);
>> else
>> @@ -288,7 +288,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
>> (drm_color_lut_extract(lut[i].green, 8) << 8) |
>> drm_color_lut_extract(lut[i].blue, 8);
>>
>> - if (HAS_GMCH_DISPLAY(dev))
>> + if (HAS_GMCH_DISPLAY(dev_priv))
>> I915_WRITE(PALETTE(pipe, i), word);
>> else
>> I915_WRITE(LGC_PALETTE(pipe, i), word);
>> @@ -297,7 +297,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
>> for (i = 0; i < 256; i++) {
>> uint32_t word = (i << 16) | (i << 8) | i;
>>
>> - if (HAS_GMCH_DISPLAY(dev))
>> + if (HAS_GMCH_DISPLAY(dev_priv))
>> I915_WRITE(PALETTE(pipe, i), word);
>> else
>> I915_WRITE(LGC_PALETTE(pipe, i), word);
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 0a69e80821ee..b7685936d324 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -5036,7 +5036,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
>> * event which is after the vblank start event, so we need to have a
>> * wait-for-vblank between disabling the plane and the pipe.
>> */
>> - if (HAS_GMCH_DISPLAY(dev)) {
>> + if (HAS_GMCH_DISPLAY(dev_priv)) {
>> intel_set_memory_cxsr(dev_priv, false);
>> dev_priv->wm.vlv.cxsr = false;
>> intel_wait_for_vblank(dev, pipe);
>> @@ -5101,7 +5101,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
>> intel_pre_disable_primary(&crtc->base);
>> }
>>
>> - if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
>> + if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) {
>> crtc->wm.cxsr_allowed = false;
>>
>> /*
>> @@ -10895,7 +10895,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
>> pos |= y << CURSOR_Y_SHIFT;
>>
>> /* ILK+ do this automagically */
>> - if (HAS_GMCH_DISPLAY(dev) &&
>> + if (HAS_GMCH_DISPLAY(dev_priv) &&
>> plane_state->base.rotation == DRM_ROTATE_180) {
>> base += (plane_state->base.crtc_h *
>> plane_state->base.crtc_w - 1) * 4;
>> @@ -16593,7 +16593,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
>> if (crtc->active && !intel_crtc_has_encoders(crtc))
>> intel_crtc_disable_noatomic(&crtc->base);
>>
>> - if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
>> + if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
>> /*
>> * We start out with underrun reporting disabled to avoid races.
>> * For correct bookkeeping mark this on active crtcs.
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 0b6f1bab671d..51d92a9c6cb1 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -1583,7 +1583,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>> return ret;
>> }
>>
>> - if (HAS_GMCH_DISPLAY(dev))
>> + if (HAS_GMCH_DISPLAY(dev_priv))
>> intel_gmch_panel_fitting(intel_crtc, pipe_config,
>> intel_connector->panel.fitting_mode);
>> else
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index 727adaace96c..5b1e445a80d0 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -1346,7 +1346,7 @@ static int intel_dsi_set_property(struct drm_connector *connector,
>> DRM_DEBUG_KMS("no scaling not supported\n");
>> return -EINVAL;
>> }
>> - if (HAS_GMCH_DISPLAY(dev) &&
>> + if (HAS_GMCH_DISPLAY(to_i915(dev)) &&
>> val == DRM_MODE_SCALE_CENTER) {
>> DRM_DEBUG_KMS("centering not supported\n");
>> return -EINVAL;
>> diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
>> index ebb4fed8322e..076893cc3890 100644
>> --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
>> +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
>> @@ -254,7 +254,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
>> old = !intel_crtc->cpu_fifo_underrun_disabled;
>> intel_crtc->cpu_fifo_underrun_disabled = !enable;
>>
>> - if (HAS_GMCH_DISPLAY(dev))
>> + if (HAS_GMCH_DISPLAY(dev_priv))
>> i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
>> else if (IS_GEN5(dev) || IS_GEN6(dev))
>> ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
>> index 397e10f4b6f0..ad3ff4fe63cf 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -1265,6 +1265,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
>> {
>> struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
>> struct drm_device *dev = intel_hdmi_to_dev(hdmi);
>> + struct drm_i915_private *dev_priv = to_i915(dev);
>> enum drm_mode_status status;
>> int clock;
>> int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
>> @@ -1287,7 +1288,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector,
>> status = hdmi_port_clock_valid(hdmi, clock, true);
>>
>> /* if we can't do 8bpc we may still be able to do 12bpc */
>> - if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
>> + if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK)
>> status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
>>
>> return status;
>> @@ -1297,7 +1298,7 @@ static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
>> {
>> struct drm_device *dev = crtc_state->base.crtc->dev;
>>
>> - if (HAS_GMCH_DISPLAY(dev))
>> + if (HAS_GMCH_DISPLAY(to_i915(dev)))
>> return false;
>>
>> /*
>> --
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[-- Attachment #1.2: Type: text/html, Size: 9665 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH 03/19] drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv
2016-10-12 8:43 ` Tvrtko Ursulin
@ 2016-10-12 10:04 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 10:04 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Wed, Oct 12, 2016 at 09:43:02AM +0100, Tvrtko Ursulin wrote:
>
> On 12/10/2016 09:17, David Weinehall wrote:
> > On Tue, Oct 11, 2016 at 02:21:36PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin<tvrtko.ursulin@intel.com>
> > >
> > > More .rodata string saving by avoid __I915__ magic inside WARNs.
> > >
> > > v2: Add parantheses around dev_priv. (Ville Syrjala)
> > >
> > > Signed-off-by: Tvrtko Ursulin<tvrtko.ursulin@intel.com>
> > Reviewed-by: David Weinehall<david.weinehall@linux.intel.com>
> >
> > Note that once this patch series goes in (or before),
> > we should have a patch that turns intel_hdmi_to_dev() into
> > intel_hdmi_to_dev_priv(). If you look at the code in
> > intel_hdmi.c, almost every (after the dev -> dev_priv transition
> > I think it's every) instance where it's used converts
> > dev immediately further to dev_priv.
>
> Agreed, but best left for later I think. And there is more of those
> opportunities throughout the code which I spotted while doing this.
>
> Regards,
>
> Tvrtko
>
> P.S. For some reason reply to all from thunderbird keeps dropping you from
> the recipients. I might forget to manually add you.
That's because my e-mail client sets the Mail-Followup-To header;
I'm subscribed to the list -- I don't need duplicate copies addressed
directly to me.
Regards, David
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 04/19] drm/i915: Make HAS_RUNTIME_PM only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (2 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 03/19] drm/i915: Make HAS_GMCH_DISPLAY " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 8:11 ` David Weinehall
2016-10-11 13:21 ` [PATCH 05/19] drm/i915: Do not use INTEL_INFO(dev_priv)->ring_mask inside WARNs Tvrtko Ursulin
` (16 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 960 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 89d322215c84..fbb4e2e0d124 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2308,7 +2308,7 @@ static int intel_runtime_suspend(struct device *kdev)
if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
return -ENODEV;
- if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+ if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
return -ENODEV;
DRM_DEBUG_KMS("Suspending device\n");
@@ -2412,7 +2412,7 @@ static int intel_runtime_resume(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret = 0;
- if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
+ if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
return -ENODEV;
DRM_DEBUG_KMS("Resuming device\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1a4698e665be..aac9375cccb3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2818,12 +2818,12 @@ struct drm_i915_cmd_table {
#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
#define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
-#define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm)
#define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
#define HAS_RC6p(dev) (INTEL_INFO(dev)->has_rc6p)
#define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr)
+#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
/*
* For now, anything with a GuC requires uCode loading, and then supports
* command submission once loaded. But these are logically independent
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c11168facd6..ed1faf14f777 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2758,7 +2758,6 @@ void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
- struct drm_device *dev = &dev_priv->drm;
struct device *kdev = &pdev->dev;
pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */
@@ -2770,7 +2769,7 @@ void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
* so the driver's own RPM reference tracking asserts also work on
* platforms without RPM support.
*/
- if (!HAS_RUNTIME_PM(dev)) {
+ if (!HAS_RUNTIME_PM(dev_priv)) {
pm_runtime_dont_use_autosuspend(kdev);
pm_runtime_get_sync(kdev);
} else {
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 04/19] drm/i915: Make HAS_RUNTIME_PM only take dev_priv
2016-10-11 13:21 ` [PATCH 04/19] drm/i915: Make HAS_RUNTIME_PM " Tvrtko Ursulin
@ 2016-10-12 8:11 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 8:11 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:37PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 960 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
> 3 files changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 89d322215c84..fbb4e2e0d124 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2308,7 +2308,7 @@ static int intel_runtime_suspend(struct device *kdev)
> if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
> return -ENODEV;
>
> - if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
> + if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
> return -ENODEV;
>
> DRM_DEBUG_KMS("Suspending device\n");
> @@ -2412,7 +2412,7 @@ static int intel_runtime_resume(struct device *kdev)
> struct drm_i915_private *dev_priv = to_i915(dev);
> int ret = 0;
>
> - if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
> + if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
> return -ENODEV;
>
> DRM_DEBUG_KMS("Resuming device\n");
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1a4698e665be..aac9375cccb3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2818,12 +2818,12 @@ struct drm_i915_cmd_table {
> #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
> #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
> #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
> -#define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm)
> #define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
> #define HAS_RC6p(dev) (INTEL_INFO(dev)->has_rc6p)
>
> #define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr)
>
> +#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
> /*
> * For now, anything with a GuC requires uCode loading, and then supports
> * command submission once loaded. But these are logically independent
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6c11168facd6..ed1faf14f777 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2758,7 +2758,6 @@ void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
> void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> - struct drm_device *dev = &dev_priv->drm;
> struct device *kdev = &pdev->dev;
>
> pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */
> @@ -2770,7 +2769,7 @@ void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
> * so the driver's own RPM reference tracking asserts also work on
> * platforms without RPM support.
> */
> - if (!HAS_RUNTIME_PM(dev)) {
> + if (!HAS_RUNTIME_PM(dev_priv)) {
> pm_runtime_dont_use_autosuspend(kdev);
> pm_runtime_get_sync(kdev);
> } else {
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 05/19] drm/i915: Do not use INTEL_INFO(dev_priv)->ring_mask inside WARNs
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (3 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 04/19] drm/i915: Make HAS_RUNTIME_PM " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-11 13:21 ` [PATCH 06/19] drm/i915: Make IS_GEN-range macro only take dev_priv Tvrtko Ursulin
` (15 subsequent siblings)
20 siblings, 0 replies; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 1520 bytes of .rodata strings.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 480584c09306..03e11348eb32 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -110,13 +110,14 @@ int intel_engines_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
+ unsigned int ring_mask = INTEL_INFO(dev_priv)->ring_mask;
unsigned int mask = 0;
int (*init)(struct intel_engine_cs *engine);
unsigned int i;
int ret;
- WARN_ON(INTEL_INFO(dev_priv)->ring_mask == 0);
- WARN_ON(INTEL_INFO(dev_priv)->ring_mask &
+ WARN_ON(ring_mask == 0);
+ WARN_ON(ring_mask &
GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
@@ -143,7 +144,7 @@ int intel_engines_init(struct drm_device *dev)
* are added to the driver by a warning and disabling the forgotten
* engines.
*/
- if (WARN_ON(mask != INTEL_INFO(dev_priv)->ring_mask))
+ if (WARN_ON(mask != ring_mask))
device_info->ring_mask = mask;
device_info->num_rings = hweight32(mask);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH 06/19] drm/i915: Make IS_GEN-range macro only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (4 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 05/19] drm/i915: Do not use INTEL_INFO(dev_priv)->ring_mask inside WARNs Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 12:03 ` David Weinehall
2016-10-11 13:21 ` [PATCH 07/19] drm/i915: Make INTEL_DEVID " Tvrtko Ursulin
` (14 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 944 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index aac9375cccb3..58045cd7a087 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2616,7 +2616,7 @@ struct drm_i915_cmd_table {
*
* Use GEN_FOREVER for unbound start and or end.
*/
-#define IS_GEN(p, s, e) ({ \
+#define IS_GEN(dev_priv, s, e) ({ \
unsigned int __s = (s), __e = (e); \
BUILD_BUG_ON(!__builtin_constant_p(s)); \
BUILD_BUG_ON(!__builtin_constant_p(e)); \
@@ -2626,7 +2626,7 @@ struct drm_i915_cmd_table {
__e = BITS_PER_LONG - 1; \
else \
__e = (e) - 1; \
- !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
+ !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
})
/*
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 06/19] drm/i915: Make IS_GEN-range macro only take dev_priv
2016-10-11 13:21 ` [PATCH 06/19] drm/i915: Make IS_GEN-range macro only take dev_priv Tvrtko Ursulin
@ 2016-10-12 12:03 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 12:03 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:39PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 944 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index aac9375cccb3..58045cd7a087 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2616,7 +2616,7 @@ struct drm_i915_cmd_table {
> *
> * Use GEN_FOREVER for unbound start and or end.
> */
> -#define IS_GEN(p, s, e) ({ \
> +#define IS_GEN(dev_priv, s, e) ({ \
> unsigned int __s = (s), __e = (e); \
> BUILD_BUG_ON(!__builtin_constant_p(s)); \
> BUILD_BUG_ON(!__builtin_constant_p(e)); \
> @@ -2626,7 +2626,7 @@ struct drm_i915_cmd_table {
> __e = BITS_PER_LONG - 1; \
> else \
> __e = (e) - 1; \
> - !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
> + !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
> })
>
> /*
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 07/19] drm/i915: Make INTEL_DEVID only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (5 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 06/19] drm/i915: Make IS_GEN-range macro only take dev_priv Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 10:43 ` David Weinehall
2016-10-11 13:21 ` [PATCH 08/19] drm/i915: Make IS_IVYBRIDGE " Tvrtko Ursulin
` (13 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 4472 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 14 +++--
drivers/gpu/drm/i915/i915_drv.h | 111 +++++++++++++++++----------------
drivers/gpu/drm/i915/i915_gem.c | 36 +++++------
drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +-
drivers/gpu/drm/i915/i915_gem_tiling.c | 3 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_crt.c | 4 +-
drivers/gpu/drm/i915/intel_display.c | 58 +++++++++--------
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/intel_i2c.c | 5 +-
drivers/gpu/drm/i915/intel_lvds.c | 9 ++-
drivers/gpu/drm/i915/intel_pm.c | 26 ++++----
drivers/gpu/drm/i915/intel_sdvo.c | 11 ++--
drivers/gpu/drm/i915/intel_tv.c | 4 +-
15 files changed, 151 insertions(+), 142 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fbb4e2e0d124..bfdbbb745939 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -188,12 +188,14 @@ static void intel_detect_pch(struct drm_device *dev)
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
- WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
+ WARN_ON(IS_HSW_ULT(dev_priv) ||
+ IS_BDW_ULT(dev_priv));
} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
- WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
+ WARN_ON(!IS_HSW_ULT(dev_priv) &&
+ !IS_BDW_ULT(dev_priv));
} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
@@ -422,7 +424,7 @@ intel_setup_mchbar(struct drm_device *dev)
dev_priv->mchbar_need_disable = false;
- if (IS_I915G(dev) || IS_I915GM(dev)) {
+ if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
enabled = !!(temp & DEVEN_MCHBAR_EN);
} else {
@@ -440,7 +442,7 @@ intel_setup_mchbar(struct drm_device *dev)
dev_priv->mchbar_need_disable = true;
/* Space is allocated or reserved, so enable it. */
- if (IS_I915G(dev) || IS_I915GM(dev)) {
+ if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
temp | DEVEN_MCHBAR_EN);
} else {
@@ -456,7 +458,7 @@ intel_teardown_mchbar(struct drm_device *dev)
int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
if (dev_priv->mchbar_need_disable) {
- if (IS_I915G(dev) || IS_I915GM(dev)) {
+ if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
u32 deven_val;
pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
@@ -1077,7 +1079,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
* be lost or delayed, but we use them anyways to avoid
* stuck interrupts on some machines.
*/
- if (!IS_I945G(dev) && !IS_I945GM(dev)) {
+ if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
if (pci_enable_msi(pdev) < 0)
DRM_DEBUG_DRIVER("can't enable MSI");
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 58045cd7a087..7a40dfa830e7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2605,7 +2605,8 @@ struct drm_i915_cmd_table {
})
#define INTEL_INFO(p) (&__I915__(p)->info)
#define INTEL_GEN(p) (INTEL_INFO(p)->gen)
-#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
+
+#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
#define REVID_FOREVER 0xff
#define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
@@ -2637,27 +2638,27 @@ struct drm_i915_cmd_table {
#define IS_REVID(p, since, until) \
(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
-#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
-#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
+#define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577)
+#define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
-#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
+#define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572)
#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
-#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
-#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
+#define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592)
+#define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772)
#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
-#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
+#define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
-#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
-#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
+#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
+#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
-#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
+#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
-#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
- INTEL_DEVID(dev) == 0x0152 || \
- INTEL_DEVID(dev) == 0x015a)
+#define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
+ INTEL_DEVID(dev_priv) == 0x0152 || \
+ INTEL_DEVID(dev_priv) == 0x015a)
#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
@@ -2666,44 +2667,44 @@ struct drm_i915_cmd_table {
#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
-#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
- (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
-#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
- ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
- (INTEL_DEVID(dev) & 0xf) == 0xb || \
- (INTEL_DEVID(dev) & 0xf) == 0xe))
+#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
+ (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
+#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
+ ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
+ (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
+ (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
/* ULX machines are also considered ULT. */
-#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
- (INTEL_DEVID(dev) & 0xf) == 0xe)
-#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
- (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
-#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
- (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
-#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
- (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
+#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
+ (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
+#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
+ (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
+ (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
+#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
+ (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
/* ULX machines are also considered ULT. */
-#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
- INTEL_DEVID(dev) == 0x0A1E)
-#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
- INTEL_DEVID(dev) == 0x1913 || \
- INTEL_DEVID(dev) == 0x1916 || \
- INTEL_DEVID(dev) == 0x1921 || \
- INTEL_DEVID(dev) == 0x1926)
-#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
- INTEL_DEVID(dev) == 0x1915 || \
- INTEL_DEVID(dev) == 0x191E)
-#define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
- INTEL_DEVID(dev) == 0x5913 || \
- INTEL_DEVID(dev) == 0x5916 || \
- INTEL_DEVID(dev) == 0x5921 || \
- INTEL_DEVID(dev) == 0x5926)
-#define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
- INTEL_DEVID(dev) == 0x5915 || \
- INTEL_DEVID(dev) == 0x591E)
-#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
- (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
-#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
- (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
+#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
+ INTEL_DEVID(dev_priv) == 0x0A1E)
+#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
+ INTEL_DEVID(dev_priv) == 0x1913 || \
+ INTEL_DEVID(dev_priv) == 0x1916 || \
+ INTEL_DEVID(dev_priv) == 0x1921 || \
+ INTEL_DEVID(dev_priv) == 0x1926)
+#define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
+ INTEL_DEVID(dev_priv) == 0x1915 || \
+ INTEL_DEVID(dev_priv) == 0x191E)
+#define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
+ INTEL_DEVID(dev_priv) == 0x5913 || \
+ INTEL_DEVID(dev_priv) == 0x5916 || \
+ INTEL_DEVID(dev_priv) == 0x5921 || \
+ INTEL_DEVID(dev_priv) == 0x5926)
+#define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
+ INTEL_DEVID(dev_priv) == 0x5915 || \
+ INTEL_DEVID(dev_priv) == 0x591E)
+#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
+ (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
+#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
+ (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
@@ -2782,7 +2783,7 @@ struct drm_i915_cmd_table {
#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
-#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
+#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv))
/* WaRsDisableCoarsePowerGating:skl,bxt */
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
@@ -2802,8 +2803,9 @@ struct drm_i915_cmd_table {
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
*/
-#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
- IS_I915GM(dev)))
+#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
+ !(IS_I915G(dev_priv) || \
+ IS_I915GM(dev_priv)))
#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
@@ -2811,7 +2813,7 @@ struct drm_i915_cmd_table {
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
-#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
+#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
#define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst)
@@ -2867,7 +2869,8 @@ struct drm_i915_cmd_table {
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
-#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
+#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
+ 2 : HAS_L3_DPF(dev_priv))
#define GT_FREQUENCY_MULTIPLIER 50
#define GEN9_FREQ_SCALER 3
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6b099f0198cc..afaa49946042 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4321,30 +4321,28 @@ void i915_gem_init_swizzling(struct drm_device *dev)
BUG();
}
-static void init_unused_ring(struct drm_device *dev, u32 base)
+static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
I915_WRITE(RING_CTL(base), 0);
I915_WRITE(RING_HEAD(base), 0);
I915_WRITE(RING_TAIL(base), 0);
I915_WRITE(RING_START(base), 0);
}
-static void init_unused_rings(struct drm_device *dev)
-{
- if (IS_I830(dev)) {
- init_unused_ring(dev, PRB1_BASE);
- init_unused_ring(dev, SRB0_BASE);
- init_unused_ring(dev, SRB1_BASE);
- init_unused_ring(dev, SRB2_BASE);
- init_unused_ring(dev, SRB3_BASE);
- } else if (IS_GEN2(dev)) {
- init_unused_ring(dev, SRB0_BASE);
- init_unused_ring(dev, SRB1_BASE);
- } else if (IS_GEN3(dev)) {
- init_unused_ring(dev, PRB1_BASE);
- init_unused_ring(dev, PRB2_BASE);
+static void init_unused_rings(struct drm_i915_private *dev_priv)
+{
+ if (IS_I830(dev_priv)) {
+ init_unused_ring(dev_priv, PRB1_BASE);
+ init_unused_ring(dev_priv, SRB0_BASE);
+ init_unused_ring(dev_priv, SRB1_BASE);
+ init_unused_ring(dev_priv, SRB2_BASE);
+ init_unused_ring(dev_priv, SRB3_BASE);
+ } else if (IS_GEN2(dev_priv)) {
+ init_unused_ring(dev_priv, SRB0_BASE);
+ init_unused_ring(dev_priv, SRB1_BASE);
+ } else if (IS_GEN3(dev_priv)) {
+ init_unused_ring(dev_priv, PRB1_BASE);
+ init_unused_ring(dev_priv, PRB2_BASE);
}
}
@@ -4362,7 +4360,7 @@ i915_gem_init_hw(struct drm_device *dev)
I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
if (IS_HASWELL(dev))
- I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
+ I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
if (HAS_PCH_NOP(dev_priv)) {
@@ -4385,7 +4383,7 @@ i915_gem_init_hw(struct drm_device *dev)
* will prevent c3 entry. Makes sure all unused rings
* are totally idle.
*/
- init_unused_rings(dev);
+ init_unused_rings(dev_priv);
BUG_ON(!dev_priv->kernel_context);
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 59989e8ee5dc..cbea6fb83ce5 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -115,7 +115,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
pci_read_config_dword(pdev, INTEL_BSM, &bsm);
base = bsm & INTEL_BSM_MASK;
- } else if (IS_I865G(dev)) {
+ } else if (IS_I865G(dev_priv)) {
u32 tseg_size = 0;
u16 toud = 0;
u8 tmp;
@@ -154,7 +154,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
tom = tmp * MB(32);
base = tom - tseg_size - ggtt->stolen_size;
- } else if (IS_845G(dev)) {
+ } else if (IS_845G(dev_priv)) {
u32 tseg_size = 0;
u32 tom;
u8 tmp;
@@ -178,7 +178,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
tom = tmp * MB(32);
base = tom - tseg_size - ggtt->stolen_size;
- } else if (IS_I830(dev)) {
+ } else if (IS_I830(dev_priv)) {
u32 tseg_size = 0;
u32 tom;
u8 tmp;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index a14b1e3d4c78..89d1d234a1b4 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -62,6 +62,7 @@
static bool
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
int tile_width;
/* Linear is always fine */
@@ -72,7 +73,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
return false;
if (IS_GEN2(dev) ||
- (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
+ (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
tile_width = 128;
else
tile_width = 512;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 883474411aee..5fb3b1c9a52c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3656,7 +3656,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
ibx_irq_postinstall(dev);
- if (IS_IRONLAKE_M(dev)) {
+ if (IS_IRONLAKE_M(dev_priv)) {
/* Enable PCU event interrupts
*
* spinlocking not required here for correctness since interrupt
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index f8919ef3a7af..d4388c03b4da 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -431,7 +431,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
* to get a reliable result.
*/
- if (IS_G4X(dev) && !IS_GM45(dev))
+ if (IS_G4X(dev_priv) && !IS_GM45(dev_priv))
tries = 2;
else
tries = 1;
@@ -894,7 +894,7 @@ void intel_crt_init(struct drm_device *dev)
crt->base.type = INTEL_OUTPUT_ANALOG;
crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
- if (IS_I830(dev))
+ if (IS_I830(dev_priv))
crt->base.crtc_mask = (1 << 0);
else
crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b7685936d324..ee3b593d3ec2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1230,10 +1230,9 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
static void assert_cursor(struct drm_i915_private *dev_priv,
enum pipe pipe, bool state)
{
- struct drm_device *dev = &dev_priv->drm;
bool cur_state;
- if (IS_845G(dev) || IS_I865G(dev))
+ if (IS_845G(dev_priv) || IS_I865G(dev_priv))
cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
else
cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
@@ -1617,11 +1616,11 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
assert_pipe_disabled(dev_priv, crtc->pipe);
/* PLL is protected by panel, make sure we can write it */
- if (IS_MOBILE(dev) && !IS_I830(dev))
+ if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
assert_panel_unlocked(dev_priv, crtc->pipe);
/* Enable DVO 2x clock on both PLLs if necessary */
- if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
+ if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev) > 0) {
/*
* It appears to be important that we don't enable this
* for the current pipe before otherwise configuring the
@@ -1686,7 +1685,7 @@ static void i9xx_disable_pll(struct intel_crtc *crtc)
enum pipe pipe = crtc->pipe;
/* Disable DVO 2x clock on both PLLs if necessary */
- if (IS_I830(dev) &&
+ if (IS_I830(dev_priv) &&
intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
!intel_num_dvo_pipes(dev)) {
I915_WRITE(DPLL(PIPE_B),
@@ -5392,7 +5391,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
/* IPS only exists on ULT machines and is tied to pipe A. */
static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
{
- return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
+ return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
}
static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
@@ -5864,9 +5863,9 @@ static void intel_update_max_cdclk(struct drm_device *dev)
*/
if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
dev_priv->max_cdclk_freq = 450000;
- else if (IS_BDW_ULX(dev))
+ else if (IS_BDW_ULX(dev_priv))
dev_priv->max_cdclk_freq = 450000;
- else if (IS_BDW_ULT(dev))
+ else if (IS_BDW_ULT(dev_priv))
dev_priv->max_cdclk_freq = 540000;
else
dev_priv->max_cdclk_freq = 675000;
@@ -7225,7 +7224,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
return -EINVAL;
- if (HAS_IPS(dev))
+ if (HAS_IPS(dev_priv))
hsw_compute_ips_config(crtc, pipe_config);
if (pipe_config->has_pch_encoder)
@@ -7363,7 +7362,7 @@ static int haswell_get_display_clock_speed(struct drm_device *dev)
return 450000;
else if (freq == LCPLL_CLK_FREQ_450)
return 450000;
- else if (IS_HSW_ULT(dev))
+ else if (IS_HSW_ULT(dev_priv))
return 337500;
else
return 540000;
@@ -7533,7 +7532,7 @@ static unsigned int intel_hpll_vco(struct drm_device *dev)
uint8_t tmp = 0;
/* FIXME other chipsets? */
- if (IS_GM45(dev))
+ if (IS_GM45(dev_priv))
vco_table = ctg_vco;
else if (IS_G4X(dev))
vco_table = elk_vco;
@@ -8152,7 +8151,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
else
dpll |= DPLLB_MODE_DAC_SERIAL;
- if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
+ if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) {
dpll |= (crtc_state->pixel_multiplier - 1)
<< SDVO_MULTIPLIER_SHIFT_HIRES;
}
@@ -8231,7 +8230,8 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
dpll |= PLL_P2_DIVIDE_BY_4;
}
- if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
+ if (!IS_I830(dev_priv) &&
+ intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
dpll |= DPLL_DVO_2X_MODE;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
@@ -8654,7 +8654,8 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(dev);
uint32_t tmp;
- if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
+ if (INTEL_GEN(dev_priv) <= 3 &&
+ (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
return;
tmp = I915_READ(PFIT_CONTROL);
@@ -8864,7 +8865,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
>> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
pipe_config->dpll_hw_state.dpll_md = tmp;
- } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
+ } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
+ IS_G33(dev_priv)) {
tmp = I915_READ(DPLL(crtc->pipe));
pipe_config->pixel_multiplier =
((tmp & SDVO_MULTIPLIER_MASK)
@@ -8882,7 +8884,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
* on 830. Filter it out here so that we don't
* report errors due to that.
*/
- if (IS_I830(dev))
+ if (IS_I830(dev_priv))
pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
@@ -10904,13 +10906,13 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
I915_WRITE(CURPOS(pipe), pos);
- if (IS_845G(dev) || IS_I865G(dev))
+ if (IS_845G(dev_priv) || IS_I865G(dev_priv))
i845_update_cursor(crtc, base, plane_state);
else
i9xx_update_cursor(crtc, base, plane_state);
}
-static bool cursor_size_ok(struct drm_device *dev,
+static bool cursor_size_ok(struct drm_i915_private *dev_priv,
uint32_t width, uint32_t height)
{
if (width == 0 || height == 0)
@@ -10922,11 +10924,11 @@ static bool cursor_size_ok(struct drm_device *dev,
* the precision of the register. Everything else requires
* square cursors, limited to a few power-of-two sizes.
*/
- if (IS_845G(dev) || IS_I865G(dev)) {
+ if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
if ((width & 63) != 0)
return false;
- if (width > (IS_845G(dev) ? 64 : 512))
+ if (width > (IS_845G(dev_priv) ? 64 : 512))
return false;
if (height > 1023)
@@ -10935,7 +10937,7 @@ static bool cursor_size_ok(struct drm_device *dev,
switch (width | height) {
case 256:
case 128:
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
return false;
case 64:
break;
@@ -11377,7 +11379,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
else
port_clock = i9xx_calc_dpll_params(refclk, &clock);
} else {
- u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
+ u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
if (is_lvds) {
@@ -14658,6 +14660,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
struct drm_plane_state *new_state)
{
struct drm_device *dev = plane->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_framebuffer *fb = new_state->fb;
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
@@ -14709,7 +14712,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
if (plane->type == DRM_PLANE_TYPE_CURSOR &&
INTEL_INFO(dev)->cursor_needs_physical) {
- int align = IS_I830(dev) ? 16 * 1024 : 256;
+ int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
ret = i915_gem_object_attach_phys(obj, align);
if (ret)
DRM_DEBUG_KMS("failed to attach phys object\n");
@@ -15031,7 +15034,8 @@ intel_check_cursor_plane(struct drm_plane *plane,
return 0;
/* Check for which cursor types we support */
- if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
+ if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
+ state->base.crtc_h)) {
DRM_DEBUG("Cursor dimension %dx%d not supported\n",
state->base.crtc_w, state->base.crtc_h);
return -EINVAL;
@@ -15325,7 +15329,7 @@ static bool intel_crt_present(struct drm_device *dev)
if (INTEL_INFO(dev)->gen >= 9)
return false;
- if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
+ if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
return false;
if (IS_CHERRYVIEW(dev))
@@ -16384,8 +16388,8 @@ void intel_modeset_init(struct drm_device *dev)
dev->mode_config.max_height = 8192;
}
- if (IS_845G(dev) || IS_I865G(dev)) {
- dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
+ if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
+ dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
dev->mode_config.cursor_height = 1023;
} else if (IS_GEN2(dev)) {
dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 51d92a9c6cb1..2e06dfb64bd4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5748,7 +5748,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
* 0xd. Failure to do so will result in spurious interrupts being
* generated on the port when a cable is not attached.
*/
- if (IS_G4X(dev) && !IS_GM45(dev)) {
+ if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index ad3ff4fe63cf..6607c4e3c36c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1921,7 +1921,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
* 0xd. Failure to do so will result in spurious interrupts being
* generated on the port when a cable is not attached.
*/
- if (IS_G4X(dev) && !IS_GM45(dev)) {
+ if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
}
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 1410330ec9bb..afb2652919d0 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -138,11 +138,10 @@ static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
static u32 get_reserved(struct intel_gmbus *bus)
{
struct drm_i915_private *dev_priv = bus->dev_priv;
- struct drm_device *dev = &dev_priv->drm;
u32 reserved = 0;
/* On most chips, these bits must be preserved in software. */
- if (!IS_I830(dev) && !IS_845G(dev))
+ if (!IS_I830(dev_priv) && !IS_845G(dev_priv))
reserved = I915_READ_NOTRACE(bus->gpio_reg) &
(GPIO_DATA_PULLUP_DISABLE |
GPIO_CLOCK_PULLUP_DISABLE);
@@ -674,7 +673,7 @@ int intel_setup_gmbus(struct drm_device *dev)
bus->reg0 = pin | GMBUS_RATE_100KHZ;
/* gmbus seems to be broken on i830 */
- if (IS_I830(dev))
+ if (IS_I830(dev_priv))
bus->force_bit = 1;
intel_gpio_setup(bus, pin);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index baaf2ed897ef..1c47f99917e6 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -949,10 +949,8 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
}
-static bool intel_lvds_supported(struct drm_device *dev)
+static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
/* With the introduction of the PCH we gained a dedicated
* LVDS presence pin, use it. */
if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
@@ -960,7 +958,8 @@ static bool intel_lvds_supported(struct drm_device *dev)
/* Otherwise LVDS was only attached to mobile products,
* except for the inglorious 830gm */
- if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
+ if (INTEL_GEN(dev_priv) <= 4 &&
+ IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
return true;
return false;
@@ -992,7 +991,7 @@ void intel_lvds_init(struct drm_device *dev)
int pipe;
u8 pin;
- if (!intel_lvds_supported(dev))
+ if (!intel_lvds_supported(dev_priv))
return;
/* Skip init on machines we know falsely report LVDS */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 86051ef2716e..04a38a37af2e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -334,12 +334,12 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
I915_WRITE(DSPFW3, val);
POSTING_READ(DSPFW3);
- } else if (IS_I945G(dev) || IS_I945GM(dev)) {
+ } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
_MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
I915_WRITE(FW_BLC_SELF, val);
POSTING_READ(FW_BLC_SELF);
- } else if (IS_I915GM(dev)) {
+ } else if (IS_I915GM(dev_priv)) {
/*
* FIXME can't find a bit like this for 915G, and
* and yet it does have the related watermark in
@@ -648,8 +648,10 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
u32 reg;
unsigned long wm;
- latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
- dev_priv->fsb_freq, dev_priv->mem_freq);
+ latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
+ dev_priv->is_ddr3,
+ dev_priv->fsb_freq,
+ dev_priv->mem_freq);
if (!latency) {
DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
intel_set_memory_cxsr(dev_priv, false);
@@ -1579,7 +1581,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
- if (IS_I915GM(dev) && enabled) {
+ if (IS_I915GM(dev_priv) && enabled) {
struct drm_i915_gem_object *obj;
obj = intel_fb_obj(enabled->primary->state->fb);
@@ -1609,7 +1611,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
unsigned long line_time_us;
int entries;
- if (IS_I915GM(dev) || IS_I945GM(dev))
+ if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
cpp = 4;
line_time_us = max(htotal * 1000 / clock, 1);
@@ -1623,7 +1625,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
if (srwm < 0)
srwm = 1;
- if (IS_I945G(dev) || IS_I945GM(dev))
+ if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
I915_WRITE(FW_BLC_SELF,
FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
else
@@ -6930,7 +6932,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
* The bit 22 of 0x42004
* The bit 7,8,9 of 0x42020.
*/
- if (IS_IRONLAKE_M(dev)) {
+ if (IS_IRONLAKE_M(dev_priv)) {
/* WaFbcAsynchFlipDisableFbcQueue:ilk */
I915_WRITE(ILK_DISPLAY_CHICKEN1,
I915_READ(ILK_DISPLAY_CHICKEN1) |
@@ -7340,7 +7342,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
CHICKEN3_DGMG_DONE_FIX_DISABLE);
/* WaDisablePSDDualDispatchEnable:ivb */
- if (IS_IVB_GT1(dev))
+ if (IS_IVB_GT1(dev_priv))
I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
@@ -7356,7 +7358,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
GEN7_WA_FOR_GEN7_L3_CONTROL);
I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
GEN7_WA_L3_CHICKEN_MODE);
- if (IS_IVB_GT1(dev))
+ if (IS_IVB_GT1(dev_priv))
I915_WRITE(GEN7_ROW_CHICKEN2,
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
else {
@@ -7550,7 +7552,7 @@ static void g4x_init_clock_gating(struct drm_device *dev)
dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
OVRUNIT_CLOCK_GATE_DISABLE |
OVCUNIT_CLOCK_GATE_DISABLE;
- if (IS_GM45(dev))
+ if (IS_GM45(dev_priv))
dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
@@ -7757,7 +7759,7 @@ void intel_init_pm(struct drm_device *dev)
vlv_setup_wm_latency(dev);
dev_priv->display.update_wm = vlv_update_wm;
} else if (IS_PINEVIEW(dev)) {
- if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
+ if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
dev_priv->is_ddr3,
dev_priv->fsb_freq,
dev_priv->mem_freq)) {
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 0d9114f9ce27..5fe423571a7e 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1296,7 +1296,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
if (INTEL_INFO(dev)->gen >= 4) {
/* done in crtc_mode_set as the dpll_md reg must be written early */
- } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
+ } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
+ IS_G33(dev_priv)) {
/* done in crtc_mode_set as it lives inside the dpll register */
} else {
sdvox |= (crtc_state->pixel_multiplier - 1)
@@ -1389,7 +1390,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
* encoder->get_config we so already have a valid pixel multplier on all
* other platfroms.
*/
- if (IS_I915G(dev) || IS_I915GM(dev)) {
+ if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
pipe_config->pixel_multiplier =
((sdvox & SDVO_PORT_MULTIPLY_MASK)
>> SDVO_PORT_MULTIPLY_SHIFT) + 1;
@@ -1595,15 +1596,15 @@ static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct in
static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
{
- struct drm_device *dev = intel_sdvo->base.base.dev;
+ struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
uint16_t hotplug;
- if (!I915_HAS_HOTPLUG(dev))
+ if (!I915_HAS_HOTPLUG(dev_priv))
return 0;
/* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
* on the line. */
- if (IS_I945G(dev) || IS_I945GM(dev))
+ if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
return 0;
if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 3988c45f9e5f..df16b1dc4c2d 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1095,7 +1095,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
/* Enable two fixes for the chips that need them. */
- if (IS_I915GM(dev))
+ if (IS_I915GM(dev_priv))
tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
@@ -1220,7 +1220,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
* The TV sense state should be cleared to zero on cantiga platform. Otherwise
* the TV is misdetected. This is hardware requirement.
*/
- if (IS_GM45(dev))
+ if (IS_GM45(dev_priv))
tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 07/19] drm/i915: Make INTEL_DEVID only take dev_priv
2016-10-11 13:21 ` [PATCH 07/19] drm/i915: Make INTEL_DEVID " Tvrtko Ursulin
@ 2016-10-12 10:43 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 10:43 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:40PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 4472 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 14 +++--
> drivers/gpu/drm/i915/i915_drv.h | 111 +++++++++++++++++----------------
> drivers/gpu/drm/i915/i915_gem.c | 36 +++++------
> drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +-
> drivers/gpu/drm/i915/i915_gem_tiling.c | 3 +-
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_crt.c | 4 +-
> drivers/gpu/drm/i915/intel_display.c | 58 +++++++++--------
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> drivers/gpu/drm/i915/intel_i2c.c | 5 +-
> drivers/gpu/drm/i915/intel_lvds.c | 9 ++-
> drivers/gpu/drm/i915/intel_pm.c | 26 ++++----
> drivers/gpu/drm/i915/intel_sdvo.c | 11 ++--
> drivers/gpu/drm/i915/intel_tv.c | 4 +-
> 15 files changed, 151 insertions(+), 142 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index fbb4e2e0d124..bfdbbb745939 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -188,12 +188,14 @@ static void intel_detect_pch(struct drm_device *dev)
> dev_priv->pch_type = PCH_LPT;
> DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
> - WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
> + WARN_ON(IS_HSW_ULT(dev_priv) ||
> + IS_BDW_ULT(dev_priv));
> } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_LPT;
> DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
> WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
> - WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
> + WARN_ON(!IS_HSW_ULT(dev_priv) &&
> + !IS_BDW_ULT(dev_priv));
> } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_SPT;
> DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
> @@ -422,7 +424,7 @@ intel_setup_mchbar(struct drm_device *dev)
>
> dev_priv->mchbar_need_disable = false;
>
> - if (IS_I915G(dev) || IS_I915GM(dev)) {
> + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
> pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
> enabled = !!(temp & DEVEN_MCHBAR_EN);
> } else {
> @@ -440,7 +442,7 @@ intel_setup_mchbar(struct drm_device *dev)
> dev_priv->mchbar_need_disable = true;
>
> /* Space is allocated or reserved, so enable it. */
> - if (IS_I915G(dev) || IS_I915GM(dev)) {
> + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
> pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
> temp | DEVEN_MCHBAR_EN);
> } else {
> @@ -456,7 +458,7 @@ intel_teardown_mchbar(struct drm_device *dev)
> int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
>
> if (dev_priv->mchbar_need_disable) {
> - if (IS_I915G(dev) || IS_I915GM(dev)) {
> + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
> u32 deven_val;
>
> pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
> @@ -1077,7 +1079,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
> * be lost or delayed, but we use them anyways to avoid
> * stuck interrupts on some machines.
> */
> - if (!IS_I945G(dev) && !IS_I945GM(dev)) {
> + if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {
> if (pci_enable_msi(pdev) < 0)
> DRM_DEBUG_DRIVER("can't enable MSI");
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 58045cd7a087..7a40dfa830e7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2605,7 +2605,8 @@ struct drm_i915_cmd_table {
> })
> #define INTEL_INFO(p) (&__I915__(p)->info)
> #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
> -#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
> +
> +#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
>
> #define REVID_FOREVER 0xff
> #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
> @@ -2637,27 +2638,27 @@ struct drm_i915_cmd_table {
> #define IS_REVID(p, since, until) \
> (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>
> -#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
> -#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
> +#define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577)
> +#define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
> #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
> -#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
> +#define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572)
> #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
> -#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
> -#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
> +#define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592)
> +#define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772)
> #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
> #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
> #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
> -#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
> +#define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
> #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
> -#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
> -#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
> +#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
> +#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
> #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
> #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
> -#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
> +#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
> #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
> -#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
> - INTEL_DEVID(dev) == 0x0152 || \
> - INTEL_DEVID(dev) == 0x015a)
> +#define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
> + INTEL_DEVID(dev_priv) == 0x0152 || \
> + INTEL_DEVID(dev_priv) == 0x015a)
> #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
> #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
> #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
> @@ -2666,44 +2667,44 @@ struct drm_i915_cmd_table {
> #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
> #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
> #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
> -#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
> - (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
> -#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
> - ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
> - (INTEL_DEVID(dev) & 0xf) == 0xb || \
> - (INTEL_DEVID(dev) & 0xf) == 0xe))
> +#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> + (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
We've got a policy for the driver elsewhere that we drop workarounds for
pre-release hardware once proper hardware is available. What's so
special about this particular piece of hardware that makes the
workaround worth keeping around? Anyone?
> +#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
> + ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
> + (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
> + (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
> /* ULX machines are also considered ULT. */
> -#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
> - (INTEL_DEVID(dev) & 0xf) == 0xe)
> -#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
> - (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
> -#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
> - (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
> -#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
> - (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
> +#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
> + (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
> +#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
> + (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
> +#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
> + (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
> +#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
> + (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
> /* ULX machines are also considered ULT. */
> -#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
> - INTEL_DEVID(dev) == 0x0A1E)
> -#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
> - INTEL_DEVID(dev) == 0x1913 || \
> - INTEL_DEVID(dev) == 0x1916 || \
> - INTEL_DEVID(dev) == 0x1921 || \
> - INTEL_DEVID(dev) == 0x1926)
> -#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
> - INTEL_DEVID(dev) == 0x1915 || \
> - INTEL_DEVID(dev) == 0x191E)
> -#define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
> - INTEL_DEVID(dev) == 0x5913 || \
> - INTEL_DEVID(dev) == 0x5916 || \
> - INTEL_DEVID(dev) == 0x5921 || \
> - INTEL_DEVID(dev) == 0x5926)
> -#define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
> - INTEL_DEVID(dev) == 0x5915 || \
> - INTEL_DEVID(dev) == 0x591E)
> -#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
> - (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
> -#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
> - (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
> +#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
> + INTEL_DEVID(dev_priv) == 0x0A1E)
> +#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
> + INTEL_DEVID(dev_priv) == 0x1913 || \
> + INTEL_DEVID(dev_priv) == 0x1916 || \
> + INTEL_DEVID(dev_priv) == 0x1921 || \
> + INTEL_DEVID(dev_priv) == 0x1926)
> +#define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
> + INTEL_DEVID(dev_priv) == 0x1915 || \
> + INTEL_DEVID(dev_priv) == 0x191E)
> +#define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
> + INTEL_DEVID(dev_priv) == 0x5913 || \
> + INTEL_DEVID(dev_priv) == 0x5916 || \
> + INTEL_DEVID(dev_priv) == 0x5921 || \
> + INTEL_DEVID(dev_priv) == 0x5926)
> +#define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
> + INTEL_DEVID(dev_priv) == 0x5915 || \
> + INTEL_DEVID(dev_priv) == 0x591E)
> +#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
> + (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
> +#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
> + (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
>
> #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
>
> @@ -2782,7 +2783,7 @@ struct drm_i915_cmd_table {
> #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
>
> /* Early gen2 have a totally busted CS tlb and require pinned batches. */
> -#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
> +#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv))
>
> /* WaRsDisableCoarsePowerGating:skl,bxt */
> #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> @@ -2802,8 +2803,9 @@ struct drm_i915_cmd_table {
> /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
> * rows, which changed the alignment requirements and fence programming.
> */
> -#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
> - IS_I915GM(dev)))
> +#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
> + !(IS_I915G(dev_priv) || \
> + IS_I915GM(dev_priv)))
> #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
> #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
>
> @@ -2811,7 +2813,7 @@ struct drm_i915_cmd_table {
> #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
> #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
>
> -#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
> +#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
>
> #define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst)
>
> @@ -2867,7 +2869,8 @@ struct drm_i915_cmd_table {
>
> /* DPF == dynamic parity feature */
> #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
> -#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
> +#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
> + 2 : HAS_L3_DPF(dev_priv))
>
> #define GT_FREQUENCY_MULTIPLIER 50
> #define GEN9_FREQ_SCALER 3
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 6b099f0198cc..afaa49946042 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4321,30 +4321,28 @@ void i915_gem_init_swizzling(struct drm_device *dev)
> BUG();
> }
>
> -static void init_unused_ring(struct drm_device *dev, u32 base)
> +static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> -
> I915_WRITE(RING_CTL(base), 0);
> I915_WRITE(RING_HEAD(base), 0);
> I915_WRITE(RING_TAIL(base), 0);
> I915_WRITE(RING_START(base), 0);
> }
>
> -static void init_unused_rings(struct drm_device *dev)
> -{
> - if (IS_I830(dev)) {
> - init_unused_ring(dev, PRB1_BASE);
> - init_unused_ring(dev, SRB0_BASE);
> - init_unused_ring(dev, SRB1_BASE);
> - init_unused_ring(dev, SRB2_BASE);
> - init_unused_ring(dev, SRB3_BASE);
> - } else if (IS_GEN2(dev)) {
> - init_unused_ring(dev, SRB0_BASE);
> - init_unused_ring(dev, SRB1_BASE);
> - } else if (IS_GEN3(dev)) {
> - init_unused_ring(dev, PRB1_BASE);
> - init_unused_ring(dev, PRB2_BASE);
> +static void init_unused_rings(struct drm_i915_private *dev_priv)
> +{
> + if (IS_I830(dev_priv)) {
> + init_unused_ring(dev_priv, PRB1_BASE);
> + init_unused_ring(dev_priv, SRB0_BASE);
> + init_unused_ring(dev_priv, SRB1_BASE);
> + init_unused_ring(dev_priv, SRB2_BASE);
> + init_unused_ring(dev_priv, SRB3_BASE);
> + } else if (IS_GEN2(dev_priv)) {
> + init_unused_ring(dev_priv, SRB0_BASE);
> + init_unused_ring(dev_priv, SRB1_BASE);
> + } else if (IS_GEN3(dev_priv)) {
> + init_unused_ring(dev_priv, PRB1_BASE);
> + init_unused_ring(dev_priv, PRB2_BASE);
> }
> }
>
> @@ -4362,7 +4360,7 @@ i915_gem_init_hw(struct drm_device *dev)
> I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
>
> if (IS_HASWELL(dev))
> - I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
> + I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
> LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>
> if (HAS_PCH_NOP(dev_priv)) {
> @@ -4385,7 +4383,7 @@ i915_gem_init_hw(struct drm_device *dev)
> * will prevent c3 entry. Makes sure all unused rings
> * are totally idle.
> */
> - init_unused_rings(dev);
> + init_unused_rings(dev_priv);
>
> BUG_ON(!dev_priv->kernel_context);
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index 59989e8ee5dc..cbea6fb83ce5 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -115,7 +115,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
> pci_read_config_dword(pdev, INTEL_BSM, &bsm);
>
> base = bsm & INTEL_BSM_MASK;
> - } else if (IS_I865G(dev)) {
> + } else if (IS_I865G(dev_priv)) {
> u32 tseg_size = 0;
> u16 toud = 0;
> u8 tmp;
> @@ -154,7 +154,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
> tom = tmp * MB(32);
>
> base = tom - tseg_size - ggtt->stolen_size;
> - } else if (IS_845G(dev)) {
> + } else if (IS_845G(dev_priv)) {
> u32 tseg_size = 0;
> u32 tom;
> u8 tmp;
> @@ -178,7 +178,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
> tom = tmp * MB(32);
>
> base = tom - tseg_size - ggtt->stolen_size;
> - } else if (IS_I830(dev)) {
> + } else if (IS_I830(dev_priv)) {
> u32 tseg_size = 0;
> u32 tom;
> u8 tmp;
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index a14b1e3d4c78..89d1d234a1b4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -62,6 +62,7 @@
> static bool
> i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> int tile_width;
>
> /* Linear is always fine */
> @@ -72,7 +73,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> return false;
>
> if (IS_GEN2(dev) ||
> - (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
> + (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
> tile_width = 128;
> else
> tile_width = 512;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 883474411aee..5fb3b1c9a52c 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3656,7 +3656,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
>
> ibx_irq_postinstall(dev);
>
> - if (IS_IRONLAKE_M(dev)) {
> + if (IS_IRONLAKE_M(dev_priv)) {
> /* Enable PCU event interrupts
> *
> * spinlocking not required here for correctness since interrupt
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index f8919ef3a7af..d4388c03b4da 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -431,7 +431,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
> * to get a reliable result.
> */
>
> - if (IS_G4X(dev) && !IS_GM45(dev))
> + if (IS_G4X(dev_priv) && !IS_GM45(dev_priv))
> tries = 2;
> else
> tries = 1;
> @@ -894,7 +894,7 @@ void intel_crt_init(struct drm_device *dev)
>
> crt->base.type = INTEL_OUTPUT_ANALOG;
> crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
> - if (IS_I830(dev))
> + if (IS_I830(dev_priv))
> crt->base.crtc_mask = (1 << 0);
> else
> crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b7685936d324..ee3b593d3ec2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1230,10 +1230,9 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
> static void assert_cursor(struct drm_i915_private *dev_priv,
> enum pipe pipe, bool state)
> {
> - struct drm_device *dev = &dev_priv->drm;
> bool cur_state;
>
> - if (IS_845G(dev) || IS_I865G(dev))
> + if (IS_845G(dev_priv) || IS_I865G(dev_priv))
> cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
> else
> cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
> @@ -1617,11 +1616,11 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
> assert_pipe_disabled(dev_priv, crtc->pipe);
>
> /* PLL is protected by panel, make sure we can write it */
> - if (IS_MOBILE(dev) && !IS_I830(dev))
> + if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
> assert_panel_unlocked(dev_priv, crtc->pipe);
>
> /* Enable DVO 2x clock on both PLLs if necessary */
> - if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
> + if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev) > 0) {
> /*
> * It appears to be important that we don't enable this
> * for the current pipe before otherwise configuring the
> @@ -1686,7 +1685,7 @@ static void i9xx_disable_pll(struct intel_crtc *crtc)
> enum pipe pipe = crtc->pipe;
>
> /* Disable DVO 2x clock on both PLLs if necessary */
> - if (IS_I830(dev) &&
> + if (IS_I830(dev_priv) &&
> intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
> !intel_num_dvo_pipes(dev)) {
> I915_WRITE(DPLL(PIPE_B),
> @@ -5392,7 +5391,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> /* IPS only exists on ULT machines and is tied to pipe A. */
> static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
> {
> - return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
> + return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
> }
>
> static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> @@ -5864,9 +5863,9 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> */
> if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
> dev_priv->max_cdclk_freq = 450000;
> - else if (IS_BDW_ULX(dev))
> + else if (IS_BDW_ULX(dev_priv))
> dev_priv->max_cdclk_freq = 450000;
> - else if (IS_BDW_ULT(dev))
> + else if (IS_BDW_ULT(dev_priv))
> dev_priv->max_cdclk_freq = 540000;
> else
> dev_priv->max_cdclk_freq = 675000;
> @@ -7225,7 +7224,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
> return -EINVAL;
>
> - if (HAS_IPS(dev))
> + if (HAS_IPS(dev_priv))
> hsw_compute_ips_config(crtc, pipe_config);
>
> if (pipe_config->has_pch_encoder)
> @@ -7363,7 +7362,7 @@ static int haswell_get_display_clock_speed(struct drm_device *dev)
> return 450000;
> else if (freq == LCPLL_CLK_FREQ_450)
> return 450000;
> - else if (IS_HSW_ULT(dev))
> + else if (IS_HSW_ULT(dev_priv))
> return 337500;
> else
> return 540000;
> @@ -7533,7 +7532,7 @@ static unsigned int intel_hpll_vco(struct drm_device *dev)
> uint8_t tmp = 0;
>
> /* FIXME other chipsets? */
> - if (IS_GM45(dev))
> + if (IS_GM45(dev_priv))
> vco_table = ctg_vco;
> else if (IS_G4X(dev))
> vco_table = elk_vco;
> @@ -8152,7 +8151,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
> else
> dpll |= DPLLB_MODE_DAC_SERIAL;
>
> - if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
> + if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) {
> dpll |= (crtc_state->pixel_multiplier - 1)
> << SDVO_MULTIPLIER_SHIFT_HIRES;
> }
> @@ -8231,7 +8230,8 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
> dpll |= PLL_P2_DIVIDE_BY_4;
> }
>
> - if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
> + if (!IS_I830(dev_priv) &&
> + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
> dpll |= DPLL_DVO_2X_MODE;
>
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
> @@ -8654,7 +8654,8 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
> struct drm_i915_private *dev_priv = to_i915(dev);
> uint32_t tmp;
>
> - if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
> + if (INTEL_GEN(dev_priv) <= 3 &&
> + (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
> return;
>
> tmp = I915_READ(PFIT_CONTROL);
> @@ -8864,7 +8865,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
> >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
> pipe_config->dpll_hw_state.dpll_md = tmp;
> - } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
> + } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
> + IS_G33(dev_priv)) {
> tmp = I915_READ(DPLL(crtc->pipe));
> pipe_config->pixel_multiplier =
> ((tmp & SDVO_MULTIPLIER_MASK)
> @@ -8882,7 +8884,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> * on 830. Filter it out here so that we don't
> * report errors due to that.
> */
> - if (IS_I830(dev))
> + if (IS_I830(dev_priv))
> pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
>
> pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
> @@ -10904,13 +10906,13 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
>
> I915_WRITE(CURPOS(pipe), pos);
>
> - if (IS_845G(dev) || IS_I865G(dev))
> + if (IS_845G(dev_priv) || IS_I865G(dev_priv))
> i845_update_cursor(crtc, base, plane_state);
> else
> i9xx_update_cursor(crtc, base, plane_state);
> }
>
> -static bool cursor_size_ok(struct drm_device *dev,
> +static bool cursor_size_ok(struct drm_i915_private *dev_priv,
> uint32_t width, uint32_t height)
> {
> if (width == 0 || height == 0)
> @@ -10922,11 +10924,11 @@ static bool cursor_size_ok(struct drm_device *dev,
> * the precision of the register. Everything else requires
> * square cursors, limited to a few power-of-two sizes.
> */
> - if (IS_845G(dev) || IS_I865G(dev)) {
> + if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
> if ((width & 63) != 0)
> return false;
>
> - if (width > (IS_845G(dev) ? 64 : 512))
> + if (width > (IS_845G(dev_priv) ? 64 : 512))
> return false;
>
> if (height > 1023)
> @@ -10935,7 +10937,7 @@ static bool cursor_size_ok(struct drm_device *dev,
> switch (width | height) {
> case 256:
> case 128:
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> return false;
> case 64:
> break;
> @@ -11377,7 +11379,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> else
> port_clock = i9xx_calc_dpll_params(refclk, &clock);
> } else {
> - u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
> + u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
> bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
>
> if (is_lvds) {
> @@ -14658,6 +14660,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> struct drm_plane_state *new_state)
> {
> struct drm_device *dev = plane->dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_framebuffer *fb = new_state->fb;
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
> @@ -14709,7 +14712,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
>
> if (plane->type == DRM_PLANE_TYPE_CURSOR &&
> INTEL_INFO(dev)->cursor_needs_physical) {
> - int align = IS_I830(dev) ? 16 * 1024 : 256;
> + int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
> ret = i915_gem_object_attach_phys(obj, align);
> if (ret)
> DRM_DEBUG_KMS("failed to attach phys object\n");
> @@ -15031,7 +15034,8 @@ intel_check_cursor_plane(struct drm_plane *plane,
> return 0;
>
> /* Check for which cursor types we support */
> - if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
> + if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w,
> + state->base.crtc_h)) {
> DRM_DEBUG("Cursor dimension %dx%d not supported\n",
> state->base.crtc_w, state->base.crtc_h);
> return -EINVAL;
> @@ -15325,7 +15329,7 @@ static bool intel_crt_present(struct drm_device *dev)
> if (INTEL_INFO(dev)->gen >= 9)
> return false;
>
> - if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
> + if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
> return false;
>
> if (IS_CHERRYVIEW(dev))
> @@ -16384,8 +16388,8 @@ void intel_modeset_init(struct drm_device *dev)
> dev->mode_config.max_height = 8192;
> }
>
> - if (IS_845G(dev) || IS_I865G(dev)) {
> - dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
> + if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
> + dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
> dev->mode_config.cursor_height = 1023;
> } else if (IS_GEN2(dev)) {
> dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 51d92a9c6cb1..2e06dfb64bd4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5748,7 +5748,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> * 0xd. Failure to do so will result in spurious interrupts being
> * generated on the port when a cable is not attached.
> */
> - if (IS_G4X(dev) && !IS_GM45(dev)) {
> + if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
> u32 temp = I915_READ(PEG_BAND_GAP_DATA);
> I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
> }
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index ad3ff4fe63cf..6607c4e3c36c 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1921,7 +1921,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> * 0xd. Failure to do so will result in spurious interrupts being
> * generated on the port when a cable is not attached.
> */
> - if (IS_G4X(dev) && !IS_GM45(dev)) {
> + if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
> u32 temp = I915_READ(PEG_BAND_GAP_DATA);
> I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
> }
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 1410330ec9bb..afb2652919d0 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -138,11 +138,10 @@ static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
> static u32 get_reserved(struct intel_gmbus *bus)
> {
> struct drm_i915_private *dev_priv = bus->dev_priv;
> - struct drm_device *dev = &dev_priv->drm;
> u32 reserved = 0;
>
> /* On most chips, these bits must be preserved in software. */
> - if (!IS_I830(dev) && !IS_845G(dev))
> + if (!IS_I830(dev_priv) && !IS_845G(dev_priv))
> reserved = I915_READ_NOTRACE(bus->gpio_reg) &
> (GPIO_DATA_PULLUP_DISABLE |
> GPIO_CLOCK_PULLUP_DISABLE);
> @@ -674,7 +673,7 @@ int intel_setup_gmbus(struct drm_device *dev)
> bus->reg0 = pin | GMBUS_RATE_100KHZ;
>
> /* gmbus seems to be broken on i830 */
> - if (IS_I830(dev))
> + if (IS_I830(dev_priv))
> bus->force_bit = 1;
>
> intel_gpio_setup(bus, pin);
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index baaf2ed897ef..1c47f99917e6 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -949,10 +949,8 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
> return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
> }
>
> -static bool intel_lvds_supported(struct drm_device *dev)
> +static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> -
> /* With the introduction of the PCH we gained a dedicated
> * LVDS presence pin, use it. */
> if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
> @@ -960,7 +958,8 @@ static bool intel_lvds_supported(struct drm_device *dev)
>
> /* Otherwise LVDS was only attached to mobile products,
> * except for the inglorious 830gm */
> - if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
> + if (INTEL_GEN(dev_priv) <= 4 &&
> + IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
> return true;
>
> return false;
> @@ -992,7 +991,7 @@ void intel_lvds_init(struct drm_device *dev)
> int pipe;
> u8 pin;
>
> - if (!intel_lvds_supported(dev))
> + if (!intel_lvds_supported(dev_priv))
> return;
>
> /* Skip init on machines we know falsely report LVDS */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 86051ef2716e..04a38a37af2e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -334,12 +334,12 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
> val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
> I915_WRITE(DSPFW3, val);
> POSTING_READ(DSPFW3);
> - } else if (IS_I945G(dev) || IS_I945GM(dev)) {
> + } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
> val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
> _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
> I915_WRITE(FW_BLC_SELF, val);
> POSTING_READ(FW_BLC_SELF);
> - } else if (IS_I915GM(dev)) {
> + } else if (IS_I915GM(dev_priv)) {
> /*
> * FIXME can't find a bit like this for 915G, and
> * and yet it does have the related watermark in
> @@ -648,8 +648,10 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
> u32 reg;
> unsigned long wm;
>
> - latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
> - dev_priv->fsb_freq, dev_priv->mem_freq);
> + latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
> + dev_priv->is_ddr3,
> + dev_priv->fsb_freq,
> + dev_priv->mem_freq);
> if (!latency) {
> DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
> intel_set_memory_cxsr(dev_priv, false);
> @@ -1579,7 +1581,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
>
> DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
>
> - if (IS_I915GM(dev) && enabled) {
> + if (IS_I915GM(dev_priv) && enabled) {
> struct drm_i915_gem_object *obj;
>
> obj = intel_fb_obj(enabled->primary->state->fb);
> @@ -1609,7 +1611,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> unsigned long line_time_us;
> int entries;
>
> - if (IS_I915GM(dev) || IS_I945GM(dev))
> + if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
> cpp = 4;
>
> line_time_us = max(htotal * 1000 / clock, 1);
> @@ -1623,7 +1625,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> if (srwm < 0)
> srwm = 1;
>
> - if (IS_I945G(dev) || IS_I945GM(dev))
> + if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
> I915_WRITE(FW_BLC_SELF,
> FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
> else
> @@ -6930,7 +6932,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
> * The bit 22 of 0x42004
> * The bit 7,8,9 of 0x42020.
> */
> - if (IS_IRONLAKE_M(dev)) {
> + if (IS_IRONLAKE_M(dev_priv)) {
> /* WaFbcAsynchFlipDisableFbcQueue:ilk */
> I915_WRITE(ILK_DISPLAY_CHICKEN1,
> I915_READ(ILK_DISPLAY_CHICKEN1) |
> @@ -7340,7 +7342,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> CHICKEN3_DGMG_DONE_FIX_DISABLE);
>
> /* WaDisablePSDDualDispatchEnable:ivb */
> - if (IS_IVB_GT1(dev))
> + if (IS_IVB_GT1(dev_priv))
> I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>
> @@ -7356,7 +7358,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> GEN7_WA_FOR_GEN7_L3_CONTROL);
> I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
> GEN7_WA_L3_CHICKEN_MODE);
> - if (IS_IVB_GT1(dev))
> + if (IS_IVB_GT1(dev_priv))
> I915_WRITE(GEN7_ROW_CHICKEN2,
> _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> else {
> @@ -7550,7 +7552,7 @@ static void g4x_init_clock_gating(struct drm_device *dev)
> dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
> OVRUNIT_CLOCK_GATE_DISABLE |
> OVCUNIT_CLOCK_GATE_DISABLE;
> - if (IS_GM45(dev))
> + if (IS_GM45(dev_priv))
> dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
> I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
>
> @@ -7757,7 +7759,7 @@ void intel_init_pm(struct drm_device *dev)
> vlv_setup_wm_latency(dev);
> dev_priv->display.update_wm = vlv_update_wm;
> } else if (IS_PINEVIEW(dev)) {
> - if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
> + if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
> dev_priv->is_ddr3,
> dev_priv->fsb_freq,
> dev_priv->mem_freq)) {
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index 0d9114f9ce27..5fe423571a7e 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -1296,7 +1296,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
>
> if (INTEL_INFO(dev)->gen >= 4) {
> /* done in crtc_mode_set as the dpll_md reg must be written early */
> - } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
> + } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
> + IS_G33(dev_priv)) {
> /* done in crtc_mode_set as it lives inside the dpll register */
> } else {
> sdvox |= (crtc_state->pixel_multiplier - 1)
> @@ -1389,7 +1390,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
> * encoder->get_config we so already have a valid pixel multplier on all
> * other platfroms.
> */
> - if (IS_I915G(dev) || IS_I915GM(dev)) {
> + if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
> pipe_config->pixel_multiplier =
> ((sdvox & SDVO_PORT_MULTIPLY_MASK)
> >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
> @@ -1595,15 +1596,15 @@ static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct in
>
> static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
> {
> - struct drm_device *dev = intel_sdvo->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
> uint16_t hotplug;
>
> - if (!I915_HAS_HOTPLUG(dev))
> + if (!I915_HAS_HOTPLUG(dev_priv))
> return 0;
>
> /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
> * on the line. */
> - if (IS_I945G(dev) || IS_I945GM(dev))
> + if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
> return 0;
>
> if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
> diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
> index 3988c45f9e5f..df16b1dc4c2d 100644
> --- a/drivers/gpu/drm/i915/intel_tv.c
> +++ b/drivers/gpu/drm/i915/intel_tv.c
> @@ -1095,7 +1095,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
> tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
>
> /* Enable two fixes for the chips that need them. */
> - if (IS_I915GM(dev))
> + if (IS_I915GM(dev_priv))
> tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
>
> set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
> @@ -1220,7 +1220,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
> * The TV sense state should be cleared to zero on cantiga platform. Otherwise
> * the TV is misdetected. This is hardware requirement.
> */
> - if (IS_GM45(dev))
> + if (IS_GM45(dev_priv))
> tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
> TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 08/19] drm/i915: Make IS_IVYBRIDGE only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (6 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 07/19] drm/i915: Make INTEL_DEVID " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 10:40 ` David Weinehall
2016-10-11 13:21 ` [PATCH 09/19] drm/i915: Make IS_BROADWELL " Tvrtko Ursulin
` (12 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 848 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 19 +++++++++++--------
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
drivers/gpu/drm/i915/intel_pm.c | 13 +++++++------
drivers/gpu/drm/i915/intel_sprite.c | 2 +-
7 files changed, 28 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bfdbbb745939..f6ba8f262238 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -114,7 +114,7 @@ static bool i915_error_injected(struct drm_i915_private *dev_priv)
fmt, ##__VA_ARGS__)
-static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
+static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
{
enum intel_pch ret = PCH_NOP;
@@ -125,16 +125,16 @@ static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
* make an educated guess as to which PCH is really there.
*/
- if (IS_GEN5(dev)) {
+ if (IS_GEN5(dev_priv)) {
ret = PCH_IBX;
DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
- } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
+ } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
ret = PCH_CPT;
DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
- } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+ } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ret = PCH_LPT;
DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
- } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
ret = PCH_SPT;
DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
}
@@ -178,12 +178,14 @@ static void intel_detect_pch(struct drm_device *dev)
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
- WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
+ WARN_ON(!(IS_GEN6(dev_priv) ||
+ IS_IVYBRIDGE(dev_priv)));
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
/* PantherPoint is CPT compatible */
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found PantherPoint PCH\n");
- WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
+ WARN_ON(!(IS_GEN6(dev_priv) ||
+ IS_IVYBRIDGE(dev_priv)));
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
@@ -217,7 +219,8 @@ static void intel_detect_pch(struct drm_device *dev)
PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
pch->subsystem_device ==
PCI_SUBDEVICE_ID_QEMU)) {
- dev_priv->pch_type = intel_virt_detect_pch(dev);
+ dev_priv->pch_type =
+ intel_virt_detect_pch(dev_priv);
} else
continue;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7a40dfa830e7..3f321932d18a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2655,7 +2655,7 @@ struct drm_i915_cmd_table {
#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
-#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
+#define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
#define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
INTEL_DEVID(dev_priv) == 0x0152 || \
INTEL_DEVID(dev_priv) == 0x015a)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index afaa49946042..6da841500510 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4364,7 +4364,7 @@ i915_gem_init_hw(struct drm_device *dev)
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
if (HAS_PCH_NOP(dev_priv)) {
- if (IS_IVYBRIDGE(dev)) {
+ if (IS_IVYBRIDGE(dev_priv)) {
u32 temp = I915_READ(GEN7_MSG_CTL);
temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
I915_WRITE(GEN7_MSG_CTL, temp);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index df10f4e95736..e117b98c726f 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -192,7 +192,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
* This is only applicable for Ivy Bridge devices since
* later platforms don't have L3 control bits in the PTE.
*/
- if (IS_IVYBRIDGE(dev)) {
+ if (IS_IVYBRIDGE(to_i915(dev))) {
ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
/* Failure shouldn't ever happen this early */
if (WARN_ON(ret)) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ee3b593d3ec2..7894675bfcb8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3729,7 +3729,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
/* enable normal train */
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
- if (IS_IVYBRIDGE(dev)) {
+ if (IS_IVYBRIDGE(dev_priv)) {
temp &= ~FDI_LINK_TRAIN_NONE_IVB;
temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
} else {
@@ -3754,7 +3754,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
udelay(1000);
/* IVB wants error correction enabled */
- if (IS_IVYBRIDGE(dev))
+ if (IS_IVYBRIDGE(dev_priv))
I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
FDI_FE_ERRC_ENABLE);
}
@@ -4540,7 +4540,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
assert_pch_transcoder_disabled(dev_priv, pipe);
- if (IS_IVYBRIDGE(dev))
+ if (IS_IVYBRIDGE(dev_priv))
ivybridge_update_fdi_bc_bifurcation(intel_crtc);
/* Write the TU size bits before fdi link training, so that error
@@ -4854,7 +4854,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
* as some pre-programmed values are broken,
* e.g. x201.
*/
- if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
+ if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
PF_PIPE_SEL_IVB(pipe));
else
@@ -12251,7 +12251,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (fb->modifier[0] != old_fb->modifier[0])
/* vlv: DISPLAY_FLIP fails to change tiling */
engine = NULL;
- } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
+ } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
engine = &dev_priv->engine[BCS];
} else if (INTEL_INFO(dev)->gen >= 7) {
engine = i915_gem_active_get_engine(&obj->last_write,
@@ -12527,7 +12527,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
* cstate->update_wm was already set above, so this flag will
* take effect when we commit and program watermarks.
*/
- if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
+ if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
needs_scaling(to_intel_plane_state(plane_state)) &&
!needs_scaling(old_plane_state))
pipe_config->disable_lp_wm = true;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 04a38a37af2e..9155735d01df 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2191,14 +2191,15 @@ static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
wm[0] = 13;
}
-static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
+static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
+ uint16_t wm[5])
{
/* ILK cursor LP0 latency is 1300 ns */
- if (IS_GEN5(dev))
+ if (IS_GEN5(dev_priv))
wm[0] = 13;
/* WaDoubleCursorLP3Latency:ivb */
- if (IS_IVYBRIDGE(dev))
+ if (IS_IVYBRIDGE(dev_priv))
wm[3] *= 2;
}
@@ -2294,7 +2295,7 @@ static void ilk_setup_wm_latency(struct drm_device *dev)
sizeof(dev_priv->wm.pri_latency));
intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
- intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
+ intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
@@ -2522,7 +2523,7 @@ static void ilk_wm_merge(struct drm_device *dev,
int last_enabled_level = max_level;
/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
- if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
+ if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
config->num_pipes_active > 1)
last_enabled_level = 0;
@@ -4617,7 +4618,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
- else if (IS_IVYBRIDGE(dev))
+ else if (IS_IVYBRIDGE(dev_priv))
hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 73a521fdf1bd..d0f798ce6bb2 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1084,7 +1084,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
case 7:
case 8:
- if (IS_IVYBRIDGE(dev)) {
+ if (IS_IVYBRIDGE(to_i915(dev))) {
intel_plane->can_scale = true;
intel_plane->max_downscale = 2;
} else {
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 08/19] drm/i915: Make IS_IVYBRIDGE only take dev_priv
2016-10-11 13:21 ` [PATCH 08/19] drm/i915: Make IS_IVYBRIDGE " Tvrtko Ursulin
@ 2016-10-12 10:40 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 10:40 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:41PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 848 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 19 +++++++++++--------
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_pm.c | 13 +++++++------
> drivers/gpu/drm/i915/intel_sprite.c | 2 +-
> 7 files changed, 28 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index bfdbbb745939..f6ba8f262238 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -114,7 +114,7 @@ static bool i915_error_injected(struct drm_i915_private *dev_priv)
> fmt, ##__VA_ARGS__)
>
>
> -static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
> +static enum intel_pch intel_virt_detect_pch(struct drm_i915_private *dev_priv)
> {
> enum intel_pch ret = PCH_NOP;
>
> @@ -125,16 +125,16 @@ static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
> * make an educated guess as to which PCH is really there.
> */
>
> - if (IS_GEN5(dev)) {
> + if (IS_GEN5(dev_priv)) {
> ret = PCH_IBX;
> DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
> - } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
> + } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
> ret = PCH_CPT;
> DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
> - } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> ret = PCH_LPT;
> DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
> - } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> ret = PCH_SPT;
> DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
> }
> @@ -178,12 +178,14 @@ static void intel_detect_pch(struct drm_device *dev)
> } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_CPT;
> DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> - WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
> + WARN_ON(!(IS_GEN6(dev_priv) ||
> + IS_IVYBRIDGE(dev_priv)));
> } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
> /* PantherPoint is CPT compatible */
> dev_priv->pch_type = PCH_CPT;
> DRM_DEBUG_KMS("Found PantherPoint PCH\n");
> - WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
> + WARN_ON(!(IS_GEN6(dev_priv) ||
> + IS_IVYBRIDGE(dev_priv)));
> } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_LPT;
> DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> @@ -217,7 +219,8 @@ static void intel_detect_pch(struct drm_device *dev)
> PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
> pch->subsystem_device ==
> PCI_SUBDEVICE_ID_QEMU)) {
> - dev_priv->pch_type = intel_virt_detect_pch(dev);
> + dev_priv->pch_type =
> + intel_virt_detect_pch(dev_priv);
> } else
> continue;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7a40dfa830e7..3f321932d18a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2655,7 +2655,7 @@ struct drm_i915_cmd_table {
> #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
> #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
> #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
> -#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
> +#define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
> #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
> INTEL_DEVID(dev_priv) == 0x0152 || \
> INTEL_DEVID(dev_priv) == 0x015a)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index afaa49946042..6da841500510 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4364,7 +4364,7 @@ i915_gem_init_hw(struct drm_device *dev)
> LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>
> if (HAS_PCH_NOP(dev_priv)) {
> - if (IS_IVYBRIDGE(dev)) {
> + if (IS_IVYBRIDGE(dev_priv)) {
> u32 temp = I915_READ(GEN7_MSG_CTL);
> temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
> I915_WRITE(GEN7_MSG_CTL, temp);
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index df10f4e95736..e117b98c726f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -192,7 +192,7 @@ i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
> * This is only applicable for Ivy Bridge devices since
> * later platforms don't have L3 control bits in the PTE.
> */
> - if (IS_IVYBRIDGE(dev)) {
> + if (IS_IVYBRIDGE(to_i915(dev))) {
> ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
> /* Failure shouldn't ever happen this early */
> if (WARN_ON(ret)) {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ee3b593d3ec2..7894675bfcb8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3729,7 +3729,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
> /* enable normal train */
> reg = FDI_TX_CTL(pipe);
> temp = I915_READ(reg);
> - if (IS_IVYBRIDGE(dev)) {
> + if (IS_IVYBRIDGE(dev_priv)) {
> temp &= ~FDI_LINK_TRAIN_NONE_IVB;
> temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
> } else {
> @@ -3754,7 +3754,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
> udelay(1000);
>
> /* IVB wants error correction enabled */
> - if (IS_IVYBRIDGE(dev))
> + if (IS_IVYBRIDGE(dev_priv))
> I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
> FDI_FE_ERRC_ENABLE);
> }
> @@ -4540,7 +4540,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>
> assert_pch_transcoder_disabled(dev_priv, pipe);
>
> - if (IS_IVYBRIDGE(dev))
> + if (IS_IVYBRIDGE(dev_priv))
> ivybridge_update_fdi_bc_bifurcation(intel_crtc);
>
> /* Write the TU size bits before fdi link training, so that error
> @@ -4854,7 +4854,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
> * as some pre-programmed values are broken,
> * e.g. x201.
> */
> - if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
> + if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
> I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
> PF_PIPE_SEL_IVB(pipe));
> else
> @@ -12251,7 +12251,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
> if (fb->modifier[0] != old_fb->modifier[0])
> /* vlv: DISPLAY_FLIP fails to change tiling */
> engine = NULL;
> - } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
> + } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
> engine = &dev_priv->engine[BCS];
> } else if (INTEL_INFO(dev)->gen >= 7) {
> engine = i915_gem_active_get_engine(&obj->last_write,
> @@ -12527,7 +12527,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
> * cstate->update_wm was already set above, so this flag will
> * take effect when we commit and program watermarks.
> */
> - if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
> + if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) &&
> needs_scaling(to_intel_plane_state(plane_state)) &&
> !needs_scaling(old_plane_state))
> pipe_config->disable_lp_wm = true;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 04a38a37af2e..9155735d01df 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2191,14 +2191,15 @@ static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
> wm[0] = 13;
> }
>
> -static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
> +static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
> + uint16_t wm[5])
> {
> /* ILK cursor LP0 latency is 1300 ns */
> - if (IS_GEN5(dev))
> + if (IS_GEN5(dev_priv))
> wm[0] = 13;
>
> /* WaDoubleCursorLP3Latency:ivb */
> - if (IS_IVYBRIDGE(dev))
> + if (IS_IVYBRIDGE(dev_priv))
> wm[3] *= 2;
> }
>
> @@ -2294,7 +2295,7 @@ static void ilk_setup_wm_latency(struct drm_device *dev)
> sizeof(dev_priv->wm.pri_latency));
>
> intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
> - intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
> + intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
>
> intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
> intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
> @@ -2522,7 +2523,7 @@ static void ilk_wm_merge(struct drm_device *dev,
> int last_enabled_level = max_level;
>
> /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
> - if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
> + if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
> config->num_pipes_active > 1)
> last_enabled_level = 0;
>
> @@ -4617,7 +4618,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
> if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
> INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
> - else if (IS_IVYBRIDGE(dev))
> + else if (IS_IVYBRIDGE(dev_priv))
> hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
> INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 73a521fdf1bd..d0f798ce6bb2 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1084,7 +1084,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
>
> case 7:
> case 8:
> - if (IS_IVYBRIDGE(dev)) {
> + if (IS_IVYBRIDGE(to_i915(dev))) {
> intel_plane->can_scale = true;
> intel_plane->max_downscale = 2;
> } else {
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 09/19] drm/i915: Make IS_BROADWELL only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (7 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 08/19] drm/i915: Make IS_IVYBRIDGE " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 12:07 ` David Weinehall
2016-10-11 13:21 ` [PATCH 10/19] drm/i915: Make IS_HASWELL " Tvrtko Ursulin
` (11 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 1808 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 6 ++++--
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
drivers/gpu/drm/i915/i915_gem.c | 5 +++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/intel_color.c | 4 ++--
drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++----------
drivers/gpu/drm/i915/intel_dp.c | 19 ++++++++++---------
drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++---------
drivers/gpu/drm/i915/intel_psr.c | 4 ++--
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
drivers/gpu/drm/i915/intel_sprite.c | 8 ++++----
11 files changed, 52 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f6ba8f262238..8899835fffab 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -189,13 +189,15 @@ static void intel_detect_pch(struct drm_device *dev)
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
- WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
+ WARN_ON(!IS_HASWELL(dev_priv) &&
+ !IS_BROADWELL(dev_priv));
WARN_ON(IS_HSW_ULT(dev_priv) ||
IS_BDW_ULT(dev_priv));
} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_LPT;
DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
- WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
+ WARN_ON(!IS_HASWELL(dev_priv) &&
+ !IS_BROADWELL(dev_priv));
WARN_ON(!IS_HSW_ULT(dev_priv) &&
!IS_BDW_ULT(dev_priv));
} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3f321932d18a..13e409554fcc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2662,7 +2662,7 @@ struct drm_i915_cmd_table {
#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
-#define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
+#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
@@ -2769,8 +2769,8 @@ struct drm_i915_cmd_table {
#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
#define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
#define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
-#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
- HAS_EDRAM(dev))
+#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
+ IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
#define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical)
#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6da841500510..aefb88f987b2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3473,7 +3473,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
level = I915_CACHE_LLC;
break;
case I915_CACHING_DISPLAY:
- level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
+ level = HAS_WT(dev_priv) ? I915_CACHE_WT : I915_CACHE_NONE;
break;
default:
return -EINVAL;
@@ -3531,7 +3531,8 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
* with that bit in the PTE to main memory with just one PIPE_CONTROL.
*/
ret = i915_gem_object_set_cache_level(obj,
- HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
+ HAS_WT(to_i915(obj->base.dev)) ?
+ I915_CACHE_WT : I915_CACHE_NONE);
if (ret) {
vma = ERR_PTR(ret);
goto err_unpin_display;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0bb4232f66bc..0f8f073c589c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2129,7 +2129,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
* workarounds here even if they get overwritten by GPU reset.
*/
/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
- if (IS_BROADWELL(dev))
+ if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 5362c07932d3..be76ef88678c 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -540,8 +540,8 @@ void intel_color_init(struct drm_crtc *crtc)
} else if (IS_HASWELL(dev)) {
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
dev_priv->display.load_luts = haswell_load_luts;
- } else if (IS_BROADWELL(dev) || IS_SKYLAKE(dev) ||
- IS_BROXTON(dev) || IS_KABYLAKE(dev)) {
+ } else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
+ IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) {
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
dev_priv->display.load_luts = broadwell_load_luts;
} else {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7894675bfcb8..d159a315099f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3139,7 +3139,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
dspcntr = DISPPLANE_GAMMA_ENABLE;
dspcntr |= DISPLAY_PLANE_ENABLE;
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
switch (fb->pixel_format) {
@@ -3168,7 +3168,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
dspcntr |= DISPPLANE_TILED;
- if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
+ if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
intel_add_fb_offsets(&x, &y, plane_state, 0);
@@ -3179,7 +3179,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
if (rotation == DRM_ROTATE_180) {
dspcntr |= DISPPLANE_ROTATE_180;
- if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
+ if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
x += (crtc_state->pipe_src_w - 1);
y += (crtc_state->pipe_src_h - 1);
}
@@ -3196,7 +3196,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
I915_WRITE(DSPSURF(plane),
intel_fb_gtt_offset(fb, rotation) +
intel_crtc->dspaddr_offset);
- if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
} else {
I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
@@ -4879,7 +4879,7 @@ void hsw_enable_ips(struct intel_crtc *crtc)
*/
assert_plane_enabled(dev_priv, crtc->plane);
- if (IS_BROADWELL(dev)) {
+ if (IS_BROADWELL(dev_priv)) {
mutex_lock(&dev_priv->rps.hw_lock);
WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
mutex_unlock(&dev_priv->rps.hw_lock);
@@ -4911,7 +4911,7 @@ void hsw_disable_ips(struct intel_crtc *crtc)
return;
assert_plane_enabled(dev_priv, crtc->plane);
- if (IS_BROADWELL(dev)) {
+ if (IS_BROADWELL(dev_priv)) {
mutex_lock(&dev_priv->rps.hw_lock);
WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
mutex_unlock(&dev_priv->rps.hw_lock);
@@ -5854,7 +5854,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
} else if (IS_BROXTON(dev)) {
dev_priv->max_cdclk_freq = 624000;
- } else if (IS_BROADWELL(dev)) {
+ } else if (IS_BROADWELL(dev_priv)) {
/*
* FIXME with extra cooling we can allow
* 540 MHz for ULX and 675 Mhz for ULT.
@@ -7023,6 +7023,7 @@ static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
struct intel_crtc_state *pipe_config)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_atomic_state *state = pipe_config->base.state;
struct intel_crtc *other_crtc;
struct intel_crtc_state *other_crtc_state;
@@ -7035,7 +7036,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
return -EINVAL;
}
- if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
if (pipe_config->fdi_lanes > 2) {
DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
pipe_config->fdi_lanes);
@@ -9883,7 +9884,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
- if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
offset = I915_READ(DSPOFFSET(pipe));
} else {
if (plane_config->tiling)
@@ -17244,7 +17245,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
return;
err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
err_printf(m, "PWR_WELL_CTL2: %08x\n",
error->power_well_driver);
for_each_pipe(dev_priv, i) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2e06dfb64bd4..02e74c467a55 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -821,15 +821,16 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
uint32_t aux_clock_divider)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
- struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv =
+ to_i915(intel_dig_port->base.base.dev);
uint32_t precharge, timeout;
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev_priv))
precharge = 3;
else
precharge = 5;
- if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
+ if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
else
timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
@@ -2999,10 +3000,10 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
- struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
enum port port = dp_to_dig_port(intel_dp)->port;
- if (INTEL_INFO(dev)->gen >= 9) {
+ if (INTEL_GEN(dev_priv) >= 9) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
return DP_TRAIN_PRE_EMPH_LEVEL_3;
@@ -3015,7 +3016,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
default:
return DP_TRAIN_PRE_EMPH_LEVEL_0;
}
- } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+ } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
return DP_TRAIN_PRE_EMPH_LEVEL_3;
@@ -3027,7 +3028,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
default:
return DP_TRAIN_PRE_EMPH_LEVEL_0;
}
- } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
return DP_TRAIN_PRE_EMPH_LEVEL_3;
@@ -3039,7 +3040,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
default:
return DP_TRAIN_PRE_EMPH_LEVEL_0;
}
- } else if (IS_GEN7(dev) && port == PORT_A) {
+ } else if (IS_GEN7(dev_priv) && port == PORT_A) {
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
return DP_TRAIN_PRE_EMPH_LEVEL_2;
@@ -5648,7 +5649,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
/* intel_dp vfuncs */
if (INTEL_INFO(dev)->gen >= 9)
intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
- else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
else if (HAS_PCH_SPLIT(dev_priv))
intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9155735d01df..3ba9502cf2c2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2157,7 +2157,7 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
}
}
- } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+ } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
uint64_t sskpd = I915_READ64(MCH_SSKPD);
wm[0] = (sskpd >> 56) & 0xFF;
@@ -2205,12 +2205,14 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
int ilk_wm_max_level(const struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
/* how many WM levels are we expecting */
- if (INTEL_INFO(dev)->gen >= 9)
+ if (INTEL_GEN(dev_priv) >= 9)
return 7;
- else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
return 4;
- else if (INTEL_INFO(dev)->gen >= 6)
+ else if (INTEL_GEN(dev_priv) >= 6)
return 3;
else
return 2;
@@ -2393,7 +2395,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
pipe_wm->wm[0] = pipe_wm->raw_wm[0];
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
if (!ilk_validate_pipe_wm(dev, pipe_wm))
@@ -2580,7 +2582,7 @@ static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
return 2 * level;
else
return dev_priv->wm.pri_latency[level];
@@ -2804,7 +2806,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
if (dirty & WM_DIRTY_DDB) {
- if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
val = I915_READ(WM_MISC);
if (results->partitioning == INTEL_DDB_PART_1_2)
val &= ~WM_MISC_DATA_PARTITION_5_6;
@@ -4407,7 +4409,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
};
hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
memset(active, 0, sizeof(*active));
@@ -4615,7 +4617,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
}
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
else if (IS_IVYBRIDGE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 9e2fbac9776e..d0667f9d9178 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -827,14 +827,14 @@ void intel_psr_init(struct drm_device *dev)
/* Per platform default */
if (i915.enable_psr == -1) {
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
i915.enable_psr = 1;
else
i915.enable_psr = 0;
}
/* Set link_standby x link_off defaults */
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
/* HSW and BDW require workarounds that we don't implement. */
dev_priv->psr.link_standby = false;
else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ed1faf14f777..77ef03cb6163 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -288,7 +288,6 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv,
static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
- struct drm_device *dev = &dev_priv->drm;
/*
* After we re-enable the power well, if we touch VGA register 0x3d5
@@ -304,7 +303,7 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
vga_put(pdev, VGA_RSRC_LEGACY_IO);
- if (IS_BROADWELL(dev))
+ if (IS_BROADWELL(dev_priv))
gen8_irq_power_well_post_enable(dev_priv,
1 << PIPE_C | 1 << PIPE_B);
}
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index d0f798ce6bb2..fefd3034aead 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -542,12 +542,12 @@ ivb_update_plane(struct drm_plane *plane,
if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
sprctl |= SPRITE_TILED;
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
else
sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
sprctl |= SPRITE_PIPE_CSC_ENABLE;
/* Sizes are 0 based */
@@ -566,7 +566,7 @@ ivb_update_plane(struct drm_plane *plane,
sprctl |= SPRITE_ROTATE_180;
/* HSW and BDW does this automagically in hardware */
- if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
+ if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
x += src_w;
y += src_h;
}
@@ -590,7 +590,7 @@ ivb_update_plane(struct drm_plane *plane,
/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
* register */
- if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
else if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 09/19] drm/i915: Make IS_BROADWELL only take dev_priv
2016-10-11 13:21 ` [PATCH 09/19] drm/i915: Make IS_BROADWELL " Tvrtko Ursulin
@ 2016-10-12 12:07 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 12:07 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:42PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 1808 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 6 ++++--
> drivers/gpu/drm/i915/i915_drv.h | 6 +++---
> drivers/gpu/drm/i915/i915_gem.c | 5 +++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> drivers/gpu/drm/i915/intel_color.c | 4 ++--
> drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++----------
> drivers/gpu/drm/i915/intel_dp.c | 19 ++++++++++---------
> drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++---------
> drivers/gpu/drm/i915/intel_psr.c | 4 ++--
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
> drivers/gpu/drm/i915/intel_sprite.c | 8 ++++----
> 11 files changed, 52 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index f6ba8f262238..8899835fffab 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -189,13 +189,15 @@ static void intel_detect_pch(struct drm_device *dev)
> } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_LPT;
> DRM_DEBUG_KMS("Found LynxPoint PCH\n");
> - WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
> + WARN_ON(!IS_HASWELL(dev_priv) &&
> + !IS_BROADWELL(dev_priv));
> WARN_ON(IS_HSW_ULT(dev_priv) ||
> IS_BDW_ULT(dev_priv));
> } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_LPT;
> DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
> - WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
> + WARN_ON(!IS_HASWELL(dev_priv) &&
> + !IS_BROADWELL(dev_priv));
> WARN_ON(!IS_HSW_ULT(dev_priv) &&
> !IS_BDW_ULT(dev_priv));
> } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3f321932d18a..13e409554fcc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2662,7 +2662,7 @@ struct drm_i915_cmd_table {
> #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
> #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
> #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
> -#define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
> +#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
> #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
> #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
> @@ -2769,8 +2769,8 @@ struct drm_i915_cmd_table {
> #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
> #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
> #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
> -#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
> - HAS_EDRAM(dev))
> +#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
> + IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
> #define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical)
>
> #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 6da841500510..aefb88f987b2 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3473,7 +3473,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
> level = I915_CACHE_LLC;
> break;
> case I915_CACHING_DISPLAY:
> - level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
> + level = HAS_WT(dev_priv) ? I915_CACHE_WT : I915_CACHE_NONE;
> break;
> default:
> return -EINVAL;
> @@ -3531,7 +3531,8 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
> * with that bit in the PTE to main memory with just one PIPE_CONTROL.
> */
> ret = i915_gem_object_set_cache_level(obj,
> - HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
> + HAS_WT(to_i915(obj->base.dev)) ?
> + I915_CACHE_WT : I915_CACHE_NONE);
> if (ret) {
> vma = ERR_PTR(ret);
> goto err_unpin_display;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 0bb4232f66bc..0f8f073c589c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2129,7 +2129,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
> * workarounds here even if they get overwritten by GPU reset.
> */
> /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
> - if (IS_BROADWELL(dev))
> + if (IS_BROADWELL(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
> else if (IS_CHERRYVIEW(dev))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 5362c07932d3..be76ef88678c 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -540,8 +540,8 @@ void intel_color_init(struct drm_crtc *crtc)
> } else if (IS_HASWELL(dev)) {
> dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
> dev_priv->display.load_luts = haswell_load_luts;
> - } else if (IS_BROADWELL(dev) || IS_SKYLAKE(dev) ||
> - IS_BROXTON(dev) || IS_KABYLAKE(dev)) {
> + } else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
> + IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) {
> dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
> dev_priv->display.load_luts = broadwell_load_luts;
> } else {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7894675bfcb8..d159a315099f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3139,7 +3139,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> dspcntr = DISPPLANE_GAMMA_ENABLE;
> dspcntr |= DISPLAY_PLANE_ENABLE;
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>
> switch (fb->pixel_format) {
> @@ -3168,7 +3168,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
> dspcntr |= DISPPLANE_TILED;
>
> - if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
> + if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv))
> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>
> intel_add_fb_offsets(&x, &y, plane_state, 0);
> @@ -3179,7 +3179,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> if (rotation == DRM_ROTATE_180) {
> dspcntr |= DISPPLANE_ROTATE_180;
>
> - if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> + if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
> x += (crtc_state->pipe_src_w - 1);
> y += (crtc_state->pipe_src_h - 1);
> }
> @@ -3196,7 +3196,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
> I915_WRITE(DSPSURF(plane),
> intel_fb_gtt_offset(fb, rotation) +
> intel_crtc->dspaddr_offset);
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
> } else {
> I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
> @@ -4879,7 +4879,7 @@ void hsw_enable_ips(struct intel_crtc *crtc)
> */
>
> assert_plane_enabled(dev_priv, crtc->plane);
> - if (IS_BROADWELL(dev)) {
> + if (IS_BROADWELL(dev_priv)) {
> mutex_lock(&dev_priv->rps.hw_lock);
> WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
> mutex_unlock(&dev_priv->rps.hw_lock);
> @@ -4911,7 +4911,7 @@ void hsw_disable_ips(struct intel_crtc *crtc)
> return;
>
> assert_plane_enabled(dev_priv, crtc->plane);
> - if (IS_BROADWELL(dev)) {
> + if (IS_BROADWELL(dev_priv)) {
> mutex_lock(&dev_priv->rps.hw_lock);
> WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
> mutex_unlock(&dev_priv->rps.hw_lock);
> @@ -5854,7 +5854,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
> } else if (IS_BROXTON(dev)) {
> dev_priv->max_cdclk_freq = 624000;
> - } else if (IS_BROADWELL(dev)) {
> + } else if (IS_BROADWELL(dev_priv)) {
> /*
> * FIXME with extra cooling we can allow
> * 540 MHz for ULX and 675 Mhz for ULT.
> @@ -7023,6 +7023,7 @@ static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
> static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
> struct intel_crtc_state *pipe_config)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_atomic_state *state = pipe_config->base.state;
> struct intel_crtc *other_crtc;
> struct intel_crtc_state *other_crtc_state;
> @@ -7035,7 +7036,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
> return -EINVAL;
> }
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> if (pipe_config->fdi_lanes > 2) {
> DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
> pipe_config->fdi_lanes);
> @@ -9883,7 +9884,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
> fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
>
> base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> offset = I915_READ(DSPOFFSET(pipe));
> } else {
> if (plane_config->tiling)
> @@ -17244,7 +17245,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
> return;
>
> err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> err_printf(m, "PWR_WELL_CTL2: %08x\n",
> error->power_well_driver);
> for_each_pipe(dev_priv, i) {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2e06dfb64bd4..02e74c467a55 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -821,15 +821,16 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
> uint32_t aux_clock_divider)
> {
> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> - struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv =
> + to_i915(intel_dig_port->base.base.dev);
> uint32_t precharge, timeout;
>
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> precharge = 3;
> else
> precharge = 5;
>
> - if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
> + if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
> timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
> else
> timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> @@ -2999,10 +3000,10 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> uint8_t
> intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> {
> - struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
> enum port port = dp_to_dig_port(intel_dp)->port;
>
> - if (INTEL_INFO(dev)->gen >= 9) {
> + if (INTEL_GEN(dev_priv) >= 9) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> return DP_TRAIN_PRE_EMPH_LEVEL_3;
> @@ -3015,7 +3016,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> default:
> return DP_TRAIN_PRE_EMPH_LEVEL_0;
> }
> - } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> return DP_TRAIN_PRE_EMPH_LEVEL_3;
> @@ -3027,7 +3028,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> default:
> return DP_TRAIN_PRE_EMPH_LEVEL_0;
> }
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> return DP_TRAIN_PRE_EMPH_LEVEL_3;
> @@ -3039,7 +3040,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
> default:
> return DP_TRAIN_PRE_EMPH_LEVEL_0;
> }
> - } else if (IS_GEN7(dev) && port == PORT_A) {
> + } else if (IS_GEN7(dev_priv) && port == PORT_A) {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> return DP_TRAIN_PRE_EMPH_LEVEL_2;
> @@ -5648,7 +5649,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> /* intel_dp vfuncs */
> if (INTEL_INFO(dev)->gen >= 9)
> intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
> - else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
> else if (HAS_PCH_SPLIT(dev_priv))
> intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9155735d01df..3ba9502cf2c2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2157,7 +2157,7 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
> }
> }
>
> - } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> uint64_t sskpd = I915_READ64(MCH_SSKPD);
>
> wm[0] = (sskpd >> 56) & 0xFF;
> @@ -2205,12 +2205,14 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
>
> int ilk_wm_max_level(const struct drm_device *dev)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> /* how many WM levels are we expecting */
> - if (INTEL_INFO(dev)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> return 7;
> - else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> return 4;
> - else if (INTEL_INFO(dev)->gen >= 6)
> + else if (INTEL_GEN(dev_priv) >= 6)
> return 3;
> else
> return 2;
> @@ -2393,7 +2395,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
> memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
> pipe_wm->wm[0] = pipe_wm->raw_wm[0];
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
>
> if (!ilk_validate_pipe_wm(dev, pipe_wm))
> @@ -2580,7 +2582,7 @@ static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> return 2 * level;
> else
> return dev_priv->wm.pri_latency[level];
> @@ -2804,7 +2806,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
> I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
>
> if (dirty & WM_DIRTY_DDB) {
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> val = I915_READ(WM_MISC);
> if (results->partitioning == INTEL_DDB_PART_1_2)
> val &= ~WM_MISC_DATA_PARTITION_5_6;
> @@ -4407,7 +4409,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
> };
>
> hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
>
> memset(active, 0, sizeof(*active));
> @@ -4615,7 +4617,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev)
> hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
> }
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
> INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
> else if (IS_IVYBRIDGE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 9e2fbac9776e..d0667f9d9178 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -827,14 +827,14 @@ void intel_psr_init(struct drm_device *dev)
>
> /* Per platform default */
> if (i915.enable_psr == -1) {
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> i915.enable_psr = 1;
> else
> i915.enable_psr = 0;
> }
>
> /* Set link_standby x link_off defaults */
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> /* HSW and BDW require workarounds that we don't implement. */
> dev_priv->psr.link_standby = false;
> else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index ed1faf14f777..77ef03cb6163 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -288,7 +288,6 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv,
> static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
> - struct drm_device *dev = &dev_priv->drm;
>
> /*
> * After we re-enable the power well, if we touch VGA register 0x3d5
> @@ -304,7 +303,7 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
> outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
> vga_put(pdev, VGA_RSRC_LEGACY_IO);
>
> - if (IS_BROADWELL(dev))
> + if (IS_BROADWELL(dev_priv))
> gen8_irq_power_well_post_enable(dev_priv,
> 1 << PIPE_C | 1 << PIPE_B);
> }
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index d0f798ce6bb2..fefd3034aead 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -542,12 +542,12 @@ ivb_update_plane(struct drm_plane *plane,
> if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
> sprctl |= SPRITE_TILED;
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
> else
> sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
>
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> sprctl |= SPRITE_PIPE_CSC_ENABLE;
>
> /* Sizes are 0 based */
> @@ -566,7 +566,7 @@ ivb_update_plane(struct drm_plane *plane,
> sprctl |= SPRITE_ROTATE_180;
>
> /* HSW and BDW does this automagically in hardware */
> - if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
> + if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
> x += src_w;
> y += src_h;
> }
> @@ -590,7 +590,7 @@ ivb_update_plane(struct drm_plane *plane,
>
> /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
> * register */
> - if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
> else if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
> I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 10/19] drm/i915: Make IS_HASWELL only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (8 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 09/19] drm/i915: Make IS_BROADWELL " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 10:52 ` David Weinehall
2016-10-11 13:21 ` [PATCH 11/19] drm/i915: Make IS_KABYLAKE " Tvrtko Ursulin
` (10 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 2432 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/i915_irq.c | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
drivers/gpu/drm/i915/intel_color.c | 4 ++--
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 23 ++++++++++-------------
drivers/gpu/drm/i915/intel_psr.c | 6 +++---
9 files changed, 24 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 13e409554fcc..d6c3a4bb29aa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2661,7 +2661,7 @@ struct drm_i915_cmd_table {
INTEL_DEVID(dev_priv) == 0x015a)
#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
-#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
+#define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index aefb88f987b2..8c362899674a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4360,7 +4360,7 @@ i915_gem_init_hw(struct drm_device *dev)
if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev_priv))
I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0f8f073c589c..3246d51c7b8e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1746,7 +1746,7 @@ static void gen7_ppgtt_enable(struct drm_device *dev)
I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
ecochk = I915_READ(GAM_ECOCHK);
- if (IS_HASWELL(dev)) {
+ if (IS_HASWELL(dev_priv)) {
ecochk |= ECOCHK_PPGTT_WB_HSW;
} else {
ecochk |= ECOCHK_PPGTT_LLC_IVB;
@@ -2058,7 +2058,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->base.pte_encode = ggtt->base.pte_encode;
if (intel_vgpu_active(dev_priv) || IS_GEN6(dev))
ppgtt->switch_mm = gen6_mm_switch;
- else if (IS_HASWELL(dev))
+ else if (IS_HASWELL(dev_priv))
ppgtt->switch_mm = hsw_mm_switch;
else if (IS_GEN7(dev))
ppgtt->switch_mm = gen7_mm_switch;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5fb3b1c9a52c..47337aabc326 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3594,8 +3594,8 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
dev_priv->gt_irq_mask = ~0;
if (HAS_L3_DPF(dev)) {
/* L3 parity interrupt is always unmasked. */
- dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
- gt_irqs |= GT_PARITY_ERROR(dev);
+ dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
+ gt_irqs |= GT_PARITY_ERROR(dev_priv);
}
gt_irqs |= GT_RENDER_USER_INTERRUPT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index acc767a52d8e..8b61669af628 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2094,9 +2094,9 @@ enum skl_disp_power_wells {
#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
-#define GT_PARITY_ERROR(dev) \
+#define GT_PARITY_ERROR(dev_priv) \
(GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
- (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
+ (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
/* These are all the "old" interrupts */
#define ILK_BSD_USER_INTERRUPT (1<<5)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index be76ef88678c..da76a799411a 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -326,7 +326,7 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
* Workaround : Do not read or write the pipe palette/gamma data while
* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
*/
- if (IS_HASWELL(dev) && intel_crtc_state->ips_enabled &&
+ if (IS_HASWELL(dev_priv) && intel_crtc_state->ips_enabled &&
(intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
hsw_disable_ips(intel_crtc);
reenable_ips = true;
@@ -537,7 +537,7 @@ void intel_color_init(struct drm_crtc *crtc)
if (IS_CHERRYVIEW(dev)) {
dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
dev_priv->display.load_luts = cherryview_load_luts;
- } else if (IS_HASWELL(dev)) {
+ } else if (IS_HASWELL(dev_priv)) {
dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
dev_priv->display.load_luts = haswell_load_luts;
} else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 35f0b7c9d0a6..cd7128b89b4d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1189,7 +1189,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
* eDP when not using the panel fitter, and when not
* using motion blur mitigation (which we don't
* support). */
- if (IS_HASWELL(dev) &&
+ if (IS_HASWELL(dev_priv) &&
(intel_crtc->config->pch_pfit.enabled ||
intel_crtc->config->pch_pfit.force_thru))
temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d159a315099f..08f6cd2fd600 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5503,7 +5503,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
/* If we change the relative order between pipe/planes enabling, we need
* to change the workaround. */
hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
- if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
+ if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
intel_wait_for_vblank(dev, hsw_workaround_pipe);
intel_wait_for_vblank(dev, hsw_workaround_pipe);
}
@@ -8301,7 +8301,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
* programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
* documented on the DDI_FUNC_CTL register description, EDP Input Select
* bits. */
- if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
+ if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
(pipe == PIPE_B || pipe == PIPE_C))
I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
@@ -10028,7 +10028,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
"CPU PWM1 enabled\n");
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev_priv))
I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
"CPU PWM2 enabled\n");
I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
@@ -10048,9 +10048,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
{
- struct drm_device *dev = &dev_priv->drm;
-
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev_priv))
return I915_READ(D_COMP_HSW);
else
return I915_READ(D_COMP_BDW);
@@ -10058,9 +10056,7 @@ static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
{
- struct drm_device *dev = &dev_priv->drm;
-
- if (IS_HASWELL(dev)) {
+ if (IS_HASWELL(dev_priv)) {
mutex_lock(&dev_priv->rps.hw_lock);
if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
val))
@@ -10737,7 +10733,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
ironlake_get_pfit_config(crtc, pipe_config);
}
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev_priv))
pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
(I915_READ(IPS_CTL) & IPS_ENABLE);
@@ -13197,6 +13193,7 @@ intel_pipe_config_compare(struct drm_device *dev,
struct intel_crtc_state *pipe_config,
bool adjust)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
bool ret = true;
#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
@@ -13342,7 +13339,7 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_I(pixel_multiplier);
PIPE_CONF_CHECK_I(has_hdmi_sink);
- if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
+ if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
PIPE_CONF_CHECK_I(limited_color_range);
PIPE_CONF_CHECK_I(has_infoframe);
@@ -13383,7 +13380,7 @@ intel_pipe_config_compare(struct drm_device *dev,
}
/* BDW+ don't expose a synchronous way to read the state */
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev_priv))
PIPE_CONF_CHECK_I(ips_enabled);
PIPE_CONF_CHECK_I(double_wide);
@@ -17262,7 +17259,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
err_printf(m, " SIZE: %08x\n", error->plane[i].size);
err_printf(m, " POS: %08x\n", error->plane[i].pos);
}
- if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
+ if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
if (INTEL_INFO(dev)->gen >= 4) {
err_printf(m, " SURF: %08x\n", error->plane[i].surface);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index d0667f9d9178..4a973b34348a 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -268,7 +268,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
- if (IS_HASWELL(dev))
+ if (IS_HASWELL(dev_priv))
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
if (dev_priv->psr.link_standby)
@@ -360,14 +360,14 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
return false;
}
- if (IS_HASWELL(dev) &&
+ if (IS_HASWELL(dev_priv) &&
I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
S3D_ENABLE) {
DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
return false;
}
- if (IS_HASWELL(dev) &&
+ if (IS_HASWELL(dev_priv) &&
adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
return false;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 10/19] drm/i915: Make IS_HASWELL only take dev_priv
2016-10-11 13:21 ` [PATCH 10/19] drm/i915: Make IS_HASWELL " Tvrtko Ursulin
@ 2016-10-12 10:52 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 10:52 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:43PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 2432 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
> drivers/gpu/drm/i915/i915_irq.c | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> drivers/gpu/drm/i915/intel_color.c | 4 ++--
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 23 ++++++++++-------------
> drivers/gpu/drm/i915/intel_psr.c | 6 +++---
> 9 files changed, 24 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 13e409554fcc..d6c3a4bb29aa 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2661,7 +2661,7 @@ struct drm_i915_cmd_table {
> INTEL_DEVID(dev_priv) == 0x015a)
> #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
> #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
> -#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
> +#define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
> #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
> #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index aefb88f987b2..8c362899674a 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4360,7 +4360,7 @@ i915_gem_init_hw(struct drm_device *dev)
> if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
> I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
>
> - if (IS_HASWELL(dev))
> + if (IS_HASWELL(dev_priv))
> I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
> LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 0f8f073c589c..3246d51c7b8e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1746,7 +1746,7 @@ static void gen7_ppgtt_enable(struct drm_device *dev)
> I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
>
> ecochk = I915_READ(GAM_ECOCHK);
> - if (IS_HASWELL(dev)) {
> + if (IS_HASWELL(dev_priv)) {
> ecochk |= ECOCHK_PPGTT_WB_HSW;
> } else {
> ecochk |= ECOCHK_PPGTT_LLC_IVB;
> @@ -2058,7 +2058,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
> ppgtt->base.pte_encode = ggtt->base.pte_encode;
> if (intel_vgpu_active(dev_priv) || IS_GEN6(dev))
> ppgtt->switch_mm = gen6_mm_switch;
> - else if (IS_HASWELL(dev))
> + else if (IS_HASWELL(dev_priv))
> ppgtt->switch_mm = hsw_mm_switch;
> else if (IS_GEN7(dev))
> ppgtt->switch_mm = gen7_mm_switch;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 5fb3b1c9a52c..47337aabc326 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3594,8 +3594,8 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
> dev_priv->gt_irq_mask = ~0;
> if (HAS_L3_DPF(dev)) {
> /* L3 parity interrupt is always unmasked. */
> - dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
> - gt_irqs |= GT_PARITY_ERROR(dev);
> + dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
> + gt_irqs |= GT_PARITY_ERROR(dev_priv);
> }
>
> gt_irqs |= GT_RENDER_USER_INTERRUPT;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index acc767a52d8e..8b61669af628 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2094,9 +2094,9 @@ enum skl_disp_power_wells {
> #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
> #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
>
> -#define GT_PARITY_ERROR(dev) \
> +#define GT_PARITY_ERROR(dev_priv) \
> (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
> - (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
> + (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
>
> /* These are all the "old" interrupts */
> #define ILK_BSD_USER_INTERRUPT (1<<5)
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index be76ef88678c..da76a799411a 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -326,7 +326,7 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
> * Workaround : Do not read or write the pipe palette/gamma data while
> * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
> */
> - if (IS_HASWELL(dev) && intel_crtc_state->ips_enabled &&
> + if (IS_HASWELL(dev_priv) && intel_crtc_state->ips_enabled &&
> (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
> hsw_disable_ips(intel_crtc);
> reenable_ips = true;
> @@ -537,7 +537,7 @@ void intel_color_init(struct drm_crtc *crtc)
> if (IS_CHERRYVIEW(dev)) {
> dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
> dev_priv->display.load_luts = cherryview_load_luts;
> - } else if (IS_HASWELL(dev)) {
> + } else if (IS_HASWELL(dev_priv)) {
> dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
> dev_priv->display.load_luts = haswell_load_luts;
> } else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 35f0b7c9d0a6..cd7128b89b4d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1189,7 +1189,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
> * eDP when not using the panel fitter, and when not
> * using motion blur mitigation (which we don't
> * support). */
> - if (IS_HASWELL(dev) &&
> + if (IS_HASWELL(dev_priv) &&
> (intel_crtc->config->pch_pfit.enabled ||
> intel_crtc->config->pch_pfit.force_thru))
> temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d159a315099f..08f6cd2fd600 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5503,7 +5503,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> /* If we change the relative order between pipe/planes enabling, we need
> * to change the workaround. */
> hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
> - if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
> + if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
> intel_wait_for_vblank(dev, hsw_workaround_pipe);
> intel_wait_for_vblank(dev, hsw_workaround_pipe);
> }
> @@ -8301,7 +8301,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
> * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
> * documented on the DDI_FUNC_CTL register description, EDP Input Select
> * bits. */
> - if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
> + if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
> (pipe == PIPE_B || pipe == PIPE_C))
> I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
>
> @@ -10028,7 +10028,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
> I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
> I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
> "CPU PWM1 enabled\n");
> - if (IS_HASWELL(dev))
> + if (IS_HASWELL(dev_priv))
> I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
> "CPU PWM2 enabled\n");
> I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
> @@ -10048,9 +10048,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
>
> static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
> {
> - struct drm_device *dev = &dev_priv->drm;
> -
> - if (IS_HASWELL(dev))
> + if (IS_HASWELL(dev_priv))
> return I915_READ(D_COMP_HSW);
> else
> return I915_READ(D_COMP_BDW);
> @@ -10058,9 +10056,7 @@ static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
>
> static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
> {
> - struct drm_device *dev = &dev_priv->drm;
> -
> - if (IS_HASWELL(dev)) {
> + if (IS_HASWELL(dev_priv)) {
> mutex_lock(&dev_priv->rps.hw_lock);
> if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
> val))
> @@ -10737,7 +10733,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> ironlake_get_pfit_config(crtc, pipe_config);
> }
>
> - if (IS_HASWELL(dev))
> + if (IS_HASWELL(dev_priv))
> pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
> (I915_READ(IPS_CTL) & IPS_ENABLE);
>
> @@ -13197,6 +13193,7 @@ intel_pipe_config_compare(struct drm_device *dev,
> struct intel_crtc_state *pipe_config,
> bool adjust)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> bool ret = true;
>
> #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
> @@ -13342,7 +13339,7 @@ intel_pipe_config_compare(struct drm_device *dev,
>
> PIPE_CONF_CHECK_I(pixel_multiplier);
> PIPE_CONF_CHECK_I(has_hdmi_sink);
> - if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
> + if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
> IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> PIPE_CONF_CHECK_I(limited_color_range);
> PIPE_CONF_CHECK_I(has_infoframe);
> @@ -13383,7 +13380,7 @@ intel_pipe_config_compare(struct drm_device *dev,
> }
>
> /* BDW+ don't expose a synchronous way to read the state */
> - if (IS_HASWELL(dev))
> + if (IS_HASWELL(dev_priv))
> PIPE_CONF_CHECK_I(ips_enabled);
>
> PIPE_CONF_CHECK_I(double_wide);
> @@ -17262,7 +17259,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
> err_printf(m, " SIZE: %08x\n", error->plane[i].size);
> err_printf(m, " POS: %08x\n", error->plane[i].pos);
> }
> - if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
> + if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
> err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
> if (INTEL_INFO(dev)->gen >= 4) {
> err_printf(m, " SURF: %08x\n", error->plane[i].surface);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index d0667f9d9178..4a973b34348a 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -268,7 +268,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> - if (IS_HASWELL(dev))
> + if (IS_HASWELL(dev_priv))
> val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>
> if (dev_priv->psr.link_standby)
> @@ -360,14 +360,14 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> return false;
> }
>
> - if (IS_HASWELL(dev) &&
> + if (IS_HASWELL(dev_priv) &&
> I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
> S3D_ENABLE) {
> DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
> return false;
> }
>
> - if (IS_HASWELL(dev) &&
> + if (IS_HASWELL(dev_priv) &&
> adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
> return false;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 11/19] drm/i915: Make IS_KABYLAKE only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (9 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 10/19] drm/i915: Make IS_HASWELL " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 11:42 ` David Weinehall
2016-10-11 13:21 ` [PATCH 12/19] drm/i915: Make IS_SKYLAKE " Tvrtko Ursulin
` (9 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 1320 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 10 +++++-----
drivers/gpu/drm/i915/i915_drv.h | 6 +++---
drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++--------
drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
8 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8899835fffab..d854ea4a7e92 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -203,17 +203,17 @@ static void intel_detect_pch(struct drm_device *dev)
} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
- WARN_ON(!IS_SKYLAKE(dev) &&
- !IS_KABYLAKE(dev));
+ WARN_ON(!IS_SKYLAKE(dev_priv) &&
+ !IS_KABYLAKE(dev_priv));
} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_SPT;
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
- WARN_ON(!IS_SKYLAKE(dev) &&
- !IS_KABYLAKE(dev));
+ WARN_ON(!IS_SKYLAKE(dev_priv) &&
+ !IS_KABYLAKE(dev_priv));
} else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_KBP;
DRM_DEBUG_KMS("Found KabyPoint PCH\n");
- WARN_ON(!IS_KABYLAKE(dev));
+ WARN_ON(!IS_KABYLAKE(dev_priv));
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
(id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d6c3a4bb29aa..3c72ed08a5d2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2665,7 +2665,7 @@ struct drm_i915_cmd_table {
#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
-#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
+#define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
@@ -2732,8 +2732,8 @@ struct drm_i915_cmd_table {
#define KBL_REVID_D0 0x3
#define KBL_REVID_E0 0x4
-#define IS_KBL_REVID(p, since, until) \
- (IS_KABYLAKE(p) && IS_REVID(p, since, until))
+#define IS_KBL_REVID(dev_priv, since, until) \
+ (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
/*
* The genX designation typically refers to the render engine, so render
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index cbea6fb83ce5..3508120b8c90 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -456,7 +456,7 @@ int i915_gem_init_stolen(struct drm_device *dev)
break;
default:
if (IS_BROADWELL(dev_priv) ||
- IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev))
+ IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
bdw_get_stolen_reserved(dev_priv, &reserved_base,
&reserved_size);
else
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cd7128b89b4d..07164e250adf 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1020,13 +1020,13 @@ static void bxt_ddi_clock_get(struct intel_encoder *encoder,
void intel_ddi_clock_get(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (INTEL_INFO(dev)->gen <= 8)
+ if (INTEL_GEN(dev_priv) <= 8)
hsw_ddi_clock_get(encoder, pipe_config);
- else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+ else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skl_ddi_clock_get(encoder, pipe_config);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
bxt_ddi_clock_get(encoder, pipe_config);
}
@@ -1081,14 +1081,14 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = intel_crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
struct intel_encoder *intel_encoder =
intel_ddi_get_crtc_new_encoder(crtc_state);
- if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
return skl_ddi_pll_select(intel_crtc, crtc_state,
intel_encoder);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
return bxt_ddi_pll_select(intel_crtc, crtc_state,
intel_encoder);
else
@@ -1742,7 +1742,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
intel_edp_panel_off(intel_dp);
}
- if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
DPLL_CTRL2_DDI_CLK_OFF(port)));
else if (INTEL_INFO(dev)->gen < 9)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 08f6cd2fd600..e673a803f213 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5830,7 +5830,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
int max_cdclk, vco;
@@ -10648,7 +10648,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
- if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skylake_get_ddi_pll(dev_priv, port, pipe_config);
else if (IS_BROXTON(dev))
bxt_get_ddi_pll(dev_priv, port, pipe_config);
@@ -12823,7 +12823,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
pipe_config->dpll_hw_state.pll9,
pipe_config->dpll_hw_state.pll10,
pipe_config->dpll_hw_state.pcsdw12);
- } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
DRM_DEBUG_KMS("dpll_hw_state: "
"ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
pipe_config->dpll_hw_state.ctrl1,
@@ -15422,7 +15422,7 @@ static void intel_setup_outputs(struct drm_device *dev)
*/
found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
/* WaIgnoreDDIAStrap: skl */
- if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+ if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
intel_ddi_init(dev, PORT_A);
/* DDI B, C and D detection is indicated by the SFUSE_STRAP
@@ -15438,7 +15438,7 @@ static void intel_setup_outputs(struct drm_device *dev)
/*
* On SKL we don't have a way to detect DDI-E so we rely on VBT.
*/
- if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
+ if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
(dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index c37ce1263142..7cf9d91c0746 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1851,7 +1851,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
const struct dpll_info *dpll_info;
int i;
- if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
dpll_mgr = &skl_pll_mgr;
else if (IS_BROXTON(dev))
dpll_mgr = &bxt_pll_mgr;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 7ace96be82a8..3c46605b58e7 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -734,7 +734,7 @@ void intel_guc_init(struct drm_device *dev)
fw_path = I915_BXT_GUC_UCODE;
guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
- } else if (IS_KABYLAKE(dev)) {
+ } else if (IS_KABYLAKE(dev_priv)) {
fw_path = I915_KBL_GUC_UCODE;
guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 77ef03cb6163..025fbd522819 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2594,7 +2594,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
power_domains->initializing = true;
- if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
skl_display_core_init(dev_priv, resume);
} else if (IS_BROXTON(dev)) {
bxt_display_core_init(dev_priv, resume);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 11/19] drm/i915: Make IS_KABYLAKE only take dev_priv
2016-10-11 13:21 ` [PATCH 11/19] drm/i915: Make IS_KABYLAKE " Tvrtko Ursulin
@ 2016-10-12 11:42 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 11:42 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:44PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 1320 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 10 +++++-----
> drivers/gpu/drm/i915/i915_drv.h | 6 +++---
> drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++--------
> drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> 8 files changed, 25 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 8899835fffab..d854ea4a7e92 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -203,17 +203,17 @@ static void intel_detect_pch(struct drm_device *dev)
> } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_SPT;
> DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
> - WARN_ON(!IS_SKYLAKE(dev) &&
> - !IS_KABYLAKE(dev));
> + WARN_ON(!IS_SKYLAKE(dev_priv) &&
> + !IS_KABYLAKE(dev_priv));
> } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_SPT;
> DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
> - WARN_ON(!IS_SKYLAKE(dev) &&
> - !IS_KABYLAKE(dev));
> + WARN_ON(!IS_SKYLAKE(dev_priv) &&
> + !IS_KABYLAKE(dev_priv));
> } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_KBP;
> DRM_DEBUG_KMS("Found KabyPoint PCH\n");
> - WARN_ON(!IS_KABYLAKE(dev));
> + WARN_ON(!IS_KABYLAKE(dev_priv));
> } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
> (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
> ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d6c3a4bb29aa..3c72ed08a5d2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2665,7 +2665,7 @@ struct drm_i915_cmd_table {
> #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
> #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
> -#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
> +#define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
> #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> @@ -2732,8 +2732,8 @@ struct drm_i915_cmd_table {
> #define KBL_REVID_D0 0x3
> #define KBL_REVID_E0 0x4
>
> -#define IS_KBL_REVID(p, since, until) \
> - (IS_KABYLAKE(p) && IS_REVID(p, since, until))
> +#define IS_KBL_REVID(dev_priv, since, until) \
> + (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
>
> /*
> * The genX designation typically refers to the render engine, so render
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index cbea6fb83ce5..3508120b8c90 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -456,7 +456,7 @@ int i915_gem_init_stolen(struct drm_device *dev)
> break;
> default:
> if (IS_BROADWELL(dev_priv) ||
> - IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev))
> + IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> bdw_get_stolen_reserved(dev_priv, &reserved_base,
> &reserved_size);
> else
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cd7128b89b4d..07164e250adf 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1020,13 +1020,13 @@ static void bxt_ddi_clock_get(struct intel_encoder *encoder,
> void intel_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (INTEL_INFO(dev)->gen <= 8)
> + if (INTEL_GEN(dev_priv) <= 8)
> hsw_ddi_clock_get(encoder, pipe_config);
> - else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> + else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skl_ddi_clock_get(encoder, pipe_config);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> bxt_ddi_clock_get(encoder, pipe_config);
> }
>
> @@ -1081,14 +1081,14 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_device *dev = intel_crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> struct intel_encoder *intel_encoder =
> intel_ddi_get_crtc_new_encoder(crtc_state);
>
> - if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> return skl_ddi_pll_select(intel_crtc, crtc_state,
> intel_encoder);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> return bxt_ddi_pll_select(intel_crtc, crtc_state,
> intel_encoder);
> else
> @@ -1742,7 +1742,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
> intel_edp_panel_off(intel_dp);
> }
>
> - if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
> DPLL_CTRL2_DDI_CLK_OFF(port)));
> else if (INTEL_INFO(dev)->gen < 9)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 08f6cd2fd600..e673a803f213 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5830,7 +5830,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> int max_cdclk, vco;
>
> @@ -10648,7 +10648,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>
> port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
>
> - if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skylake_get_ddi_pll(dev_priv, port, pipe_config);
> else if (IS_BROXTON(dev))
> bxt_get_ddi_pll(dev_priv, port, pipe_config);
> @@ -12823,7 +12823,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> pipe_config->dpll_hw_state.pll9,
> pipe_config->dpll_hw_state.pll10,
> pipe_config->dpll_hw_state.pcsdw12);
> - } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> DRM_DEBUG_KMS("dpll_hw_state: "
> "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
> pipe_config->dpll_hw_state.ctrl1,
> @@ -15422,7 +15422,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> */
> found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
> /* WaIgnoreDDIAStrap: skl */
> - if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> + if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> intel_ddi_init(dev, PORT_A);
>
> /* DDI B, C and D detection is indicated by the SFUSE_STRAP
> @@ -15438,7 +15438,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> /*
> * On SKL we don't have a way to detect DDI-E so we rely on VBT.
> */
> - if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
> + if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
> dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
> dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index c37ce1263142..7cf9d91c0746 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1851,7 +1851,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> const struct dpll_info *dpll_info;
> int i;
>
> - if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> dpll_mgr = &skl_pll_mgr;
> else if (IS_BROXTON(dev))
> dpll_mgr = &bxt_pll_mgr;
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 7ace96be82a8..3c46605b58e7 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -734,7 +734,7 @@ void intel_guc_init(struct drm_device *dev)
> fw_path = I915_BXT_GUC_UCODE;
> guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
> guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
> - } else if (IS_KABYLAKE(dev)) {
> + } else if (IS_KABYLAKE(dev_priv)) {
> fw_path = I915_KBL_GUC_UCODE;
> guc_fw->guc_fw_major_wanted = KBL_FW_MAJOR;
> guc_fw->guc_fw_minor_wanted = KBL_FW_MINOR;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 77ef03cb6163..025fbd522819 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2594,7 +2594,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
>
> power_domains->initializing = true;
>
> - if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
> + if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> skl_display_core_init(dev_priv, resume);
> } else if (IS_BROXTON(dev)) {
> bxt_display_core_init(dev_priv, resume);
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 12/19] drm/i915: Make IS_SKYLAKE only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (10 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 11/19] drm/i915: Make IS_KABYLAKE " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 10:46 ` David Weinehall
2016-10-11 13:21 ` [PATCH 13/19] drm/i915: Make IS_BROXTON " Tvrtko Ursulin
` (8 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 1016 bytes of .rodata strings and couple hundred of .text.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3c72ed08a5d2..9784e61400e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2663,7 +2663,7 @@ struct drm_i915_cmd_table {
#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
#define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
-#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
+#define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
#define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 3246d51c7b8e..cf43a5632961 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2133,7 +2133,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
else if (IS_CHERRYVIEW(dev))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
- else if (IS_SKYLAKE(dev))
+ else if (IS_SKYLAKE(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
else if (IS_BROXTON(dev))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 3c46605b58e7..182204373931 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -726,7 +726,7 @@ void intel_guc_init(struct drm_device *dev)
if (!HAS_GUC_UCODE(dev)) {
fw_path = NULL;
- } else if (IS_SKYLAKE(dev)) {
+ } else if (IS_SKYLAKE(dev_priv)) {
fw_path = I915_SKL_GUC_UCODE;
guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 12/19] drm/i915: Make IS_SKYLAKE only take dev_priv
2016-10-11 13:21 ` [PATCH 12/19] drm/i915: Make IS_SKYLAKE " Tvrtko Ursulin
@ 2016-10-12 10:46 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 10:46 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:45PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 1016 bytes of .rodata strings and couple hundred of .text.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3c72ed08a5d2..9784e61400e5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2663,7 +2663,7 @@ struct drm_i915_cmd_table {
> #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
> #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
> #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> -#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
> +#define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
> #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
> #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
> #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 3246d51c7b8e..cf43a5632961 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2133,7 +2133,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
> else if (IS_CHERRYVIEW(dev))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> - else if (IS_SKYLAKE(dev))
> + else if (IS_SKYLAKE(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> else if (IS_BROXTON(dev))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 3c46605b58e7..182204373931 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -726,7 +726,7 @@ void intel_guc_init(struct drm_device *dev)
>
> if (!HAS_GUC_UCODE(dev)) {
> fw_path = NULL;
> - } else if (IS_SKYLAKE(dev)) {
> + } else if (IS_SKYLAKE(dev_priv)) {
> fw_path = I915_SKL_GUC_UCODE;
> guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
> guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 13/19] drm/i915: Make IS_BROXTON only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (11 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 12/19] drm/i915: Make IS_SKYLAKE " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 11:52 ` David Weinehall
2016-10-11 13:21 ` [PATCH 14/19] drm/i915: Make HAS_L3_DPF " Tvrtko Ursulin
` (7 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 1392 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 5 +++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++++++++++++++++----------------
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++-----------
drivers/gpu/drm/i915/intel_dp.c | 16 ++++++-------
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/intel_dsi.c | 27 +++++++++++-----------
drivers/gpu/drm/i915/intel_dsi_pll.c | 26 ++++++++++-----------
drivers/gpu/drm/i915/intel_guc_loader.c | 8 +++----
drivers/gpu/drm/i915/intel_hdmi.c | 6 ++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
13 files changed, 89 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d854ea4a7e92..18af6d1ccec9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2437,7 +2437,7 @@ static int intel_runtime_resume(struct device *kdev)
if (IS_GEN6(dev_priv))
intel_init_pch_refclk(dev);
- if (IS_BROXTON(dev)) {
+ if (IS_BROXTON(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9784e61400e5..ad9299196d13 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2664,7 +2664,7 @@ struct drm_i915_cmd_table {
#define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
#define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
-#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
+#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
#define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
@@ -2724,7 +2724,8 @@ struct drm_i915_cmd_table {
#define BXT_REVID_B0 0x3
#define BXT_REVID_C0 0x9
-#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
+#define IS_BXT_REVID(dev_priv, since, until) \
+ (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
#define KBL_REVID_A0 0x0
#define KBL_REVID_B0 0x1
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index cf43a5632961..e628691fe97e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p)
/* We use the flushing unmap only with ppgtt structures:
* page directories, page tables and scratch pages.
*/
-static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
+static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
{
/* There are only few exceptions for gen >=6. chv and bxt.
* And we are not sure about the latter so play safe for now.
*/
- if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
+ if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
drm_clflush_virt_range(vaddr, PAGE_SIZE);
kunmap_atomic(vaddr);
}
#define kmap_px(px) kmap_page_dma(px_base(px))
-#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
+#define kunmap_px(ppgtt, vaddr) \
+ kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr))
#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
-#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
-#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
+#define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v))
+#define fill32_px(dev_priv, px, v) \
+ fill_page_dma_32((dev_priv), px_base(px), (v))
-static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
- const uint64_t val)
+static void fill_page_dma(struct drm_i915_private *dev_priv,
+ struct i915_page_dma *p, const uint64_t val)
{
int i;
uint64_t * const vaddr = kmap_page_dma(p);
@@ -401,17 +403,17 @@ static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
for (i = 0; i < 512; i++)
vaddr[i] = val;
- kunmap_page_dma(dev, vaddr);
+ kunmap_page_dma(dev_priv, vaddr);
}
-static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
- const uint32_t val32)
+static void fill_page_dma_32(struct drm_i915_private *dev_priv,
+ struct i915_page_dma *p, const uint32_t val32)
{
uint64_t v = val32;
v = v << 32 | val32;
- fill_page_dma(dev, p, v);
+ fill_page_dma(dev_priv, p, v);
}
static int
@@ -474,7 +476,7 @@ static void gen8_initialize_pt(struct i915_address_space *vm,
scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
I915_CACHE_LLC, true);
- fill_px(vm->dev, pt, scratch_pte);
+ fill_px(to_i915(vm->dev), pt, scratch_pte);
}
static void gen6_initialize_pt(struct i915_address_space *vm,
@@ -487,7 +489,7 @@ static void gen6_initialize_pt(struct i915_address_space *vm,
scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
I915_CACHE_LLC, true, 0);
- fill32_px(vm->dev, pt, scratch_pte);
+ fill32_px(to_i915(vm->dev), pt, scratch_pte);
}
static struct i915_page_directory *alloc_pd(struct drm_device *dev)
@@ -534,7 +536,7 @@ static void gen8_initialize_pd(struct i915_address_space *vm,
scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
- fill_px(vm->dev, pd, scratch_pde);
+ fill_px(to_i915(vm->dev), pd, scratch_pde);
}
static int __pdp_init(struct drm_device *dev,
@@ -615,7 +617,7 @@ static void gen8_initialize_pdp(struct i915_address_space *vm,
scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
- fill_px(vm->dev, pdp, scratch_pdpe);
+ fill_px(to_i915(vm->dev), pdp, scratch_pdpe);
}
static void gen8_initialize_pml4(struct i915_address_space *vm,
@@ -626,7 +628,7 @@ static void gen8_initialize_pml4(struct i915_address_space *vm,
scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
I915_CACHE_LLC);
- fill_px(vm->dev, pml4, scratch_pml4e);
+ fill_px(to_i915(vm->dev), pml4, scratch_pml4e);
}
static void
@@ -2135,7 +2137,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
else if (IS_SKYLAKE(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
}
@@ -2895,7 +2897,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
* resort to an uncached mapping. The WC issue is easily caught by the
* readback check when writing GTT PTE entries.
*/
- if (IS_BROXTON(ggtt->base.dev))
+ if (IS_BROXTON(to_i915(ggtt->base.dev)))
ggtt->gsm = ioremap_nocache(phys_addr, size);
else
ggtt->gsm = ioremap_wc(phys_addr, size);
@@ -3267,7 +3269,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
ggtt->base.closed = false;
if (INTEL_INFO(dev)->gen >= 8) {
- if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
+ if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
chv_setup_private_ppat(dev_priv);
else
bdw_setup_private_ppat(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 47337aabc326..75f4ba935ebc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4597,7 +4597,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->irq_uninstall = gen8_irq_uninstall;
dev->driver->enable_vblank = gen8_enable_vblank;
dev->driver->disable_vblank = gen8_disable_vblank;
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 07164e250adf..a76afd7a6616 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2509,7 +2509,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
* configuration so that we use the proper lane count for our
* calculations.
*/
- if (IS_BROXTON(dev) && port == PORT_A) {
+ if (IS_BROXTON(dev_priv) && port == PORT_A) {
if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
@@ -2533,7 +2533,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
* On BXT A0/A1, sw needs to activate DDIA HPD logic and
* interrupts to check the external panel connection.
*/
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) && port == PORT_B)
dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
else
dev_priv->hotplug.irq_port[port] = intel_dig_port;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e673a803f213..636e5572b996 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -600,7 +600,7 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
* the given connectors.
*/
-static bool intel_PLL_is_valid(struct drm_device *dev,
+static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
const struct intel_limit *limit,
const struct dpll *clock)
{
@@ -613,12 +613,13 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
INTELPllInvalid("m1 out of range\n");
- if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
- !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
+ if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
+ !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
if (clock->m1 <= clock->m2)
INTELPllInvalid("m1 <= m2\n");
- if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
+ if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
+ !IS_BROXTON(dev_priv)) {
if (clock->p < limit->p.min || limit->p.max < clock->p)
INTELPllInvalid("p out of range\n");
if (clock->m < limit->m.min || limit->m.max < clock->m)
@@ -698,7 +699,8 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
int this_err;
i9xx_calc_dpll_params(refclk, &clock);
- if (!intel_PLL_is_valid(dev, limit,
+ if (!intel_PLL_is_valid(to_i915(dev),
+ limit,
&clock))
continue;
if (match_clock &&
@@ -753,7 +755,8 @@ pnv_find_best_dpll(const struct intel_limit *limit,
int this_err;
pnv_calc_dpll_params(refclk, &clock);
- if (!intel_PLL_is_valid(dev, limit,
+ if (!intel_PLL_is_valid(to_i915(dev),
+ limit,
&clock))
continue;
if (match_clock &&
@@ -813,7 +816,8 @@ g4x_find_best_dpll(const struct intel_limit *limit,
int this_err;
i9xx_calc_dpll_params(refclk, &clock);
- if (!intel_PLL_is_valid(dev, limit,
+ if (!intel_PLL_is_valid(to_i915(dev),
+ limit,
&clock))
continue;
@@ -909,7 +913,8 @@ vlv_find_best_dpll(const struct intel_limit *limit,
vlv_calc_dpll_params(refclk, &clock);
- if (!intel_PLL_is_valid(dev, limit,
+ if (!intel_PLL_is_valid(to_i915(dev),
+ limit,
&clock))
continue;
@@ -977,7 +982,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
chv_calc_dpll_params(refclk, &clock);
- if (!intel_PLL_is_valid(dev, limit, &clock))
+ if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
continue;
if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
@@ -5852,7 +5857,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
max_cdclk = 308571;
dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
- } else if (IS_BROXTON(dev)) {
+ } else if (IS_BROXTON(dev_priv)) {
dev_priv->max_cdclk_freq = 624000;
} else if (IS_BROADWELL(dev_priv)) {
/*
@@ -10650,7 +10655,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skylake_get_ddi_pll(dev_priv, port, pipe_config);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
bxt_get_ddi_pll(dev_priv, port, pipe_config);
else
haswell_get_ddi_pll(dev_priv, port, pipe_config);
@@ -12808,7 +12813,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
- if (IS_BROXTON(dev)) {
+ if (IS_BROXTON(dev_priv)) {
DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
"pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
"pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
@@ -15401,7 +15406,7 @@ static void intel_setup_outputs(struct drm_device *dev)
if (intel_crt_present(dev))
intel_crt_init(dev);
- if (IS_BROXTON(dev)) {
+ if (IS_BROXTON(dev_priv)) {
/*
* FIXME: Broxton doesn't support port detection via the
* DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 02e74c467a55..b6c8b25ee1d4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -571,7 +571,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
struct intel_encoder *encoder;
if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
- !IS_BROXTON(dev)))
+ !IS_BROXTON(dev_priv)))
return;
/*
@@ -591,7 +591,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
continue;
intel_dp = enc_to_intel_dp(&encoder->base);
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
intel_dp->pps_reset = true;
else
intel_dp->pps_pipe = INVALID_PIPE;
@@ -2981,7 +2981,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = to_i915(dev);
enum port port = dp_to_dig_port(intel_dp)->port;
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (INTEL_INFO(dev)->gen >= 9) {
if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
@@ -3344,7 +3344,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
if (HAS_DDI(dev_priv)) {
signal_levels = ddi_signal_levels(intel_dp);
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
signal_levels = 0;
else
mask = DDI_BUF_EMP_MASK;
@@ -5072,7 +5072,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
/* Compute the divisor for the pp clock, simply match the Bspec
* formula. */
- if (IS_BROXTON(dev)) {
+ if (IS_BROXTON(dev_priv)) {
pp_div = I915_READ(regs.pp_ctrl);
pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5098,7 +5098,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
I915_WRITE(regs.pp_on, pp_on);
I915_WRITE(regs.pp_off, pp_off);
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
I915_WRITE(regs.pp_ctrl, pp_div);
else
I915_WRITE(regs.pp_div, pp_div);
@@ -5106,7 +5106,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
I915_READ(regs.pp_on),
I915_READ(regs.pp_off),
- IS_BROXTON(dev) ?
+ IS_BROXTON(dev_priv) ?
(I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
I915_READ(regs.pp_div));
}
@@ -5715,7 +5715,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
break;
case PORT_B:
intel_encoder->hpd_pin = HPD_PORT_B;
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
intel_encoder->hpd_pin = HPD_PORT_A;
break;
case PORT_C:
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 7cf9d91c0746..605d0b509f24 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1853,7 +1853,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
dpll_mgr = &skl_pll_mgr;
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
dpll_mgr = &bxt_pll_mgr;
else if (HAS_DDI(dev_priv))
dpll_mgr = &hsw_pll_mgr;
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 5b1e445a80d0..48e8dd108f4f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -437,11 +437,11 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
static void intel_dsi_device_ready(struct intel_encoder *encoder)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_dsi_device_ready(encoder);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
bxt_dsi_device_ready(encoder);
}
@@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
}
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t port_ctrl = IS_BROXTON(dev) ?
+ i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
u32 temp;
@@ -494,7 +494,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
enum port port;
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t port_ctrl = IS_BROXTON(dev) ?
+ i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
u32 temp;
@@ -656,7 +656,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
{
- struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
@@ -664,7 +663,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
for_each_dsi_port(port, intel_dsi->ports) {
/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
- i915_reg_t port_ctrl = IS_BROXTON(dev) ?
+ i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
u32 val;
@@ -762,7 +761,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
/* XXX: this only works for one DSI output */
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t ctrl_reg = IS_BROXTON(dev) ?
+ i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
@@ -970,11 +969,11 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
static void intel_dsi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 pclk;
DRM_DEBUG_KMS("\n");
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
bxt_dsi_get_pipe_config(encoder, pipe_config);
pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
@@ -1066,7 +1065,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
for_each_dsi_port(port, intel_dsi->ports) {
- if (IS_BROXTON(dev)) {
+ if (IS_BROXTON(dev_priv)) {
/*
* Program hdisplay and vdisplay on MIPI transcoder.
* This is different from calculated hactive and
@@ -1153,7 +1152,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
tmp &= ~READ_REQUEST_PRIORITY_MASK;
I915_WRITE(MIPI_CTRL(port), tmp |
READ_REQUEST_PRIORITY_HIGH);
- } else if (IS_BROXTON(dev)) {
+ } else if (IS_BROXTON(dev_priv)) {
enum pipe pipe = intel_crtc->pipe;
tmp = I915_READ(MIPI_CTRL(port));
@@ -1242,7 +1241,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
I915_WRITE(MIPI_INIT_COUNT(port),
txclkesc(intel_dsi->escape_clk_div, 100));
- if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
+ if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
/*
* BXT spec says write MIPI_INIT_COUNT for
* both the ports, even if only one is
@@ -1452,7 +1451,7 @@ void intel_dsi_init(struct drm_device *dev)
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
- } else if (IS_BROXTON(dev)) {
+ } else if (IS_BROXTON(dev_priv)) {
dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
} else {
DRM_ERROR("Unsupported Mipi device to reg base");
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 6ab58a01b18e..56eff6004bc0 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
struct intel_crtc_state *config)
{
- if (IS_BROXTON(encoder->base.dev))
+ if (IS_BROXTON(to_i915(encoder->base.dev)))
return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
else
return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
@@ -515,11 +515,11 @@ bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
int intel_compute_dsi_pll(struct intel_encoder *encoder,
struct intel_crtc_state *config)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return vlv_compute_dsi_pll(encoder, config);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
return bxt_compute_dsi_pll(encoder, config);
return -ENODEV;
@@ -528,21 +528,21 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
void intel_enable_dsi_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *config)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_enable_dsi_pll(encoder, config);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
bxt_enable_dsi_pll(encoder, config);
}
void intel_disable_dsi_pll(struct intel_encoder *encoder)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_disable_dsi_pll(encoder);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
bxt_disable_dsi_pll(encoder);
}
@@ -564,10 +564,10 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
bxt_dsi_reset_clocks(encoder, port);
- else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_dsi_reset_clocks(encoder, port);
}
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 182204373931..5d5d609ed5e9 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -376,16 +376,16 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
/* WaDisableMinuteIaClockGating:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
~GUC_ENABLE_MIA_CLOCK_GATING));
}
/* WaC6DisallowByGfxPause:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_B0))
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
else
I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
@@ -730,7 +730,7 @@ void intel_guc_init(struct drm_device *dev)
fw_path = I915_SKL_GUC_UCODE;
guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
- } else if (IS_BROXTON(dev)) {
+ } else if (IS_BROXTON(dev_priv)) {
fw_path = I915_BXT_GUC_UCODE;
guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6607c4e3c36c..f6562451c47e 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1241,7 +1241,7 @@ static enum drm_mode_status
hdmi_port_clock_valid(struct intel_hdmi *hdmi,
int clock, bool respect_downstream_limits)
{
- struct drm_device *dev = intel_hdmi_to_dev(hdmi);
+ struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
if (clock < 25000)
return MODE_CLOCK_LOW;
@@ -1249,11 +1249,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
return MODE_CLOCK_HIGH;
/* BXT DPLL can't generate 223-240 MHz */
- if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
+ if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
return MODE_CLOCK_RANGE;
/* CHV DPLL can't generate 216-240 MHz */
- if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
+ if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
return MODE_CLOCK_RANGE;
return MODE_OK;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 025fbd522819..e4bb85c9c6e1 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2596,7 +2596,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
skl_display_core_init(dev_priv, resume);
- } else if (IS_BROXTON(dev)) {
+ } else if (IS_BROXTON(dev_priv)) {
bxt_display_core_init(dev_priv, resume);
} else if (IS_CHERRYVIEW(dev)) {
mutex_lock(&power_domains->lock);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 13/19] drm/i915: Make IS_BROXTON only take dev_priv
2016-10-11 13:21 ` [PATCH 13/19] drm/i915: Make IS_BROXTON " Tvrtko Ursulin
@ 2016-10-12 11:52 ` David Weinehall
2016-10-12 12:06 ` Tvrtko Ursulin
0 siblings, 1 reply; 46+ messages in thread
From: David Weinehall @ 2016-10-12 11:52 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:46PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 1392 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
This patch does quite a bit more than just change IS_BROXTON to use
dev_priv...
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 5 +++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++++++++++++++++----------------
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++-----------
> drivers/gpu/drm/i915/intel_dp.c | 16 ++++++-------
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/intel_dsi.c | 27 +++++++++++-----------
> drivers/gpu/drm/i915/intel_dsi_pll.c | 26 ++++++++++-----------
> drivers/gpu/drm/i915/intel_guc_loader.c | 8 +++----
> drivers/gpu/drm/i915/intel_hdmi.c | 6 ++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> 13 files changed, 89 insertions(+), 82 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d854ea4a7e92..18af6d1ccec9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2437,7 +2437,7 @@ static int intel_runtime_resume(struct device *kdev)
> if (IS_GEN6(dev_priv))
> intel_init_pch_refclk(dev);
>
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> bxt_disable_dc9(dev_priv);
> bxt_display_core_init(dev_priv, true);
> if (dev_priv->csr.dmc_payload &&
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9784e61400e5..ad9299196d13 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2664,7 +2664,7 @@ struct drm_i915_cmd_table {
> #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
> #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
> -#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
> +#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
> #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
> #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> @@ -2724,7 +2724,8 @@ struct drm_i915_cmd_table {
> #define BXT_REVID_B0 0x3
> #define BXT_REVID_C0 0x9
>
> -#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
> +#define IS_BXT_REVID(dev_priv, since, until) \
> + (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
>
> #define KBL_REVID_A0 0x0
> #define KBL_REVID_B0 0x1
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index cf43a5632961..e628691fe97e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p)
> /* We use the flushing unmap only with ppgtt structures:
> * page directories, page tables and scratch pages.
> */
> -static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
> +static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
> {
> /* There are only few exceptions for gen >=6. chv and bxt.
> * And we are not sure about the latter so play safe for now.
> */
> - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
> + if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> drm_clflush_virt_range(vaddr, PAGE_SIZE);
>
> kunmap_atomic(vaddr);
> }
>
> #define kmap_px(px) kmap_page_dma(px_base(px))
> -#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
> +#define kunmap_px(ppgtt, vaddr) \
> + kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr))
>
> #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
> #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
> -#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
> -#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
> +#define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v))
> +#define fill32_px(dev_priv, px, v) \
> + fill_page_dma_32((dev_priv), px_base(px), (v))
>
> -static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
> - const uint64_t val)
> +static void fill_page_dma(struct drm_i915_private *dev_priv,
> + struct i915_page_dma *p, const uint64_t val)
> {
> int i;
> uint64_t * const vaddr = kmap_page_dma(p);
> @@ -401,17 +403,17 @@ static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
> for (i = 0; i < 512; i++)
> vaddr[i] = val;
>
> - kunmap_page_dma(dev, vaddr);
> + kunmap_page_dma(dev_priv, vaddr);
> }
>
> -static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
> - const uint32_t val32)
> +static void fill_page_dma_32(struct drm_i915_private *dev_priv,
> + struct i915_page_dma *p, const uint32_t val32)
> {
> uint64_t v = val32;
>
> v = v << 32 | val32;
>
> - fill_page_dma(dev, p, v);
> + fill_page_dma(dev_priv, p, v);
> }
>
> static int
> @@ -474,7 +476,7 @@ static void gen8_initialize_pt(struct i915_address_space *vm,
> scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
> I915_CACHE_LLC, true);
>
> - fill_px(vm->dev, pt, scratch_pte);
> + fill_px(to_i915(vm->dev), pt, scratch_pte);
> }
>
> static void gen6_initialize_pt(struct i915_address_space *vm,
> @@ -487,7 +489,7 @@ static void gen6_initialize_pt(struct i915_address_space *vm,
> scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
> I915_CACHE_LLC, true, 0);
>
> - fill32_px(vm->dev, pt, scratch_pte);
> + fill32_px(to_i915(vm->dev), pt, scratch_pte);
> }
>
> static struct i915_page_directory *alloc_pd(struct drm_device *dev)
> @@ -534,7 +536,7 @@ static void gen8_initialize_pd(struct i915_address_space *vm,
>
> scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
>
> - fill_px(vm->dev, pd, scratch_pde);
> + fill_px(to_i915(vm->dev), pd, scratch_pde);
> }
>
> static int __pdp_init(struct drm_device *dev,
> @@ -615,7 +617,7 @@ static void gen8_initialize_pdp(struct i915_address_space *vm,
>
> scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
>
> - fill_px(vm->dev, pdp, scratch_pdpe);
> + fill_px(to_i915(vm->dev), pdp, scratch_pdpe);
> }
>
> static void gen8_initialize_pml4(struct i915_address_space *vm,
> @@ -626,7 +628,7 @@ static void gen8_initialize_pml4(struct i915_address_space *vm,
> scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
> I915_CACHE_LLC);
>
> - fill_px(vm->dev, pml4, scratch_pml4e);
> + fill_px(to_i915(vm->dev), pml4, scratch_pml4e);
> }
>
> static void
> @@ -2135,7 +2137,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> else if (IS_SKYLAKE(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> }
>
> @@ -2895,7 +2897,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
> * resort to an uncached mapping. The WC issue is easily caught by the
> * readback check when writing GTT PTE entries.
> */
> - if (IS_BROXTON(ggtt->base.dev))
> + if (IS_BROXTON(to_i915(ggtt->base.dev)))
> ggtt->gsm = ioremap_nocache(phys_addr, size);
> else
> ggtt->gsm = ioremap_wc(phys_addr, size);
> @@ -3267,7 +3269,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
> ggtt->base.closed = false;
>
> if (INTEL_INFO(dev)->gen >= 8) {
> - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
> + if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> chv_setup_private_ppat(dev_priv);
> else
> bdw_setup_private_ppat(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 47337aabc326..75f4ba935ebc 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4597,7 +4597,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev->driver->irq_uninstall = gen8_irq_uninstall;
> dev->driver->enable_vblank = gen8_enable_vblank;
> dev->driver->disable_vblank = gen8_disable_vblank;
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
> dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 07164e250adf..a76afd7a6616 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2509,7 +2509,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
> * configuration so that we use the proper lane count for our
> * calculations.
> */
> - if (IS_BROXTON(dev) && port == PORT_A) {
> + if (IS_BROXTON(dev_priv) && port == PORT_A) {
> if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> @@ -2533,7 +2533,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
> * On BXT A0/A1, sw needs to activate DDIA HPD logic and
> * interrupts to check the external panel connection.
> */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) && port == PORT_B)
> dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
> else
> dev_priv->hotplug.irq_port[port] = intel_dig_port;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e673a803f213..636e5572b996 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -600,7 +600,7 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
> * the given connectors.
> */
>
> -static bool intel_PLL_is_valid(struct drm_device *dev,
> +static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
> const struct intel_limit *limit,
> const struct dpll *clock)
> {
> @@ -613,12 +613,13 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
> if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
> INTELPllInvalid("m1 out of range\n");
>
> - if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
> - !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
> + if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> + !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
> if (clock->m1 <= clock->m2)
> INTELPllInvalid("m1 <= m2\n");
>
> - if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
> + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> + !IS_BROXTON(dev_priv)) {
> if (clock->p < limit->p.min || limit->p.max < clock->p)
> INTELPllInvalid("p out of range\n");
> if (clock->m < limit->m.min || limit->m.max < clock->m)
> @@ -698,7 +699,8 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
> int this_err;
>
> i9xx_calc_dpll_params(refclk, &clock);
> - if (!intel_PLL_is_valid(dev, limit,
> + if (!intel_PLL_is_valid(to_i915(dev),
> + limit,
> &clock))
> continue;
> if (match_clock &&
> @@ -753,7 +755,8 @@ pnv_find_best_dpll(const struct intel_limit *limit,
> int this_err;
>
> pnv_calc_dpll_params(refclk, &clock);
> - if (!intel_PLL_is_valid(dev, limit,
> + if (!intel_PLL_is_valid(to_i915(dev),
> + limit,
> &clock))
> continue;
> if (match_clock &&
> @@ -813,7 +816,8 @@ g4x_find_best_dpll(const struct intel_limit *limit,
> int this_err;
>
> i9xx_calc_dpll_params(refclk, &clock);
> - if (!intel_PLL_is_valid(dev, limit,
> + if (!intel_PLL_is_valid(to_i915(dev),
> + limit,
> &clock))
> continue;
>
> @@ -909,7 +913,8 @@ vlv_find_best_dpll(const struct intel_limit *limit,
>
> vlv_calc_dpll_params(refclk, &clock);
>
> - if (!intel_PLL_is_valid(dev, limit,
> + if (!intel_PLL_is_valid(to_i915(dev),
> + limit,
> &clock))
> continue;
>
> @@ -977,7 +982,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
>
> chv_calc_dpll_params(refclk, &clock);
>
> - if (!intel_PLL_is_valid(dev, limit, &clock))
> + if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
> continue;
>
> if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
> @@ -5852,7 +5857,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> max_cdclk = 308571;
>
> dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> dev_priv->max_cdclk_freq = 624000;
> } else if (IS_BROADWELL(dev_priv)) {
> /*
> @@ -10650,7 +10655,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skylake_get_ddi_pll(dev_priv, port, pipe_config);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> bxt_get_ddi_pll(dev_priv, port, pipe_config);
> else
> haswell_get_ddi_pll(dev_priv, port, pipe_config);
> @@ -12808,7 +12813,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
> DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
>
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
> "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
> "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
> @@ -15401,7 +15406,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> if (intel_crt_present(dev))
> intel_crt_init(dev);
>
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> /*
> * FIXME: Broxton doesn't support port detection via the
> * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 02e74c467a55..b6c8b25ee1d4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -571,7 +571,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> struct intel_encoder *encoder;
>
> if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> - !IS_BROXTON(dev)))
> + !IS_BROXTON(dev_priv)))
> return;
>
> /*
> @@ -591,7 +591,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> continue;
>
> intel_dp = enc_to_intel_dp(&encoder->base);
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> intel_dp->pps_reset = true;
> else
> intel_dp->pps_pipe = INVALID_PIPE;
> @@ -2981,7 +2981,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum port port = dp_to_dig_port(intel_dp)->port;
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (INTEL_INFO(dev)->gen >= 9) {
> if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> @@ -3344,7 +3344,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> if (HAS_DDI(dev_priv)) {
> signal_levels = ddi_signal_levels(intel_dp);
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> signal_levels = 0;
> else
> mask = DDI_BUF_EMP_MASK;
> @@ -5072,7 +5072,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> /* Compute the divisor for the pp clock, simply match the Bspec
> * formula. */
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> pp_div = I915_READ(regs.pp_ctrl);
> pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> @@ -5098,7 +5098,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>
> I915_WRITE(regs.pp_on, pp_on);
> I915_WRITE(regs.pp_off, pp_off);
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> I915_WRITE(regs.pp_ctrl, pp_div);
> else
> I915_WRITE(regs.pp_div, pp_div);
> @@ -5106,7 +5106,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> I915_READ(regs.pp_on),
> I915_READ(regs.pp_off),
> - IS_BROXTON(dev) ?
> + IS_BROXTON(dev_priv) ?
> (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> I915_READ(regs.pp_div));
> }
> @@ -5715,7 +5715,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> break;
> case PORT_B:
> intel_encoder->hpd_pin = HPD_PORT_B;
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> intel_encoder->hpd_pin = HPD_PORT_A;
> break;
> case PORT_C:
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 7cf9d91c0746..605d0b509f24 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1853,7 +1853,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> dpll_mgr = &skl_pll_mgr;
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> dpll_mgr = &bxt_pll_mgr;
> else if (HAS_DDI(dev_priv))
> dpll_mgr = &hsw_pll_mgr;
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 5b1e445a80d0..48e8dd108f4f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -437,11 +437,11 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
>
> static void intel_dsi_device_ready(struct intel_encoder *encoder)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_device_ready(encoder);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> bxt_dsi_device_ready(encoder);
> }
>
> @@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
> + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -494,7 +494,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
> enum port port;
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
> + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -656,7 +656,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>
> static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> {
> - struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
> @@ -664,7 +663,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> DRM_DEBUG_KMS("\n");
> for_each_dsi_port(port, intel_dsi->ports) {
> /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
> - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
> + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
> u32 val;
>
> @@ -762,7 +761,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>
> /* XXX: this only works for one DSI output */
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t ctrl_reg = IS_BROXTON(dev) ?
> + i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
>
> @@ -970,11 +969,11 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> static void intel_dsi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 pclk;
> DRM_DEBUG_KMS("\n");
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> bxt_dsi_get_pipe_config(encoder, pipe_config);
>
> pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
> @@ -1066,7 +1065,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
> hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> /*
> * Program hdisplay and vdisplay on MIPI transcoder.
> * This is different from calculated hactive and
> @@ -1153,7 +1152,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> tmp &= ~READ_REQUEST_PRIORITY_MASK;
> I915_WRITE(MIPI_CTRL(port), tmp |
> READ_REQUEST_PRIORITY_HIGH);
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> enum pipe pipe = intel_crtc->pipe;
>
> tmp = I915_READ(MIPI_CTRL(port));
> @@ -1242,7 +1241,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> I915_WRITE(MIPI_INIT_COUNT(port),
> txclkesc(intel_dsi->escape_clk_div, 100));
>
> - if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
> + if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
> /*
> * BXT spec says write MIPI_INIT_COUNT for
> * both the ports, even if only one is
> @@ -1452,7 +1451,7 @@ void intel_dsi_init(struct drm_device *dev)
>
> if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> } else {
> DRM_ERROR("Unsupported Mipi device to reg base");
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 6ab58a01b18e..56eff6004bc0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> struct intel_crtc_state *config)
> {
> - if (IS_BROXTON(encoder->base.dev))
> + if (IS_BROXTON(to_i915(encoder->base.dev)))
> return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
> else
> return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
> @@ -515,11 +515,11 @@ bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
> int intel_compute_dsi_pll(struct intel_encoder *encoder,
> struct intel_crtc_state *config)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return vlv_compute_dsi_pll(encoder, config);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> return bxt_compute_dsi_pll(encoder, config);
>
> return -ENODEV;
> @@ -528,21 +528,21 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
> void intel_enable_dsi_pll(struct intel_encoder *encoder,
> const struct intel_crtc_state *config)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_enable_dsi_pll(encoder, config);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> bxt_enable_dsi_pll(encoder, config);
> }
>
> void intel_disable_dsi_pll(struct intel_encoder *encoder)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_disable_dsi_pll(encoder);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> bxt_disable_dsi_pll(encoder);
> }
>
> @@ -564,10 +564,10 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>
> void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> bxt_dsi_reset_clocks(encoder, port);
> - else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_reset_clocks(encoder, port);
> }
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 182204373931..5d5d609ed5e9 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -376,16 +376,16 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
>
> /* WaDisableMinuteIaClockGating:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
> ~GUC_ENABLE_MIA_CLOCK_GATING));
> }
>
> /* WaC6DisallowByGfxPause:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_B0))
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
> I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> else
> I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> @@ -730,7 +730,7 @@ void intel_guc_init(struct drm_device *dev)
> fw_path = I915_SKL_GUC_UCODE;
> guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
> guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> fw_path = I915_BXT_GUC_UCODE;
> guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
> guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 6607c4e3c36c..f6562451c47e 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1241,7 +1241,7 @@ static enum drm_mode_status
> hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> int clock, bool respect_downstream_limits)
> {
> - struct drm_device *dev = intel_hdmi_to_dev(hdmi);
> + struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
>
> if (clock < 25000)
> return MODE_CLOCK_LOW;
> @@ -1249,11 +1249,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> return MODE_CLOCK_HIGH;
>
> /* BXT DPLL can't generate 223-240 MHz */
> - if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
> + if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
> return MODE_CLOCK_RANGE;
>
> /* CHV DPLL can't generate 216-240 MHz */
> - if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
> + if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
> return MODE_CLOCK_RANGE;
>
> return MODE_OK;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 025fbd522819..e4bb85c9c6e1 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2596,7 +2596,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> skl_display_core_init(dev_priv, resume);
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> bxt_display_core_init(dev_priv, resume);
> } else if (IS_CHERRYVIEW(dev)) {
> mutex_lock(&power_domains->lock);
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH 13/19] drm/i915: Make IS_BROXTON only take dev_priv
2016-10-12 11:52 ` David Weinehall
@ 2016-10-12 12:06 ` Tvrtko Ursulin
2016-10-12 12:50 ` David Weinehall
0 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-12 12:06 UTC (permalink / raw)
To: Tvrtko Ursulin, Intel-gfx
On 12/10/2016 12:52, David Weinehall wrote:
> On Tue, Oct 11, 2016 at 02:21:46PM +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Saves 1392 bytes of .rodata strings.
>>
>> v2: Add parantheses around dev_priv. (Ville Syrjala)
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> This patch does quite a bit more than just change IS_BROXTON to use
> dev_priv...
Some cascade effects on function prototypes here and there - if you find
it objectionable I can try to eliminate or at least minimise?
Regards,
Tvrtko
>> ---
>> drivers/gpu/drm/i915/i915_drv.c | 2 +-
>> drivers/gpu/drm/i915/i915_drv.h | 5 +++--
>> drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++++++++++++++++----------------
>> drivers/gpu/drm/i915/i915_irq.c | 2 +-
>> drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
>> drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++-----------
>> drivers/gpu/drm/i915/intel_dp.c | 16 ++++++-------
>> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
>> drivers/gpu/drm/i915/intel_dsi.c | 27 +++++++++++-----------
>> drivers/gpu/drm/i915/intel_dsi_pll.c | 26 ++++++++++-----------
>> drivers/gpu/drm/i915/intel_guc_loader.c | 8 +++----
>> drivers/gpu/drm/i915/intel_hdmi.c | 6 ++---
>> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
>> 13 files changed, 89 insertions(+), 82 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index d854ea4a7e92..18af6d1ccec9 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -2437,7 +2437,7 @@ static int intel_runtime_resume(struct device *kdev)
>> if (IS_GEN6(dev_priv))
>> intel_init_pch_refclk(dev);
>>
>> - if (IS_BROXTON(dev)) {
>> + if (IS_BROXTON(dev_priv)) {
>> bxt_disable_dc9(dev_priv);
>> bxt_display_core_init(dev_priv, true);
>> if (dev_priv->csr.dmc_payload &&
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 9784e61400e5..ad9299196d13 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2664,7 +2664,7 @@ struct drm_i915_cmd_table {
>> #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
>> #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
>> #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
>> -#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
>> +#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
>> #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
>> #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
>> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>> @@ -2724,7 +2724,8 @@ struct drm_i915_cmd_table {
>> #define BXT_REVID_B0 0x3
>> #define BXT_REVID_C0 0x9
>>
>> -#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
>> +#define IS_BXT_REVID(dev_priv, since, until) \
>> + (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
>>
>> #define KBL_REVID_A0 0x0
>> #define KBL_REVID_B0 0x1
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index cf43a5632961..e628691fe97e 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p)
>> /* We use the flushing unmap only with ppgtt structures:
>> * page directories, page tables and scratch pages.
>> */
>> -static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
>> +static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
>> {
>> /* There are only few exceptions for gen >=6. chv and bxt.
>> * And we are not sure about the latter so play safe for now.
>> */
>> - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
>> + if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
>> drm_clflush_virt_range(vaddr, PAGE_SIZE);
>>
>> kunmap_atomic(vaddr);
>> }
>>
>> #define kmap_px(px) kmap_page_dma(px_base(px))
>> -#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
>> +#define kunmap_px(ppgtt, vaddr) \
>> + kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr))
>>
>> #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
>> #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
>> -#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
>> -#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
>> +#define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v))
>> +#define fill32_px(dev_priv, px, v) \
>> + fill_page_dma_32((dev_priv), px_base(px), (v))
>>
>> -static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
>> - const uint64_t val)
>> +static void fill_page_dma(struct drm_i915_private *dev_priv,
>> + struct i915_page_dma *p, const uint64_t val)
>> {
>> int i;
>> uint64_t * const vaddr = kmap_page_dma(p);
>> @@ -401,17 +403,17 @@ static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
>> for (i = 0; i < 512; i++)
>> vaddr[i] = val;
>>
>> - kunmap_page_dma(dev, vaddr);
>> + kunmap_page_dma(dev_priv, vaddr);
>> }
>>
>> -static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
>> - const uint32_t val32)
>> +static void fill_page_dma_32(struct drm_i915_private *dev_priv,
>> + struct i915_page_dma *p, const uint32_t val32)
>> {
>> uint64_t v = val32;
>>
>> v = v << 32 | val32;
>>
>> - fill_page_dma(dev, p, v);
>> + fill_page_dma(dev_priv, p, v);
>> }
>>
>> static int
>> @@ -474,7 +476,7 @@ static void gen8_initialize_pt(struct i915_address_space *vm,
>> scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
>> I915_CACHE_LLC, true);
>>
>> - fill_px(vm->dev, pt, scratch_pte);
>> + fill_px(to_i915(vm->dev), pt, scratch_pte);
>> }
>>
>> static void gen6_initialize_pt(struct i915_address_space *vm,
>> @@ -487,7 +489,7 @@ static void gen6_initialize_pt(struct i915_address_space *vm,
>> scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
>> I915_CACHE_LLC, true, 0);
>>
>> - fill32_px(vm->dev, pt, scratch_pte);
>> + fill32_px(to_i915(vm->dev), pt, scratch_pte);
>> }
>>
>> static struct i915_page_directory *alloc_pd(struct drm_device *dev)
>> @@ -534,7 +536,7 @@ static void gen8_initialize_pd(struct i915_address_space *vm,
>>
>> scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
>>
>> - fill_px(vm->dev, pd, scratch_pde);
>> + fill_px(to_i915(vm->dev), pd, scratch_pde);
>> }
>>
>> static int __pdp_init(struct drm_device *dev,
>> @@ -615,7 +617,7 @@ static void gen8_initialize_pdp(struct i915_address_space *vm,
>>
>> scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
>>
>> - fill_px(vm->dev, pdp, scratch_pdpe);
>> + fill_px(to_i915(vm->dev), pdp, scratch_pdpe);
>> }
>>
>> static void gen8_initialize_pml4(struct i915_address_space *vm,
>> @@ -626,7 +628,7 @@ static void gen8_initialize_pml4(struct i915_address_space *vm,
>> scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
>> I915_CACHE_LLC);
>>
>> - fill_px(vm->dev, pml4, scratch_pml4e);
>> + fill_px(to_i915(vm->dev), pml4, scratch_pml4e);
>> }
>>
>> static void
>> @@ -2135,7 +2137,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
>> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
>> else if (IS_SKYLAKE(dev_priv))
>> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>> - else if (IS_BROXTON(dev))
>> + else if (IS_BROXTON(dev_priv))
>> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
>> }
>>
>> @@ -2895,7 +2897,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
>> * resort to an uncached mapping. The WC issue is easily caught by the
>> * readback check when writing GTT PTE entries.
>> */
>> - if (IS_BROXTON(ggtt->base.dev))
>> + if (IS_BROXTON(to_i915(ggtt->base.dev)))
>> ggtt->gsm = ioremap_nocache(phys_addr, size);
>> else
>> ggtt->gsm = ioremap_wc(phys_addr, size);
>> @@ -3267,7 +3269,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
>> ggtt->base.closed = false;
>>
>> if (INTEL_INFO(dev)->gen >= 8) {
>> - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
>> + if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
>> chv_setup_private_ppat(dev_priv);
>> else
>> bdw_setup_private_ppat(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index 47337aabc326..75f4ba935ebc 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -4597,7 +4597,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>> dev->driver->irq_uninstall = gen8_irq_uninstall;
>> dev->driver->enable_vblank = gen8_enable_vblank;
>> dev->driver->disable_vblank = gen8_disable_vblank;
>> - if (IS_BROXTON(dev))
>> + if (IS_BROXTON(dev_priv))
>> dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
>> else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
>> dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 07164e250adf..a76afd7a6616 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -2509,7 +2509,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
>> * configuration so that we use the proper lane count for our
>> * calculations.
>> */
>> - if (IS_BROXTON(dev) && port == PORT_A) {
>> + if (IS_BROXTON(dev_priv) && port == PORT_A) {
>> if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
>> DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
>> intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
>> @@ -2533,7 +2533,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
>> * On BXT A0/A1, sw needs to activate DDIA HPD logic and
>> * interrupts to check the external panel connection.
>> */
>> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
>> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) && port == PORT_B)
>> dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
>> else
>> dev_priv->hotplug.irq_port[port] = intel_dig_port;
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index e673a803f213..636e5572b996 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -600,7 +600,7 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
>> * the given connectors.
>> */
>>
>> -static bool intel_PLL_is_valid(struct drm_device *dev,
>> +static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
>> const struct intel_limit *limit,
>> const struct dpll *clock)
>> {
>> @@ -613,12 +613,13 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
>> if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
>> INTELPllInvalid("m1 out of range\n");
>>
>> - if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
>> - !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
>> + if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
>> + !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
>> if (clock->m1 <= clock->m2)
>> INTELPllInvalid("m1 <= m2\n");
>>
>> - if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
>> + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
>> + !IS_BROXTON(dev_priv)) {
>> if (clock->p < limit->p.min || limit->p.max < clock->p)
>> INTELPllInvalid("p out of range\n");
>> if (clock->m < limit->m.min || limit->m.max < clock->m)
>> @@ -698,7 +699,8 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
>> int this_err;
>>
>> i9xx_calc_dpll_params(refclk, &clock);
>> - if (!intel_PLL_is_valid(dev, limit,
>> + if (!intel_PLL_is_valid(to_i915(dev),
>> + limit,
>> &clock))
>> continue;
>> if (match_clock &&
>> @@ -753,7 +755,8 @@ pnv_find_best_dpll(const struct intel_limit *limit,
>> int this_err;
>>
>> pnv_calc_dpll_params(refclk, &clock);
>> - if (!intel_PLL_is_valid(dev, limit,
>> + if (!intel_PLL_is_valid(to_i915(dev),
>> + limit,
>> &clock))
>> continue;
>> if (match_clock &&
>> @@ -813,7 +816,8 @@ g4x_find_best_dpll(const struct intel_limit *limit,
>> int this_err;
>>
>> i9xx_calc_dpll_params(refclk, &clock);
>> - if (!intel_PLL_is_valid(dev, limit,
>> + if (!intel_PLL_is_valid(to_i915(dev),
>> + limit,
>> &clock))
>> continue;
>>
>> @@ -909,7 +913,8 @@ vlv_find_best_dpll(const struct intel_limit *limit,
>>
>> vlv_calc_dpll_params(refclk, &clock);
>>
>> - if (!intel_PLL_is_valid(dev, limit,
>> + if (!intel_PLL_is_valid(to_i915(dev),
>> + limit,
>> &clock))
>> continue;
>>
>> @@ -977,7 +982,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
>>
>> chv_calc_dpll_params(refclk, &clock);
>>
>> - if (!intel_PLL_is_valid(dev, limit, &clock))
>> + if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
>> continue;
>>
>> if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
>> @@ -5852,7 +5857,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
>> max_cdclk = 308571;
>>
>> dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
>> - } else if (IS_BROXTON(dev)) {
>> + } else if (IS_BROXTON(dev_priv)) {
>> dev_priv->max_cdclk_freq = 624000;
>> } else if (IS_BROADWELL(dev_priv)) {
>> /*
>> @@ -10650,7 +10655,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>>
>> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>> skylake_get_ddi_pll(dev_priv, port, pipe_config);
>> - else if (IS_BROXTON(dev))
>> + else if (IS_BROXTON(dev_priv))
>> bxt_get_ddi_pll(dev_priv, port, pipe_config);
>> else
>> haswell_get_ddi_pll(dev_priv, port, pipe_config);
>> @@ -12808,7 +12813,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
>> DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
>> DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
>>
>> - if (IS_BROXTON(dev)) {
>> + if (IS_BROXTON(dev_priv)) {
>> DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
>> "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
>> "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
>> @@ -15401,7 +15406,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>> if (intel_crt_present(dev))
>> intel_crt_init(dev);
>>
>> - if (IS_BROXTON(dev)) {
>> + if (IS_BROXTON(dev_priv)) {
>> /*
>> * FIXME: Broxton doesn't support port detection via the
>> * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 02e74c467a55..b6c8b25ee1d4 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -571,7 +571,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
>> struct intel_encoder *encoder;
>>
>> if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
>> - !IS_BROXTON(dev)))
>> + !IS_BROXTON(dev_priv)))
>> return;
>>
>> /*
>> @@ -591,7 +591,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
>> continue;
>>
>> intel_dp = enc_to_intel_dp(&encoder->base);
>> - if (IS_BROXTON(dev))
>> + if (IS_BROXTON(dev_priv))
>> intel_dp->pps_reset = true;
>> else
>> intel_dp->pps_pipe = INVALID_PIPE;
>> @@ -2981,7 +2981,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>> struct drm_i915_private *dev_priv = to_i915(dev);
>> enum port port = dp_to_dig_port(intel_dp)->port;
>>
>> - if (IS_BROXTON(dev))
>> + if (IS_BROXTON(dev_priv))
>> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>> else if (INTEL_INFO(dev)->gen >= 9) {
>> if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
>> @@ -3344,7 +3344,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>> if (HAS_DDI(dev_priv)) {
>> signal_levels = ddi_signal_levels(intel_dp);
>>
>> - if (IS_BROXTON(dev))
>> + if (IS_BROXTON(dev_priv))
>> signal_levels = 0;
>> else
>> mask = DDI_BUF_EMP_MASK;
>> @@ -5072,7 +5072,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>> (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
>> /* Compute the divisor for the pp clock, simply match the Bspec
>> * formula. */
>> - if (IS_BROXTON(dev)) {
>> + if (IS_BROXTON(dev_priv)) {
>> pp_div = I915_READ(regs.pp_ctrl);
>> pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
>> pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
>> @@ -5098,7 +5098,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>>
>> I915_WRITE(regs.pp_on, pp_on);
>> I915_WRITE(regs.pp_off, pp_off);
>> - if (IS_BROXTON(dev))
>> + if (IS_BROXTON(dev_priv))
>> I915_WRITE(regs.pp_ctrl, pp_div);
>> else
>> I915_WRITE(regs.pp_div, pp_div);
>> @@ -5106,7 +5106,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>> DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
>> I915_READ(regs.pp_on),
>> I915_READ(regs.pp_off),
>> - IS_BROXTON(dev) ?
>> + IS_BROXTON(dev_priv) ?
>> (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
>> I915_READ(regs.pp_div));
>> }
>> @@ -5715,7 +5715,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>> break;
>> case PORT_B:
>> intel_encoder->hpd_pin = HPD_PORT_B;
>> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
>> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
>> intel_encoder->hpd_pin = HPD_PORT_A;
>> break;
>> case PORT_C:
>> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> index 7cf9d91c0746..605d0b509f24 100644
>> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>> @@ -1853,7 +1853,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
>>
>> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>> dpll_mgr = &skl_pll_mgr;
>> - else if (IS_BROXTON(dev))
>> + else if (IS_BROXTON(dev_priv))
>> dpll_mgr = &bxt_pll_mgr;
>> else if (HAS_DDI(dev_priv))
>> dpll_mgr = &hsw_pll_mgr;
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index 5b1e445a80d0..48e8dd108f4f 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -437,11 +437,11 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
>>
>> static void intel_dsi_device_ready(struct intel_encoder *encoder)
>> {
>> - struct drm_device *dev = encoder->base.dev;
>> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>
>> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> vlv_dsi_device_ready(encoder);
>> - else if (IS_BROXTON(dev))
>> + else if (IS_BROXTON(dev_priv))
>> bxt_dsi_device_ready(encoder);
>> }
>>
>> @@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>> }
>>
>> for_each_dsi_port(port, intel_dsi->ports) {
>> - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
>> + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
>> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
>> u32 temp;
>>
>> @@ -494,7 +494,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
>> enum port port;
>>
>> for_each_dsi_port(port, intel_dsi->ports) {
>> - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
>> + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
>> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
>> u32 temp;
>>
>> @@ -656,7 +656,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>>
>> static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
>> {
>> - struct drm_device *dev = encoder->base.dev;
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>> enum port port;
>> @@ -664,7 +663,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
>> DRM_DEBUG_KMS("\n");
>> for_each_dsi_port(port, intel_dsi->ports) {
>> /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
>> - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
>> + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
>> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
>> u32 val;
>>
>> @@ -762,7 +761,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>>
>> /* XXX: this only works for one DSI output */
>> for_each_dsi_port(port, intel_dsi->ports) {
>> - i915_reg_t ctrl_reg = IS_BROXTON(dev) ?
>> + i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
>> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
>> bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
>>
>> @@ -970,11 +969,11 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
>> static void intel_dsi_get_config(struct intel_encoder *encoder,
>> struct intel_crtc_state *pipe_config)
>> {
>> - struct drm_device *dev = encoder->base.dev;
>> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> u32 pclk;
>> DRM_DEBUG_KMS("\n");
>>
>> - if (IS_BROXTON(dev))
>> + if (IS_BROXTON(dev_priv))
>> bxt_dsi_get_pipe_config(encoder, pipe_config);
>>
>> pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
>> @@ -1066,7 +1065,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
>> hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>>
>> for_each_dsi_port(port, intel_dsi->ports) {
>> - if (IS_BROXTON(dev)) {
>> + if (IS_BROXTON(dev_priv)) {
>> /*
>> * Program hdisplay and vdisplay on MIPI transcoder.
>> * This is different from calculated hactive and
>> @@ -1153,7 +1152,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
>> tmp &= ~READ_REQUEST_PRIORITY_MASK;
>> I915_WRITE(MIPI_CTRL(port), tmp |
>> READ_REQUEST_PRIORITY_HIGH);
>> - } else if (IS_BROXTON(dev)) {
>> + } else if (IS_BROXTON(dev_priv)) {
>> enum pipe pipe = intel_crtc->pipe;
>>
>> tmp = I915_READ(MIPI_CTRL(port));
>> @@ -1242,7 +1241,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
>> I915_WRITE(MIPI_INIT_COUNT(port),
>> txclkesc(intel_dsi->escape_clk_div, 100));
>>
>> - if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
>> + if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
>> /*
>> * BXT spec says write MIPI_INIT_COUNT for
>> * both the ports, even if only one is
>> @@ -1452,7 +1451,7 @@ void intel_dsi_init(struct drm_device *dev)
>>
>> if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>> dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
>> - } else if (IS_BROXTON(dev)) {
>> + } else if (IS_BROXTON(dev_priv)) {
>> dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
>> } else {
>> DRM_ERROR("Unsupported Mipi device to reg base");
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> index 6ab58a01b18e..56eff6004bc0 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> @@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
>> u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
>> struct intel_crtc_state *config)
>> {
>> - if (IS_BROXTON(encoder->base.dev))
>> + if (IS_BROXTON(to_i915(encoder->base.dev)))
>> return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
>> else
>> return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
>> @@ -515,11 +515,11 @@ bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
>> int intel_compute_dsi_pll(struct intel_encoder *encoder,
>> struct intel_crtc_state *config)
>> {
>> - struct drm_device *dev = encoder->base.dev;
>> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>
>> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> return vlv_compute_dsi_pll(encoder, config);
>> - else if (IS_BROXTON(dev))
>> + else if (IS_BROXTON(dev_priv))
>> return bxt_compute_dsi_pll(encoder, config);
>>
>> return -ENODEV;
>> @@ -528,21 +528,21 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
>> void intel_enable_dsi_pll(struct intel_encoder *encoder,
>> const struct intel_crtc_state *config)
>> {
>> - struct drm_device *dev = encoder->base.dev;
>> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>
>> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> vlv_enable_dsi_pll(encoder, config);
>> - else if (IS_BROXTON(dev))
>> + else if (IS_BROXTON(dev_priv))
>> bxt_enable_dsi_pll(encoder, config);
>> }
>>
>> void intel_disable_dsi_pll(struct intel_encoder *encoder)
>> {
>> - struct drm_device *dev = encoder->base.dev;
>> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>
>> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> vlv_disable_dsi_pll(encoder);
>> - else if (IS_BROXTON(dev))
>> + else if (IS_BROXTON(dev_priv))
>> bxt_disable_dsi_pll(encoder);
>> }
>>
>> @@ -564,10 +564,10 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>>
>> void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>> {
>> - struct drm_device *dev = encoder->base.dev;
>> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>
>> - if (IS_BROXTON(dev))
>> + if (IS_BROXTON(dev_priv))
>> bxt_dsi_reset_clocks(encoder, port);
>> - else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
>> + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>> vlv_dsi_reset_clocks(encoder, port);
>> }
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index 182204373931..5d5d609ed5e9 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -376,16 +376,16 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>> I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
>>
>> /* WaDisableMinuteIaClockGating:bxt */
>> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
>> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
>> I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
>> ~GUC_ENABLE_MIA_CLOCK_GATING));
>> }
>>
>> /* WaC6DisallowByGfxPause:bxt */
>> - if (IS_BXT_REVID(dev, 0, BXT_REVID_B0))
>> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
>> I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
>>
>> - if (IS_BROXTON(dev))
>> + if (IS_BROXTON(dev_priv))
>> I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>> else
>> I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>> @@ -730,7 +730,7 @@ void intel_guc_init(struct drm_device *dev)
>> fw_path = I915_SKL_GUC_UCODE;
>> guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
>> guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
>> - } else if (IS_BROXTON(dev)) {
>> + } else if (IS_BROXTON(dev_priv)) {
>> fw_path = I915_BXT_GUC_UCODE;
>> guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
>> guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
>> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
>> index 6607c4e3c36c..f6562451c47e 100644
>> --- a/drivers/gpu/drm/i915/intel_hdmi.c
>> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
>> @@ -1241,7 +1241,7 @@ static enum drm_mode_status
>> hdmi_port_clock_valid(struct intel_hdmi *hdmi,
>> int clock, bool respect_downstream_limits)
>> {
>> - struct drm_device *dev = intel_hdmi_to_dev(hdmi);
>> + struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
>>
>> if (clock < 25000)
>> return MODE_CLOCK_LOW;
>> @@ -1249,11 +1249,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
>> return MODE_CLOCK_HIGH;
>>
>> /* BXT DPLL can't generate 223-240 MHz */
>> - if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
>> + if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
>> return MODE_CLOCK_RANGE;
>>
>> /* CHV DPLL can't generate 216-240 MHz */
>> - if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
>> + if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
>> return MODE_CLOCK_RANGE;
>>
>> return MODE_OK;
>> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> index 025fbd522819..e4bb85c9c6e1 100644
>> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> @@ -2596,7 +2596,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
>>
>> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
>> skl_display_core_init(dev_priv, resume);
>> - } else if (IS_BROXTON(dev)) {
>> + } else if (IS_BROXTON(dev_priv)) {
>> bxt_display_core_init(dev_priv, resume);
>> } else if (IS_CHERRYVIEW(dev)) {
>> mutex_lock(&power_domains->lock);
>> --
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH 13/19] drm/i915: Make IS_BROXTON only take dev_priv
2016-10-12 12:06 ` Tvrtko Ursulin
@ 2016-10-12 12:50 ` David Weinehall
2016-10-13 9:44 ` [PATCH v3 " Tvrtko Ursulin
0 siblings, 1 reply; 46+ messages in thread
From: David Weinehall @ 2016-10-12 12:50 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Wed, Oct 12, 2016 at 01:06:51PM +0100, Tvrtko Ursulin wrote:
>
> On 12/10/2016 12:52, David Weinehall wrote:
> > On Tue, Oct 11, 2016 at 02:21:46PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > >
> > > Saves 1392 bytes of .rodata strings.
> > >
> > > v2: Add parantheses around dev_priv. (Ville Syrjala)
> > >
> > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > This patch does quite a bit more than just change IS_BROXTON to use
> > dev_priv...
>
> Some cascade effects on function prototypes here and there - if you find it
> objectionable I can try to eliminate or at least minimise?
I don't find the changes objectionable -- they are, as you say, cascade
effects. It might, however, be worth explaining in the patch description
that the patch does a bit more than just more than IS_BROXTON(). Doing
so for just minor differences is overkill, but in this case it feels
justified.
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 2 +-
> > > drivers/gpu/drm/i915/i915_drv.h | 5 +++--
> > > drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++++++++++++++++----------------
> > > drivers/gpu/drm/i915/i915_irq.c | 2 +-
> > > drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> > > drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++-----------
> > > drivers/gpu/drm/i915/intel_dp.c | 16 ++++++-------
> > > drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> > > drivers/gpu/drm/i915/intel_dsi.c | 27 +++++++++++-----------
> > > drivers/gpu/drm/i915/intel_dsi_pll.c | 26 ++++++++++-----------
> > > drivers/gpu/drm/i915/intel_guc_loader.c | 8 +++----
> > > drivers/gpu/drm/i915/intel_hdmi.c | 6 ++---
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> > > 13 files changed, 89 insertions(+), 82 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > index d854ea4a7e92..18af6d1ccec9 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -2437,7 +2437,7 @@ static int intel_runtime_resume(struct device *kdev)
> > > if (IS_GEN6(dev_priv))
> > > intel_init_pch_refclk(dev);
> > > - if (IS_BROXTON(dev)) {
> > > + if (IS_BROXTON(dev_priv)) {
> > > bxt_disable_dc9(dev_priv);
> > > bxt_display_core_init(dev_priv, true);
> > > if (dev_priv->csr.dmc_payload &&
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index 9784e61400e5..ad9299196d13 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -2664,7 +2664,7 @@ struct drm_i915_cmd_table {
> > > #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
> > > #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> > > #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
> > > -#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
> > > +#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
> > > #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
> > > #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
> > > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> > > @@ -2724,7 +2724,8 @@ struct drm_i915_cmd_table {
> > > #define BXT_REVID_B0 0x3
> > > #define BXT_REVID_C0 0x9
> > > -#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
> > > +#define IS_BXT_REVID(dev_priv, since, until) \
> > > + (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
> > > #define KBL_REVID_A0 0x0
> > > #define KBL_REVID_B0 0x1
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > index cf43a5632961..e628691fe97e 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > @@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p)
> > > /* We use the flushing unmap only with ppgtt structures:
> > > * page directories, page tables and scratch pages.
> > > */
> > > -static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
> > > +static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
> > > {
> > > /* There are only few exceptions for gen >=6. chv and bxt.
> > > * And we are not sure about the latter so play safe for now.
> > > */
> > > - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
> > > + if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> > > drm_clflush_virt_range(vaddr, PAGE_SIZE);
> > > kunmap_atomic(vaddr);
> > > }
> > > #define kmap_px(px) kmap_page_dma(px_base(px))
> > > -#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
> > > +#define kunmap_px(ppgtt, vaddr) \
> > > + kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr))
> > > #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
> > > #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
> > > -#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
> > > -#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
> > > +#define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v))
> > > +#define fill32_px(dev_priv, px, v) \
> > > + fill_page_dma_32((dev_priv), px_base(px), (v))
> > > -static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
> > > - const uint64_t val)
> > > +static void fill_page_dma(struct drm_i915_private *dev_priv,
> > > + struct i915_page_dma *p, const uint64_t val)
> > > {
> > > int i;
> > > uint64_t * const vaddr = kmap_page_dma(p);
> > > @@ -401,17 +403,17 @@ static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
> > > for (i = 0; i < 512; i++)
> > > vaddr[i] = val;
> > > - kunmap_page_dma(dev, vaddr);
> > > + kunmap_page_dma(dev_priv, vaddr);
> > > }
> > > -static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
> > > - const uint32_t val32)
> > > +static void fill_page_dma_32(struct drm_i915_private *dev_priv,
> > > + struct i915_page_dma *p, const uint32_t val32)
> > > {
> > > uint64_t v = val32;
> > > v = v << 32 | val32;
> > > - fill_page_dma(dev, p, v);
> > > + fill_page_dma(dev_priv, p, v);
> > > }
> > > static int
> > > @@ -474,7 +476,7 @@ static void gen8_initialize_pt(struct i915_address_space *vm,
> > > scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
> > > I915_CACHE_LLC, true);
> > > - fill_px(vm->dev, pt, scratch_pte);
> > > + fill_px(to_i915(vm->dev), pt, scratch_pte);
> > > }
> > > static void gen6_initialize_pt(struct i915_address_space *vm,
> > > @@ -487,7 +489,7 @@ static void gen6_initialize_pt(struct i915_address_space *vm,
> > > scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
> > > I915_CACHE_LLC, true, 0);
> > > - fill32_px(vm->dev, pt, scratch_pte);
> > > + fill32_px(to_i915(vm->dev), pt, scratch_pte);
> > > }
> > > static struct i915_page_directory *alloc_pd(struct drm_device *dev)
> > > @@ -534,7 +536,7 @@ static void gen8_initialize_pd(struct i915_address_space *vm,
> > > scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
> > > - fill_px(vm->dev, pd, scratch_pde);
> > > + fill_px(to_i915(vm->dev), pd, scratch_pde);
> > > }
> > > static int __pdp_init(struct drm_device *dev,
> > > @@ -615,7 +617,7 @@ static void gen8_initialize_pdp(struct i915_address_space *vm,
> > > scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
> > > - fill_px(vm->dev, pdp, scratch_pdpe);
> > > + fill_px(to_i915(vm->dev), pdp, scratch_pdpe);
> > > }
> > > static void gen8_initialize_pml4(struct i915_address_space *vm,
> > > @@ -626,7 +628,7 @@ static void gen8_initialize_pml4(struct i915_address_space *vm,
> > > scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
> > > I915_CACHE_LLC);
> > > - fill_px(vm->dev, pml4, scratch_pml4e);
> > > + fill_px(to_i915(vm->dev), pml4, scratch_pml4e);
> > > }
> > > static void
> > > @@ -2135,7 +2137,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
> > > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> > > else if (IS_SKYLAKE(dev_priv))
> > > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> > > - else if (IS_BROXTON(dev))
> > > + else if (IS_BROXTON(dev_priv))
> > > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> > > }
> > > @@ -2895,7 +2897,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
> > > * resort to an uncached mapping. The WC issue is easily caught by the
> > > * readback check when writing GTT PTE entries.
> > > */
> > > - if (IS_BROXTON(ggtt->base.dev))
> > > + if (IS_BROXTON(to_i915(ggtt->base.dev)))
> > > ggtt->gsm = ioremap_nocache(phys_addr, size);
> > > else
> > > ggtt->gsm = ioremap_wc(phys_addr, size);
> > > @@ -3267,7 +3269,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
> > > ggtt->base.closed = false;
> > > if (INTEL_INFO(dev)->gen >= 8) {
> > > - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
> > > + if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> > > chv_setup_private_ppat(dev_priv);
> > > else
> > > bdw_setup_private_ppat(dev_priv);
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > > index 47337aabc326..75f4ba935ebc 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -4597,7 +4597,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> > > dev->driver->irq_uninstall = gen8_irq_uninstall;
> > > dev->driver->enable_vblank = gen8_enable_vblank;
> > > dev->driver->disable_vblank = gen8_disable_vblank;
> > > - if (IS_BROXTON(dev))
> > > + if (IS_BROXTON(dev_priv))
> > > dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> > > else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
> > > dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > > index 07164e250adf..a76afd7a6616 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -2509,7 +2509,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
> > > * configuration so that we use the proper lane count for our
> > > * calculations.
> > > */
> > > - if (IS_BROXTON(dev) && port == PORT_A) {
> > > + if (IS_BROXTON(dev_priv) && port == PORT_A) {
> > > if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> > > DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> > > intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> > > @@ -2533,7 +2533,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
> > > * On BXT A0/A1, sw needs to activate DDIA HPD logic and
> > > * interrupts to check the external panel connection.
> > > */
> > > - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
> > > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) && port == PORT_B)
> > > dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
> > > else
> > > dev_priv->hotplug.irq_port[port] = intel_dig_port;
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index e673a803f213..636e5572b996 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -600,7 +600,7 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
> > > * the given connectors.
> > > */
> > > -static bool intel_PLL_is_valid(struct drm_device *dev,
> > > +static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
> > > const struct intel_limit *limit,
> > > const struct dpll *clock)
> > > {
> > > @@ -613,12 +613,13 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
> > > if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
> > > INTELPllInvalid("m1 out of range\n");
> > > - if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
> > > - !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
> > > + if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> > > + !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
> > > if (clock->m1 <= clock->m2)
> > > INTELPllInvalid("m1 <= m2\n");
> > > - if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
> > > + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> > > + !IS_BROXTON(dev_priv)) {
> > > if (clock->p < limit->p.min || limit->p.max < clock->p)
> > > INTELPllInvalid("p out of range\n");
> > > if (clock->m < limit->m.min || limit->m.max < clock->m)
> > > @@ -698,7 +699,8 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
> > > int this_err;
> > > i9xx_calc_dpll_params(refclk, &clock);
> > > - if (!intel_PLL_is_valid(dev, limit,
> > > + if (!intel_PLL_is_valid(to_i915(dev),
> > > + limit,
> > > &clock))
> > > continue;
> > > if (match_clock &&
> > > @@ -753,7 +755,8 @@ pnv_find_best_dpll(const struct intel_limit *limit,
> > > int this_err;
> > > pnv_calc_dpll_params(refclk, &clock);
> > > - if (!intel_PLL_is_valid(dev, limit,
> > > + if (!intel_PLL_is_valid(to_i915(dev),
> > > + limit,
> > > &clock))
> > > continue;
> > > if (match_clock &&
> > > @@ -813,7 +816,8 @@ g4x_find_best_dpll(const struct intel_limit *limit,
> > > int this_err;
> > > i9xx_calc_dpll_params(refclk, &clock);
> > > - if (!intel_PLL_is_valid(dev, limit,
> > > + if (!intel_PLL_is_valid(to_i915(dev),
> > > + limit,
> > > &clock))
> > > continue;
> > > @@ -909,7 +913,8 @@ vlv_find_best_dpll(const struct intel_limit *limit,
> > > vlv_calc_dpll_params(refclk, &clock);
> > > - if (!intel_PLL_is_valid(dev, limit,
> > > + if (!intel_PLL_is_valid(to_i915(dev),
> > > + limit,
> > > &clock))
> > > continue;
> > > @@ -977,7 +982,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
> > > chv_calc_dpll_params(refclk, &clock);
> > > - if (!intel_PLL_is_valid(dev, limit, &clock))
> > > + if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
> > > continue;
> > > if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
> > > @@ -5852,7 +5857,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> > > max_cdclk = 308571;
> > > dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
> > > - } else if (IS_BROXTON(dev)) {
> > > + } else if (IS_BROXTON(dev_priv)) {
> > > dev_priv->max_cdclk_freq = 624000;
> > > } else if (IS_BROADWELL(dev_priv)) {
> > > /*
> > > @@ -10650,7 +10655,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
> > > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > > skylake_get_ddi_pll(dev_priv, port, pipe_config);
> > > - else if (IS_BROXTON(dev))
> > > + else if (IS_BROXTON(dev_priv))
> > > bxt_get_ddi_pll(dev_priv, port, pipe_config);
> > > else
> > > haswell_get_ddi_pll(dev_priv, port, pipe_config);
> > > @@ -12808,7 +12813,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> > > DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
> > > DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
> > > - if (IS_BROXTON(dev)) {
> > > + if (IS_BROXTON(dev_priv)) {
> > > DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
> > > "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
> > > "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
> > > @@ -15401,7 +15406,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> > > if (intel_crt_present(dev))
> > > intel_crt_init(dev);
> > > - if (IS_BROXTON(dev)) {
> > > + if (IS_BROXTON(dev_priv)) {
> > > /*
> > > * FIXME: Broxton doesn't support port detection via the
> > > * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index 02e74c467a55..b6c8b25ee1d4 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -571,7 +571,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> > > struct intel_encoder *encoder;
> > > if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> > > - !IS_BROXTON(dev)))
> > > + !IS_BROXTON(dev_priv)))
> > > return;
> > > /*
> > > @@ -591,7 +591,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> > > continue;
> > > intel_dp = enc_to_intel_dp(&encoder->base);
> > > - if (IS_BROXTON(dev))
> > > + if (IS_BROXTON(dev_priv))
> > > intel_dp->pps_reset = true;
> > > else
> > > intel_dp->pps_pipe = INVALID_PIPE;
> > > @@ -2981,7 +2981,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> > > struct drm_i915_private *dev_priv = to_i915(dev);
> > > enum port port = dp_to_dig_port(intel_dp)->port;
> > > - if (IS_BROXTON(dev))
> > > + if (IS_BROXTON(dev_priv))
> > > return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> > > else if (INTEL_INFO(dev)->gen >= 9) {
> > > if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> > > @@ -3344,7 +3344,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> > > if (HAS_DDI(dev_priv)) {
> > > signal_levels = ddi_signal_levels(intel_dp);
> > > - if (IS_BROXTON(dev))
> > > + if (IS_BROXTON(dev_priv))
> > > signal_levels = 0;
> > > else
> > > mask = DDI_BUF_EMP_MASK;
> > > @@ -5072,7 +5072,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> > > (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> > > /* Compute the divisor for the pp clock, simply match the Bspec
> > > * formula. */
> > > - if (IS_BROXTON(dev)) {
> > > + if (IS_BROXTON(dev_priv)) {
> > > pp_div = I915_READ(regs.pp_ctrl);
> > > pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> > > pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> > > @@ -5098,7 +5098,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> > > I915_WRITE(regs.pp_on, pp_on);
> > > I915_WRITE(regs.pp_off, pp_off);
> > > - if (IS_BROXTON(dev))
> > > + if (IS_BROXTON(dev_priv))
> > > I915_WRITE(regs.pp_ctrl, pp_div);
> > > else
> > > I915_WRITE(regs.pp_div, pp_div);
> > > @@ -5106,7 +5106,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> > > DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> > > I915_READ(regs.pp_on),
> > > I915_READ(regs.pp_off),
> > > - IS_BROXTON(dev) ?
> > > + IS_BROXTON(dev_priv) ?
> > > (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> > > I915_READ(regs.pp_div));
> > > }
> > > @@ -5715,7 +5715,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> > > break;
> > > case PORT_B:
> > > intel_encoder->hpd_pin = HPD_PORT_B;
> > > - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> > > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> > > intel_encoder->hpd_pin = HPD_PORT_A;
> > > break;
> > > case PORT_C:
> > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > index 7cf9d91c0746..605d0b509f24 100644
> > > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > > @@ -1853,7 +1853,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> > > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> > > dpll_mgr = &skl_pll_mgr;
> > > - else if (IS_BROXTON(dev))
> > > + else if (IS_BROXTON(dev_priv))
> > > dpll_mgr = &bxt_pll_mgr;
> > > else if (HAS_DDI(dev_priv))
> > > dpll_mgr = &hsw_pll_mgr;
> > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> > > index 5b1e445a80d0..48e8dd108f4f 100644
> > > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > > @@ -437,11 +437,11 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
> > > static void intel_dsi_device_ready(struct intel_encoder *encoder)
> > > {
> > > - struct drm_device *dev = encoder->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> > > + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > vlv_dsi_device_ready(encoder);
> > > - else if (IS_BROXTON(dev))
> > > + else if (IS_BROXTON(dev_priv))
> > > bxt_dsi_device_ready(encoder);
> > > }
> > > @@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
> > > }
> > > for_each_dsi_port(port, intel_dsi->ports) {
> > > - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
> > > + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> > > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> > > u32 temp;
> > > @@ -494,7 +494,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
> > > enum port port;
> > > for_each_dsi_port(port, intel_dsi->ports) {
> > > - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
> > > + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> > > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> > > u32 temp;
> > > @@ -656,7 +656,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
> > > static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> > > {
> > > - struct drm_device *dev = encoder->base.dev;
> > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> > > enum port port;
> > > @@ -664,7 +663,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> > > DRM_DEBUG_KMS("\n");
> > > for_each_dsi_port(port, intel_dsi->ports) {
> > > /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
> > > - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
> > > + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> > > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
> > > u32 val;
> > > @@ -762,7 +761,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> > > /* XXX: this only works for one DSI output */
> > > for_each_dsi_port(port, intel_dsi->ports) {
> > > - i915_reg_t ctrl_reg = IS_BROXTON(dev) ?
> > > + i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
> > > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> > > bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
> > > @@ -970,11 +969,11 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> > > static void intel_dsi_get_config(struct intel_encoder *encoder,
> > > struct intel_crtc_state *pipe_config)
> > > {
> > > - struct drm_device *dev = encoder->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > u32 pclk;
> > > DRM_DEBUG_KMS("\n");
> > > - if (IS_BROXTON(dev))
> > > + if (IS_BROXTON(dev_priv))
> > > bxt_dsi_get_pipe_config(encoder, pipe_config);
> > > pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
> > > @@ -1066,7 +1065,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
> > > hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
> > > for_each_dsi_port(port, intel_dsi->ports) {
> > > - if (IS_BROXTON(dev)) {
> > > + if (IS_BROXTON(dev_priv)) {
> > > /*
> > > * Program hdisplay and vdisplay on MIPI transcoder.
> > > * This is different from calculated hactive and
> > > @@ -1153,7 +1152,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> > > tmp &= ~READ_REQUEST_PRIORITY_MASK;
> > > I915_WRITE(MIPI_CTRL(port), tmp |
> > > READ_REQUEST_PRIORITY_HIGH);
> > > - } else if (IS_BROXTON(dev)) {
> > > + } else if (IS_BROXTON(dev_priv)) {
> > > enum pipe pipe = intel_crtc->pipe;
> > > tmp = I915_READ(MIPI_CTRL(port));
> > > @@ -1242,7 +1241,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> > > I915_WRITE(MIPI_INIT_COUNT(port),
> > > txclkesc(intel_dsi->escape_clk_div, 100));
> > > - if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
> > > + if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
> > > /*
> > > * BXT spec says write MIPI_INIT_COUNT for
> > > * both the ports, even if only one is
> > > @@ -1452,7 +1451,7 @@ void intel_dsi_init(struct drm_device *dev)
> > > if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> > > dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> > > - } else if (IS_BROXTON(dev)) {
> > > + } else if (IS_BROXTON(dev_priv)) {
> > > dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> > > } else {
> > > DRM_ERROR("Unsupported Mipi device to reg base");
> > > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > > index 6ab58a01b18e..56eff6004bc0 100644
> > > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> > > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> > > @@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> > > u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> > > struct intel_crtc_state *config)
> > > {
> > > - if (IS_BROXTON(encoder->base.dev))
> > > + if (IS_BROXTON(to_i915(encoder->base.dev)))
> > > return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
> > > else
> > > return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
> > > @@ -515,11 +515,11 @@ bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
> > > int intel_compute_dsi_pll(struct intel_encoder *encoder,
> > > struct intel_crtc_state *config)
> > > {
> > > - struct drm_device *dev = encoder->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> > > + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > return vlv_compute_dsi_pll(encoder, config);
> > > - else if (IS_BROXTON(dev))
> > > + else if (IS_BROXTON(dev_priv))
> > > return bxt_compute_dsi_pll(encoder, config);
> > > return -ENODEV;
> > > @@ -528,21 +528,21 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
> > > void intel_enable_dsi_pll(struct intel_encoder *encoder,
> > > const struct intel_crtc_state *config)
> > > {
> > > - struct drm_device *dev = encoder->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> > > + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > vlv_enable_dsi_pll(encoder, config);
> > > - else if (IS_BROXTON(dev))
> > > + else if (IS_BROXTON(dev_priv))
> > > bxt_enable_dsi_pll(encoder, config);
> > > }
> > > void intel_disable_dsi_pll(struct intel_encoder *encoder)
> > > {
> > > - struct drm_device *dev = encoder->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> > > + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > vlv_disable_dsi_pll(encoder);
> > > - else if (IS_BROXTON(dev))
> > > + else if (IS_BROXTON(dev_priv))
> > > bxt_disable_dsi_pll(encoder);
> > > }
> > > @@ -564,10 +564,10 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> > > void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> > > {
> > > - struct drm_device *dev = encoder->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > - if (IS_BROXTON(dev))
> > > + if (IS_BROXTON(dev_priv))
> > > bxt_dsi_reset_clocks(encoder, port);
> > > - else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> > > + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > vlv_dsi_reset_clocks(encoder, port);
> > > }
> > > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > index 182204373931..5d5d609ed5e9 100644
> > > --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> > > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> > > @@ -376,16 +376,16 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> > > I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
> > > /* WaDisableMinuteIaClockGating:bxt */
> > > - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> > > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> > > I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
> > > ~GUC_ENABLE_MIA_CLOCK_GATING));
> > > }
> > > /* WaC6DisallowByGfxPause:bxt */
> > > - if (IS_BXT_REVID(dev, 0, BXT_REVID_B0))
> > > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
> > > I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
> > > - if (IS_BROXTON(dev))
> > > + if (IS_BROXTON(dev_priv))
> > > I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> > > else
> > > I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> > > @@ -730,7 +730,7 @@ void intel_guc_init(struct drm_device *dev)
> > > fw_path = I915_SKL_GUC_UCODE;
> > > guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
> > > guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
> > > - } else if (IS_BROXTON(dev)) {
> > > + } else if (IS_BROXTON(dev_priv)) {
> > > fw_path = I915_BXT_GUC_UCODE;
> > > guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
> > > guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
> > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> > > index 6607c4e3c36c..f6562451c47e 100644
> > > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > > @@ -1241,7 +1241,7 @@ static enum drm_mode_status
> > > hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> > > int clock, bool respect_downstream_limits)
> > > {
> > > - struct drm_device *dev = intel_hdmi_to_dev(hdmi);
> > > + struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
> > > if (clock < 25000)
> > > return MODE_CLOCK_LOW;
> > > @@ -1249,11 +1249,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> > > return MODE_CLOCK_HIGH;
> > > /* BXT DPLL can't generate 223-240 MHz */
> > > - if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
> > > + if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
> > > return MODE_CLOCK_RANGE;
> > > /* CHV DPLL can't generate 216-240 MHz */
> > > - if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
> > > + if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
> > > return MODE_CLOCK_RANGE;
> > > return MODE_OK;
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 025fbd522819..e4bb85c9c6e1 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -2596,7 +2596,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
> > > if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> > > skl_display_core_init(dev_priv, resume);
> > > - } else if (IS_BROXTON(dev)) {
> > > + } else if (IS_BROXTON(dev_priv)) {
> > > bxt_display_core_init(dev_priv, resume);
> > > } else if (IS_CHERRYVIEW(dev)) {
> > > mutex_lock(&power_domains->lock);
> > > --
> > > 2.7.4
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* [PATCH v3 13/19] drm/i915: Make IS_BROXTON only take dev_priv
2016-10-12 12:50 ` David Weinehall
@ 2016-10-13 9:44 ` Tvrtko Ursulin
2016-10-13 9:53 ` David Weinehall
0 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-13 9:44 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 1392 bytes of .rodata strings.
Also change a few function/macro prototypes in i915_gem_gtt.c
from dev to dev_priv where it made more sense to do so.
v2: Add parantheses around dev_priv. (Ville Syrjala)
v3: Mention function prototype changes. (David Weinhall)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: David Weinehall <david.weinehall@linux.intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Jani Nikula <jani.nikula@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 5 +++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++++++++++++++++----------------
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++-----------
drivers/gpu/drm/i915/intel_dp.c | 16 ++++++-------
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/intel_dsi.c | 27 +++++++++++-----------
drivers/gpu/drm/i915/intel_dsi_pll.c | 26 ++++++++++-----------
drivers/gpu/drm/i915/intel_guc_loader.c | 8 +++----
drivers/gpu/drm/i915/intel_hdmi.c | 6 ++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
13 files changed, 89 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d854ea4a7e92..18af6d1ccec9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2437,7 +2437,7 @@ static int intel_runtime_resume(struct device *kdev)
if (IS_GEN6(dev_priv))
intel_init_pch_refclk(dev);
- if (IS_BROXTON(dev)) {
+ if (IS_BROXTON(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
if (dev_priv->csr.dmc_payload &&
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 297f6a103d54..9ad79d196a73 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2667,7 +2667,7 @@ struct drm_i915_cmd_table {
#define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
#define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
-#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
+#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
#define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
@@ -2727,7 +2727,8 @@ struct drm_i915_cmd_table {
#define BXT_REVID_B0 0x3
#define BXT_REVID_C0 0x9
-#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
+#define IS_BXT_REVID(dev_priv, since, until) \
+ (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
#define KBL_REVID_A0 0x0
#define KBL_REVID_B0 0x1
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0b4702cedad1..d215db5e6d38 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p)
/* We use the flushing unmap only with ppgtt structures:
* page directories, page tables and scratch pages.
*/
-static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
+static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
{
/* There are only few exceptions for gen >=6. chv and bxt.
* And we are not sure about the latter so play safe for now.
*/
- if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
+ if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
drm_clflush_virt_range(vaddr, PAGE_SIZE);
kunmap_atomic(vaddr);
}
#define kmap_px(px) kmap_page_dma(px_base(px))
-#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
+#define kunmap_px(ppgtt, vaddr) \
+ kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr))
#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
-#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
-#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
+#define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v))
+#define fill32_px(dev_priv, px, v) \
+ fill_page_dma_32((dev_priv), px_base(px), (v))
-static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
- const uint64_t val)
+static void fill_page_dma(struct drm_i915_private *dev_priv,
+ struct i915_page_dma *p, const uint64_t val)
{
int i;
uint64_t * const vaddr = kmap_page_dma(p);
@@ -401,17 +403,17 @@ static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
for (i = 0; i < 512; i++)
vaddr[i] = val;
- kunmap_page_dma(dev, vaddr);
+ kunmap_page_dma(dev_priv, vaddr);
}
-static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
- const uint32_t val32)
+static void fill_page_dma_32(struct drm_i915_private *dev_priv,
+ struct i915_page_dma *p, const uint32_t val32)
{
uint64_t v = val32;
v = v << 32 | val32;
- fill_page_dma(dev, p, v);
+ fill_page_dma(dev_priv, p, v);
}
static int
@@ -474,7 +476,7 @@ static void gen8_initialize_pt(struct i915_address_space *vm,
scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
I915_CACHE_LLC, true);
- fill_px(vm->dev, pt, scratch_pte);
+ fill_px(to_i915(vm->dev), pt, scratch_pte);
}
static void gen6_initialize_pt(struct i915_address_space *vm,
@@ -487,7 +489,7 @@ static void gen6_initialize_pt(struct i915_address_space *vm,
scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
I915_CACHE_LLC, true, 0);
- fill32_px(vm->dev, pt, scratch_pte);
+ fill32_px(to_i915(vm->dev), pt, scratch_pte);
}
static struct i915_page_directory *alloc_pd(struct drm_device *dev)
@@ -534,7 +536,7 @@ static void gen8_initialize_pd(struct i915_address_space *vm,
scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
- fill_px(vm->dev, pd, scratch_pde);
+ fill_px(to_i915(vm->dev), pd, scratch_pde);
}
static int __pdp_init(struct drm_device *dev,
@@ -615,7 +617,7 @@ static void gen8_initialize_pdp(struct i915_address_space *vm,
scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
- fill_px(vm->dev, pdp, scratch_pdpe);
+ fill_px(to_i915(vm->dev), pdp, scratch_pdpe);
}
static void gen8_initialize_pml4(struct i915_address_space *vm,
@@ -626,7 +628,7 @@ static void gen8_initialize_pml4(struct i915_address_space *vm,
scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
I915_CACHE_LLC);
- fill_px(vm->dev, pml4, scratch_pml4e);
+ fill_px(to_i915(vm->dev), pml4, scratch_pml4e);
}
static void
@@ -2135,7 +2137,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
else if (IS_SKYLAKE(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
}
@@ -2912,7 +2914,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
* resort to an uncached mapping. The WC issue is easily caught by the
* readback check when writing GTT PTE entries.
*/
- if (IS_BROXTON(ggtt->base.dev))
+ if (IS_BROXTON(to_i915(ggtt->base.dev)))
ggtt->gsm = ioremap_nocache(phys_addr, size);
else
ggtt->gsm = ioremap_wc(phys_addr, size);
@@ -3284,7 +3286,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
ggtt->base.closed = false;
if (INTEL_INFO(dev)->gen >= 8) {
- if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
+ if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
chv_setup_private_ppat(dev_priv);
else
bdw_setup_private_ppat(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ae43d5ebd76a..a9a73c4b4933 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4597,7 +4597,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev->driver->irq_uninstall = gen8_irq_uninstall;
dev->driver->enable_vblank = gen8_enable_vblank;
dev->driver->disable_vblank = gen8_disable_vblank;
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 07164e250adf..a76afd7a6616 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2509,7 +2509,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
* configuration so that we use the proper lane count for our
* calculations.
*/
- if (IS_BROXTON(dev) && port == PORT_A) {
+ if (IS_BROXTON(dev_priv) && port == PORT_A) {
if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
@@ -2533,7 +2533,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
* On BXT A0/A1, sw needs to activate DDIA HPD logic and
* interrupts to check the external panel connection.
*/
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) && port == PORT_B)
dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
else
dev_priv->hotplug.irq_port[port] = intel_dig_port;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2c7899000b74..3d2bd5504ab4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -600,7 +600,7 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
* the given connectors.
*/
-static bool intel_PLL_is_valid(struct drm_device *dev,
+static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
const struct intel_limit *limit,
const struct dpll *clock)
{
@@ -613,12 +613,13 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
INTELPllInvalid("m1 out of range\n");
- if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
- !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
+ if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
+ !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
if (clock->m1 <= clock->m2)
INTELPllInvalid("m1 <= m2\n");
- if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
+ if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
+ !IS_BROXTON(dev_priv)) {
if (clock->p < limit->p.min || limit->p.max < clock->p)
INTELPllInvalid("p out of range\n");
if (clock->m < limit->m.min || limit->m.max < clock->m)
@@ -698,7 +699,8 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
int this_err;
i9xx_calc_dpll_params(refclk, &clock);
- if (!intel_PLL_is_valid(dev, limit,
+ if (!intel_PLL_is_valid(to_i915(dev),
+ limit,
&clock))
continue;
if (match_clock &&
@@ -753,7 +755,8 @@ pnv_find_best_dpll(const struct intel_limit *limit,
int this_err;
pnv_calc_dpll_params(refclk, &clock);
- if (!intel_PLL_is_valid(dev, limit,
+ if (!intel_PLL_is_valid(to_i915(dev),
+ limit,
&clock))
continue;
if (match_clock &&
@@ -813,7 +816,8 @@ g4x_find_best_dpll(const struct intel_limit *limit,
int this_err;
i9xx_calc_dpll_params(refclk, &clock);
- if (!intel_PLL_is_valid(dev, limit,
+ if (!intel_PLL_is_valid(to_i915(dev),
+ limit,
&clock))
continue;
@@ -909,7 +913,8 @@ vlv_find_best_dpll(const struct intel_limit *limit,
vlv_calc_dpll_params(refclk, &clock);
- if (!intel_PLL_is_valid(dev, limit,
+ if (!intel_PLL_is_valid(to_i915(dev),
+ limit,
&clock))
continue;
@@ -977,7 +982,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
chv_calc_dpll_params(refclk, &clock);
- if (!intel_PLL_is_valid(dev, limit, &clock))
+ if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
continue;
if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
@@ -5850,7 +5855,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
max_cdclk = 308571;
dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
- } else if (IS_BROXTON(dev)) {
+ } else if (IS_BROXTON(dev_priv)) {
dev_priv->max_cdclk_freq = 624000;
} else if (IS_BROADWELL(dev_priv)) {
/*
@@ -10648,7 +10653,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
skylake_get_ddi_pll(dev_priv, port, pipe_config);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
bxt_get_ddi_pll(dev_priv, port, pipe_config);
else
haswell_get_ddi_pll(dev_priv, port, pipe_config);
@@ -12806,7 +12811,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
- if (IS_BROXTON(dev)) {
+ if (IS_BROXTON(dev_priv)) {
DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
"pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
"pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
@@ -15399,7 +15404,7 @@ static void intel_setup_outputs(struct drm_device *dev)
if (intel_crt_present(dev))
intel_crt_init(dev);
- if (IS_BROXTON(dev)) {
+ if (IS_BROXTON(dev_priv)) {
/*
* FIXME: Broxton doesn't support port detection via the
* DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 02e74c467a55..b6c8b25ee1d4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -571,7 +571,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
struct intel_encoder *encoder;
if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
- !IS_BROXTON(dev)))
+ !IS_BROXTON(dev_priv)))
return;
/*
@@ -591,7 +591,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
continue;
intel_dp = enc_to_intel_dp(&encoder->base);
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
intel_dp->pps_reset = true;
else
intel_dp->pps_pipe = INVALID_PIPE;
@@ -2981,7 +2981,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = to_i915(dev);
enum port port = dp_to_dig_port(intel_dp)->port;
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (INTEL_INFO(dev)->gen >= 9) {
if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
@@ -3344,7 +3344,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
if (HAS_DDI(dev_priv)) {
signal_levels = ddi_signal_levels(intel_dp);
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
signal_levels = 0;
else
mask = DDI_BUF_EMP_MASK;
@@ -5072,7 +5072,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
/* Compute the divisor for the pp clock, simply match the Bspec
* formula. */
- if (IS_BROXTON(dev)) {
+ if (IS_BROXTON(dev_priv)) {
pp_div = I915_READ(regs.pp_ctrl);
pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5098,7 +5098,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
I915_WRITE(regs.pp_on, pp_on);
I915_WRITE(regs.pp_off, pp_off);
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
I915_WRITE(regs.pp_ctrl, pp_div);
else
I915_WRITE(regs.pp_div, pp_div);
@@ -5106,7 +5106,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
I915_READ(regs.pp_on),
I915_READ(regs.pp_off),
- IS_BROXTON(dev) ?
+ IS_BROXTON(dev_priv) ?
(I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
I915_READ(regs.pp_div));
}
@@ -5715,7 +5715,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
break;
case PORT_B:
intel_encoder->hpd_pin = HPD_PORT_B;
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
intel_encoder->hpd_pin = HPD_PORT_A;
break;
case PORT_C:
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 7cf9d91c0746..605d0b509f24 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1853,7 +1853,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
dpll_mgr = &skl_pll_mgr;
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
dpll_mgr = &bxt_pll_mgr;
else if (HAS_DDI(dev_priv))
dpll_mgr = &hsw_pll_mgr;
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 5b1e445a80d0..48e8dd108f4f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -437,11 +437,11 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
static void intel_dsi_device_ready(struct intel_encoder *encoder)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_dsi_device_ready(encoder);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
bxt_dsi_device_ready(encoder);
}
@@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
}
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t port_ctrl = IS_BROXTON(dev) ?
+ i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
u32 temp;
@@ -494,7 +494,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
enum port port;
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t port_ctrl = IS_BROXTON(dev) ?
+ i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
u32 temp;
@@ -656,7 +656,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
{
- struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
enum port port;
@@ -664,7 +663,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
for_each_dsi_port(port, intel_dsi->ports) {
/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
- i915_reg_t port_ctrl = IS_BROXTON(dev) ?
+ i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
u32 val;
@@ -762,7 +761,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
/* XXX: this only works for one DSI output */
for_each_dsi_port(port, intel_dsi->ports) {
- i915_reg_t ctrl_reg = IS_BROXTON(dev) ?
+ i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
@@ -970,11 +969,11 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
static void intel_dsi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 pclk;
DRM_DEBUG_KMS("\n");
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
bxt_dsi_get_pipe_config(encoder, pipe_config);
pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
@@ -1066,7 +1065,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
for_each_dsi_port(port, intel_dsi->ports) {
- if (IS_BROXTON(dev)) {
+ if (IS_BROXTON(dev_priv)) {
/*
* Program hdisplay and vdisplay on MIPI transcoder.
* This is different from calculated hactive and
@@ -1153,7 +1152,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
tmp &= ~READ_REQUEST_PRIORITY_MASK;
I915_WRITE(MIPI_CTRL(port), tmp |
READ_REQUEST_PRIORITY_HIGH);
- } else if (IS_BROXTON(dev)) {
+ } else if (IS_BROXTON(dev_priv)) {
enum pipe pipe = intel_crtc->pipe;
tmp = I915_READ(MIPI_CTRL(port));
@@ -1242,7 +1241,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
I915_WRITE(MIPI_INIT_COUNT(port),
txclkesc(intel_dsi->escape_clk_div, 100));
- if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
+ if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
/*
* BXT spec says write MIPI_INIT_COUNT for
* both the ports, even if only one is
@@ -1452,7 +1451,7 @@ void intel_dsi_init(struct drm_device *dev)
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
- } else if (IS_BROXTON(dev)) {
+ } else if (IS_BROXTON(dev_priv)) {
dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
} else {
DRM_ERROR("Unsupported Mipi device to reg base");
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 6ab58a01b18e..56eff6004bc0 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
struct intel_crtc_state *config)
{
- if (IS_BROXTON(encoder->base.dev))
+ if (IS_BROXTON(to_i915(encoder->base.dev)))
return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
else
return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
@@ -515,11 +515,11 @@ bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
int intel_compute_dsi_pll(struct intel_encoder *encoder,
struct intel_crtc_state *config)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return vlv_compute_dsi_pll(encoder, config);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
return bxt_compute_dsi_pll(encoder, config);
return -ENODEV;
@@ -528,21 +528,21 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
void intel_enable_dsi_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *config)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_enable_dsi_pll(encoder, config);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
bxt_enable_dsi_pll(encoder, config);
}
void intel_disable_dsi_pll(struct intel_encoder *encoder)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_disable_dsi_pll(encoder);
- else if (IS_BROXTON(dev))
+ else if (IS_BROXTON(dev_priv))
bxt_disable_dsi_pll(encoder);
}
@@ -564,10 +564,10 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
{
- struct drm_device *dev = encoder->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
bxt_dsi_reset_clocks(encoder, port);
- else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_dsi_reset_clocks(encoder, port);
}
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 182204373931..5d5d609ed5e9 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -376,16 +376,16 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
/* WaDisableMinuteIaClockGating:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
~GUC_ENABLE_MIA_CLOCK_GATING));
}
/* WaC6DisallowByGfxPause:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_B0))
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(dev_priv))
I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
else
I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
@@ -730,7 +730,7 @@ void intel_guc_init(struct drm_device *dev)
fw_path = I915_SKL_GUC_UCODE;
guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
- } else if (IS_BROXTON(dev)) {
+ } else if (IS_BROXTON(dev_priv)) {
fw_path = I915_BXT_GUC_UCODE;
guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6607c4e3c36c..f6562451c47e 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1241,7 +1241,7 @@ static enum drm_mode_status
hdmi_port_clock_valid(struct intel_hdmi *hdmi,
int clock, bool respect_downstream_limits)
{
- struct drm_device *dev = intel_hdmi_to_dev(hdmi);
+ struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
if (clock < 25000)
return MODE_CLOCK_LOW;
@@ -1249,11 +1249,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
return MODE_CLOCK_HIGH;
/* BXT DPLL can't generate 223-240 MHz */
- if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
+ if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
return MODE_CLOCK_RANGE;
/* CHV DPLL can't generate 216-240 MHz */
- if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
+ if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
return MODE_CLOCK_RANGE;
return MODE_OK;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 025fbd522819..e4bb85c9c6e1 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2596,7 +2596,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
skl_display_core_init(dev_priv, resume);
- } else if (IS_BROXTON(dev)) {
+ } else if (IS_BROXTON(dev_priv)) {
bxt_display_core_init(dev_priv, resume);
} else if (IS_CHERRYVIEW(dev)) {
mutex_lock(&power_domains->lock);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v3 13/19] drm/i915: Make IS_BROXTON only take dev_priv
2016-10-13 9:44 ` [PATCH v3 " Tvrtko Ursulin
@ 2016-10-13 9:53 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-13 9:53 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Thu, Oct 13, 2016 at 10:44:44AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 1392 bytes of .rodata strings.
>
> Also change a few function/macro prototypes in i915_gem_gtt.c
> from dev to dev_priv where it made more sense to do so.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> v3: Mention function prototype changes. (David Weinhall)
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: David Weinehall <david.weinehall@linux.intel.com>
> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> Acked-by: Jani Nikula <jani.nikula@linux.intel.com>
> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 5 +++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++++++++++++++++----------------
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++-----------
> drivers/gpu/drm/i915/intel_dp.c | 16 ++++++-------
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/intel_dsi.c | 27 +++++++++++-----------
> drivers/gpu/drm/i915/intel_dsi_pll.c | 26 ++++++++++-----------
> drivers/gpu/drm/i915/intel_guc_loader.c | 8 +++----
> drivers/gpu/drm/i915/intel_hdmi.c | 6 ++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> 13 files changed, 89 insertions(+), 82 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d854ea4a7e92..18af6d1ccec9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2437,7 +2437,7 @@ static int intel_runtime_resume(struct device *kdev)
> if (IS_GEN6(dev_priv))
> intel_init_pch_refclk(dev);
>
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> bxt_disable_dc9(dev_priv);
> bxt_display_core_init(dev_priv, true);
> if (dev_priv->csr.dmc_payload &&
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 297f6a103d54..9ad79d196a73 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2667,7 +2667,7 @@ struct drm_i915_cmd_table {
> #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
> #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
> -#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
> +#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
> #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
> #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> @@ -2727,7 +2727,8 @@ struct drm_i915_cmd_table {
> #define BXT_REVID_B0 0x3
> #define BXT_REVID_C0 0x9
>
> -#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
> +#define IS_BXT_REVID(dev_priv, since, until) \
> + (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
>
> #define KBL_REVID_A0 0x0
> #define KBL_REVID_B0 0x1
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 0b4702cedad1..d215db5e6d38 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p)
> /* We use the flushing unmap only with ppgtt structures:
> * page directories, page tables and scratch pages.
> */
> -static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
> +static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
> {
> /* There are only few exceptions for gen >=6. chv and bxt.
> * And we are not sure about the latter so play safe for now.
> */
> - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
> + if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> drm_clflush_virt_range(vaddr, PAGE_SIZE);
>
> kunmap_atomic(vaddr);
> }
>
> #define kmap_px(px) kmap_page_dma(px_base(px))
> -#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
> +#define kunmap_px(ppgtt, vaddr) \
> + kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr))
>
> #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
> #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
> -#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
> -#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
> +#define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v))
> +#define fill32_px(dev_priv, px, v) \
> + fill_page_dma_32((dev_priv), px_base(px), (v))
>
> -static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
> - const uint64_t val)
> +static void fill_page_dma(struct drm_i915_private *dev_priv,
> + struct i915_page_dma *p, const uint64_t val)
> {
> int i;
> uint64_t * const vaddr = kmap_page_dma(p);
> @@ -401,17 +403,17 @@ static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
> for (i = 0; i < 512; i++)
> vaddr[i] = val;
>
> - kunmap_page_dma(dev, vaddr);
> + kunmap_page_dma(dev_priv, vaddr);
> }
>
> -static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
> - const uint32_t val32)
> +static void fill_page_dma_32(struct drm_i915_private *dev_priv,
> + struct i915_page_dma *p, const uint32_t val32)
> {
> uint64_t v = val32;
>
> v = v << 32 | val32;
>
> - fill_page_dma(dev, p, v);
> + fill_page_dma(dev_priv, p, v);
> }
>
> static int
> @@ -474,7 +476,7 @@ static void gen8_initialize_pt(struct i915_address_space *vm,
> scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
> I915_CACHE_LLC, true);
>
> - fill_px(vm->dev, pt, scratch_pte);
> + fill_px(to_i915(vm->dev), pt, scratch_pte);
> }
>
> static void gen6_initialize_pt(struct i915_address_space *vm,
> @@ -487,7 +489,7 @@ static void gen6_initialize_pt(struct i915_address_space *vm,
> scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
> I915_CACHE_LLC, true, 0);
>
> - fill32_px(vm->dev, pt, scratch_pte);
> + fill32_px(to_i915(vm->dev), pt, scratch_pte);
> }
>
> static struct i915_page_directory *alloc_pd(struct drm_device *dev)
> @@ -534,7 +536,7 @@ static void gen8_initialize_pd(struct i915_address_space *vm,
>
> scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
>
> - fill_px(vm->dev, pd, scratch_pde);
> + fill_px(to_i915(vm->dev), pd, scratch_pde);
> }
>
> static int __pdp_init(struct drm_device *dev,
> @@ -615,7 +617,7 @@ static void gen8_initialize_pdp(struct i915_address_space *vm,
>
> scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
>
> - fill_px(vm->dev, pdp, scratch_pdpe);
> + fill_px(to_i915(vm->dev), pdp, scratch_pdpe);
> }
>
> static void gen8_initialize_pml4(struct i915_address_space *vm,
> @@ -626,7 +628,7 @@ static void gen8_initialize_pml4(struct i915_address_space *vm,
> scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
> I915_CACHE_LLC);
>
> - fill_px(vm->dev, pml4, scratch_pml4e);
> + fill_px(to_i915(vm->dev), pml4, scratch_pml4e);
> }
>
> static void
> @@ -2135,7 +2137,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> else if (IS_SKYLAKE(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> }
>
> @@ -2912,7 +2914,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
> * resort to an uncached mapping. The WC issue is easily caught by the
> * readback check when writing GTT PTE entries.
> */
> - if (IS_BROXTON(ggtt->base.dev))
> + if (IS_BROXTON(to_i915(ggtt->base.dev)))
> ggtt->gsm = ioremap_nocache(phys_addr, size);
> else
> ggtt->gsm = ioremap_wc(phys_addr, size);
> @@ -3284,7 +3286,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
> ggtt->base.closed = false;
>
> if (INTEL_INFO(dev)->gen >= 8) {
> - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
> + if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> chv_setup_private_ppat(dev_priv);
> else
> bdw_setup_private_ppat(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index ae43d5ebd76a..a9a73c4b4933 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4597,7 +4597,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev->driver->irq_uninstall = gen8_irq_uninstall;
> dev->driver->enable_vblank = gen8_enable_vblank;
> dev->driver->disable_vblank = gen8_disable_vblank;
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
> dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 07164e250adf..a76afd7a6616 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2509,7 +2509,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
> * configuration so that we use the proper lane count for our
> * calculations.
> */
> - if (IS_BROXTON(dev) && port == PORT_A) {
> + if (IS_BROXTON(dev_priv) && port == PORT_A) {
> if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> @@ -2533,7 +2533,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
> * On BXT A0/A1, sw needs to activate DDIA HPD logic and
> * interrupts to check the external panel connection.
> */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) && port == PORT_B)
> dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
> else
> dev_priv->hotplug.irq_port[port] = intel_dig_port;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2c7899000b74..3d2bd5504ab4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -600,7 +600,7 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
> * the given connectors.
> */
>
> -static bool intel_PLL_is_valid(struct drm_device *dev,
> +static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
> const struct intel_limit *limit,
> const struct dpll *clock)
> {
> @@ -613,12 +613,13 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
> if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
> INTELPllInvalid("m1 out of range\n");
>
> - if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
> - !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
> + if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> + !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
> if (clock->m1 <= clock->m2)
> INTELPllInvalid("m1 <= m2\n");
>
> - if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
> + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> + !IS_BROXTON(dev_priv)) {
> if (clock->p < limit->p.min || limit->p.max < clock->p)
> INTELPllInvalid("p out of range\n");
> if (clock->m < limit->m.min || limit->m.max < clock->m)
> @@ -698,7 +699,8 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
> int this_err;
>
> i9xx_calc_dpll_params(refclk, &clock);
> - if (!intel_PLL_is_valid(dev, limit,
> + if (!intel_PLL_is_valid(to_i915(dev),
> + limit,
> &clock))
> continue;
> if (match_clock &&
> @@ -753,7 +755,8 @@ pnv_find_best_dpll(const struct intel_limit *limit,
> int this_err;
>
> pnv_calc_dpll_params(refclk, &clock);
> - if (!intel_PLL_is_valid(dev, limit,
> + if (!intel_PLL_is_valid(to_i915(dev),
> + limit,
> &clock))
> continue;
> if (match_clock &&
> @@ -813,7 +816,8 @@ g4x_find_best_dpll(const struct intel_limit *limit,
> int this_err;
>
> i9xx_calc_dpll_params(refclk, &clock);
> - if (!intel_PLL_is_valid(dev, limit,
> + if (!intel_PLL_is_valid(to_i915(dev),
> + limit,
> &clock))
> continue;
>
> @@ -909,7 +913,8 @@ vlv_find_best_dpll(const struct intel_limit *limit,
>
> vlv_calc_dpll_params(refclk, &clock);
>
> - if (!intel_PLL_is_valid(dev, limit,
> + if (!intel_PLL_is_valid(to_i915(dev),
> + limit,
> &clock))
> continue;
>
> @@ -977,7 +982,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
>
> chv_calc_dpll_params(refclk, &clock);
>
> - if (!intel_PLL_is_valid(dev, limit, &clock))
> + if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
> continue;
>
> if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
> @@ -5850,7 +5855,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> max_cdclk = 308571;
>
> dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> dev_priv->max_cdclk_freq = 624000;
> } else if (IS_BROADWELL(dev_priv)) {
> /*
> @@ -10648,7 +10653,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skylake_get_ddi_pll(dev_priv, port, pipe_config);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> bxt_get_ddi_pll(dev_priv, port, pipe_config);
> else
> haswell_get_ddi_pll(dev_priv, port, pipe_config);
> @@ -12806,7 +12811,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
> DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
>
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
> "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
> "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
> @@ -15399,7 +15404,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> if (intel_crt_present(dev))
> intel_crt_init(dev);
>
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> /*
> * FIXME: Broxton doesn't support port detection via the
> * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 02e74c467a55..b6c8b25ee1d4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -571,7 +571,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> struct intel_encoder *encoder;
>
> if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> - !IS_BROXTON(dev)))
> + !IS_BROXTON(dev_priv)))
> return;
>
> /*
> @@ -591,7 +591,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> continue;
>
> intel_dp = enc_to_intel_dp(&encoder->base);
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> intel_dp->pps_reset = true;
> else
> intel_dp->pps_pipe = INVALID_PIPE;
> @@ -2981,7 +2981,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum port port = dp_to_dig_port(intel_dp)->port;
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (INTEL_INFO(dev)->gen >= 9) {
> if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> @@ -3344,7 +3344,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> if (HAS_DDI(dev_priv)) {
> signal_levels = ddi_signal_levels(intel_dp);
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> signal_levels = 0;
> else
> mask = DDI_BUF_EMP_MASK;
> @@ -5072,7 +5072,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> /* Compute the divisor for the pp clock, simply match the Bspec
> * formula. */
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> pp_div = I915_READ(regs.pp_ctrl);
> pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> @@ -5098,7 +5098,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>
> I915_WRITE(regs.pp_on, pp_on);
> I915_WRITE(regs.pp_off, pp_off);
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> I915_WRITE(regs.pp_ctrl, pp_div);
> else
> I915_WRITE(regs.pp_div, pp_div);
> @@ -5106,7 +5106,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> I915_READ(regs.pp_on),
> I915_READ(regs.pp_off),
> - IS_BROXTON(dev) ?
> + IS_BROXTON(dev_priv) ?
> (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> I915_READ(regs.pp_div));
> }
> @@ -5715,7 +5715,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> break;
> case PORT_B:
> intel_encoder->hpd_pin = HPD_PORT_B;
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> intel_encoder->hpd_pin = HPD_PORT_A;
> break;
> case PORT_C:
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 7cf9d91c0746..605d0b509f24 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1853,7 +1853,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> dpll_mgr = &skl_pll_mgr;
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> dpll_mgr = &bxt_pll_mgr;
> else if (HAS_DDI(dev_priv))
> dpll_mgr = &hsw_pll_mgr;
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 5b1e445a80d0..48e8dd108f4f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -437,11 +437,11 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
>
> static void intel_dsi_device_ready(struct intel_encoder *encoder)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_device_ready(encoder);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> bxt_dsi_device_ready(encoder);
> }
>
> @@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
> + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -494,7 +494,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
> enum port port;
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
> + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -656,7 +656,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>
> static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> {
> - struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
> @@ -664,7 +663,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> DRM_DEBUG_KMS("\n");
> for_each_dsi_port(port, intel_dsi->ports) {
> /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
> - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
> + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
> u32 val;
>
> @@ -762,7 +761,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>
> /* XXX: this only works for one DSI output */
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t ctrl_reg = IS_BROXTON(dev) ?
> + i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
>
> @@ -970,11 +969,11 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> static void intel_dsi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 pclk;
> DRM_DEBUG_KMS("\n");
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> bxt_dsi_get_pipe_config(encoder, pipe_config);
>
> pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
> @@ -1066,7 +1065,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
> hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> /*
> * Program hdisplay and vdisplay on MIPI transcoder.
> * This is different from calculated hactive and
> @@ -1153,7 +1152,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> tmp &= ~READ_REQUEST_PRIORITY_MASK;
> I915_WRITE(MIPI_CTRL(port), tmp |
> READ_REQUEST_PRIORITY_HIGH);
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> enum pipe pipe = intel_crtc->pipe;
>
> tmp = I915_READ(MIPI_CTRL(port));
> @@ -1242,7 +1241,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> I915_WRITE(MIPI_INIT_COUNT(port),
> txclkesc(intel_dsi->escape_clk_div, 100));
>
> - if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
> + if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
> /*
> * BXT spec says write MIPI_INIT_COUNT for
> * both the ports, even if only one is
> @@ -1452,7 +1451,7 @@ void intel_dsi_init(struct drm_device *dev)
>
> if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> } else {
> DRM_ERROR("Unsupported Mipi device to reg base");
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 6ab58a01b18e..56eff6004bc0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> struct intel_crtc_state *config)
> {
> - if (IS_BROXTON(encoder->base.dev))
> + if (IS_BROXTON(to_i915(encoder->base.dev)))
> return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
> else
> return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
> @@ -515,11 +515,11 @@ bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
> int intel_compute_dsi_pll(struct intel_encoder *encoder,
> struct intel_crtc_state *config)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return vlv_compute_dsi_pll(encoder, config);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> return bxt_compute_dsi_pll(encoder, config);
>
> return -ENODEV;
> @@ -528,21 +528,21 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
> void intel_enable_dsi_pll(struct intel_encoder *encoder,
> const struct intel_crtc_state *config)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_enable_dsi_pll(encoder, config);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> bxt_enable_dsi_pll(encoder, config);
> }
>
> void intel_disable_dsi_pll(struct intel_encoder *encoder)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_disable_dsi_pll(encoder);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> bxt_disable_dsi_pll(encoder);
> }
>
> @@ -564,10 +564,10 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>
> void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> bxt_dsi_reset_clocks(encoder, port);
> - else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_reset_clocks(encoder, port);
> }
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 182204373931..5d5d609ed5e9 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -376,16 +376,16 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
>
> /* WaDisableMinuteIaClockGating:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
> ~GUC_ENABLE_MIA_CLOCK_GATING));
> }
>
> /* WaC6DisallowByGfxPause:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_B0))
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
> I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> else
> I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> @@ -730,7 +730,7 @@ void intel_guc_init(struct drm_device *dev)
> fw_path = I915_SKL_GUC_UCODE;
> guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
> guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> fw_path = I915_BXT_GUC_UCODE;
> guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
> guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 6607c4e3c36c..f6562451c47e 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1241,7 +1241,7 @@ static enum drm_mode_status
> hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> int clock, bool respect_downstream_limits)
> {
> - struct drm_device *dev = intel_hdmi_to_dev(hdmi);
> + struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
>
> if (clock < 25000)
> return MODE_CLOCK_LOW;
> @@ -1249,11 +1249,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> return MODE_CLOCK_HIGH;
>
> /* BXT DPLL can't generate 223-240 MHz */
> - if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
> + if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
> return MODE_CLOCK_RANGE;
>
> /* CHV DPLL can't generate 216-240 MHz */
> - if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
> + if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
> return MODE_CLOCK_RANGE;
>
> return MODE_OK;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 025fbd522819..e4bb85c9c6e1 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2596,7 +2596,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> skl_display_core_init(dev_priv, resume);
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> bxt_display_core_init(dev_priv, resume);
> } else if (IS_CHERRYVIEW(dev)) {
> mutex_lock(&power_domains->lock);
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 14/19] drm/i915: Make HAS_L3_DPF only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (12 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 13/19] drm/i915: Make IS_BROXTON " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 10:54 ` David Weinehall
2016-10-11 13:21 ` [PATCH 15/19] drm/i915: Make IS_G4X " Tvrtko Ursulin
` (6 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 472 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ad9299196d13..c264e703b686 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2869,7 +2869,7 @@ struct drm_i915_cmd_table {
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
/* DPF == dynamic parity feature */
-#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
+#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2 : HAS_L3_DPF(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 75f4ba935ebc..079ba7cfc971 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3592,7 +3592,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
pm_irqs = gt_irqs = 0;
dev_priv->gt_irq_mask = ~0;
- if (HAS_L3_DPF(dev)) {
+ if (HAS_L3_DPF(dev_priv)) {
/* L3 parity interrupt is always unmasked. */
dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
gt_irqs |= GT_PARITY_ERROR(dev_priv);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 14/19] drm/i915: Make HAS_L3_DPF only take dev_priv
2016-10-11 13:21 ` [PATCH 14/19] drm/i915: Make HAS_L3_DPF " Tvrtko Ursulin
@ 2016-10-12 10:54 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 10:54 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:47PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 472 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ad9299196d13..c264e703b686 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2869,7 +2869,7 @@ struct drm_i915_cmd_table {
> #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
>
> /* DPF == dynamic parity feature */
> -#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)
> +#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
> #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
> 2 : HAS_L3_DPF(dev_priv))
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 75f4ba935ebc..079ba7cfc971 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3592,7 +3592,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
> pm_irqs = gt_irqs = 0;
>
> dev_priv->gt_irq_mask = ~0;
> - if (HAS_L3_DPF(dev)) {
> + if (HAS_L3_DPF(dev_priv)) {
> /* L3 parity interrupt is always unmasked. */
> dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
> gt_irqs |= GT_PARITY_ERROR(dev_priv);
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 15/19] drm/i915: Make IS_G4X only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (13 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 14/19] drm/i915: Make HAS_L3_DPF " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 11:43 ` David Weinehall
2016-10-11 13:21 ` [PATCH 16/19] drm/i915: Make IS_CHERRYVIEW " Tvrtko Ursulin
` (5 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 472 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 5 +++--
drivers/gpu/drm/i915/i915_suspend.c | 4 ++--
drivers/gpu/drm/i915/intel_crt.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 40 ++++++++++++++++++----------------
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_hdmi.c | 4 ++--
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
8 files changed, 33 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c264e703b686..f54465ea2f44 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2649,7 +2649,7 @@ struct drm_i915_cmd_table {
#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
#define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
-#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
+#define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 3508120b8c90..d1b40bce0249 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -204,7 +204,8 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
return 0;
/* make sure we don't clobber the GTT if it's within stolen memory */
- if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) {
+ if (INTEL_GEN(dev_priv) <= 4 && !IS_G33(dev_priv) &&
+ !IS_G4X(dev_priv)) {
struct {
u32 start, end;
} stolen[2] = {
@@ -437,7 +438,7 @@ int i915_gem_init_stolen(struct drm_device *dev)
case 3:
break;
case 4:
- if (IS_G4X(dev))
+ if (IS_G4X(dev_priv))
g4x_get_stolen_reserved(dev_priv, &reserved_base,
&reserved_size);
break;
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index a0af170062b1..7870856fccd0 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -38,7 +38,7 @@ static void i915_save_display(struct drm_device *dev)
dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
/* save FBC interval */
- if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
+ if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
}
@@ -54,7 +54,7 @@ static void i915_restore_display(struct drm_device *dev)
intel_fbc_global_disable(dev_priv);
/* restore FBC interval */
- if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
+ if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
i915_redisable_vga(dev);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index d4388c03b4da..d456786f5813 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -771,7 +771,7 @@ static int intel_crt_get_modes(struct drm_connector *connector)
i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
ret = intel_crt_ddc_get_modes(connector, i2c);
- if (ret || !IS_G4X(dev))
+ if (ret || !IS_G4X(dev_priv))
goto out;
/* Try to probe digital port for output in DVI-I -> VGA mode. */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 636e5572b996..bf871b565549 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3071,7 +3071,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
dspcntr |= DISPPLANE_TILED;
- if (IS_G4X(dev))
+ if (IS_G4X(dev_priv))
dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
intel_add_fb_offsets(&x, &y, plane_state, 0);
@@ -7226,7 +7226,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
/* Cantiga+ cannot handle modes with a hsync front porch of 0.
* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
*/
- if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
+ if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
return -EINVAL;
@@ -7540,7 +7540,7 @@ static unsigned int intel_hpll_vco(struct drm_device *dev)
/* FIXME other chipsets? */
if (IS_GM45(dev_priv))
vco_table = ctg_vco;
- else if (IS_G4X(dev))
+ else if (IS_G4X(dev_priv))
vco_table = elk_vco;
else if (IS_CRESTLINE(dev))
vco_table = cl_vco;
@@ -8174,7 +8174,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
else {
dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
- if (IS_G4X(dev) && reduced_clock)
+ if (IS_G4X(dev_priv) && reduced_clock)
dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
}
switch (clock->p2) {
@@ -8416,7 +8416,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
pipeconf |= PIPECONF_DOUBLE_WIDE;
/* only g4x and later have fancy bpc/dither controls */
- if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
+ IS_CHERRYVIEW(dev_priv)) {
/* Bspec claims that we can't use dithering for 30bpp pipes. */
if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
pipeconf |= PIPECONF_DITHER_EN |
@@ -8833,7 +8834,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
if (!(tmp & PIPECONF_ENABLE))
goto out;
- if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
+ IS_CHERRYVIEW(dev_priv)) {
switch (tmp & PIPECONF_BPC_MASK) {
case PIPECONF_6BPC:
pipe_config->pipe_bpp = 18;
@@ -11582,7 +11584,7 @@ static bool __pageflip_finished_cs(struct intel_crtc *crtc,
* really needed there. But since ctg has the registers,
* include it in the check anyway.
*/
- if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
+ if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
return true;
/*
@@ -12245,7 +12247,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
atomic_inc(&intel_crtc->unpin_work_count);
- if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
+ if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
@@ -12705,15 +12707,16 @@ static int
compute_baseline_pipe_bpp(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
- struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_atomic_state *state;
struct drm_connector *connector;
struct drm_connector_state *connector_state;
int bpp, i;
- if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
+ if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
+ IS_CHERRYVIEW(dev_priv)))
bpp = 10*3;
- else if (INTEL_INFO(dev)->gen >= 5)
+ else if (INTEL_GEN(dev_priv) >= 5)
bpp = 12*3;
else
bpp = 8*3;
@@ -13404,7 +13407,7 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_X(dsi_pll.ctrl);
PIPE_CONF_CHECK_X(dsi_pll.div);
- if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
+ if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
@@ -14966,7 +14969,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
intel_primary_formats, num_formats,
DRM_PLANE_TYPE_PRIMARY,
"plane 1%c", pipe_name(pipe));
- else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
+ else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
ret = drm_universal_plane_init(dev, &primary->base, 0,
&intel_plane_funcs,
intel_primary_formats, num_formats,
@@ -15527,12 +15530,12 @@ static void intel_setup_outputs(struct drm_device *dev)
if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
DRM_DEBUG_KMS("probing SDVOB\n");
found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
- if (!found && IS_G4X(dev)) {
+ if (!found && IS_G4X(dev_priv)) {
DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
}
- if (!found && IS_G4X(dev))
+ if (!found && IS_G4X(dev_priv))
intel_dp_init(dev, DP_B, PORT_B);
}
@@ -15545,16 +15548,15 @@ static void intel_setup_outputs(struct drm_device *dev)
if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
- if (IS_G4X(dev)) {
+ if (IS_G4X(dev_priv)) {
DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
}
- if (IS_G4X(dev))
+ if (IS_G4X(dev_priv))
intel_dp_init(dev, DP_C, PORT_C);
}
- if (IS_G4X(dev) &&
- (I915_READ(DP_D) & DP_DETECTED))
+ if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
intel_dp_init(dev, DP_D, PORT_D);
} else if (IS_GEN2(dev))
intel_dvo_init(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b6c8b25ee1d4..dfc93cc11a13 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1341,7 +1341,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
const struct dp_link_dpll *divisor = NULL;
int i, count = 0;
- if (IS_G4X(dev)) {
+ if (IS_G4X(dev_priv)) {
divisor = gen4_dpll;
count = ARRAY_SIZE(gen4_dpll);
} else if (HAS_PCH_SPLIT(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f6562451c47e..c7d9cddf4e3e 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1889,7 +1889,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
intel_hdmi->write_infoframe = vlv_write_infoframe;
intel_hdmi->set_infoframes = vlv_set_infoframes;
intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
- } else if (IS_G4X(dev)) {
+ } else if (IS_G4X(dev_priv)) {
intel_hdmi->write_infoframe = g4x_write_infoframe;
intel_hdmi->set_infoframes = g4x_set_infoframes;
intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
@@ -1996,7 +1996,7 @@ void intel_hdmi_init(struct drm_device *dev,
* to work on real hardware. And since g4x can send infoframes to
* only one port anyway, nothing is lost by allowing it.
*/
- if (IS_G4X(dev))
+ if (IS_G4X(dev_priv))
intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
intel_dig_port->port = port;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3ba9502cf2c2..2c5dcd3ba2c2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -326,7 +326,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
POSTING_READ(FW_BLC_SELF_VLV);
dev_priv->wm.vlv.cxsr = enable;
- } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
+ } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
POSTING_READ(FW_BLC_SELF);
} else if (IS_PINEVIEW(dev)) {
@@ -7776,7 +7776,7 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.update_wm = NULL;
} else
dev_priv->display.update_wm = pineview_update_wm;
- } else if (IS_G4X(dev)) {
+ } else if (IS_G4X(dev_priv)) {
dev_priv->display.update_wm = g4x_update_wm;
} else if (IS_GEN4(dev)) {
dev_priv->display.update_wm = i965_update_wm;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 15/19] drm/i915: Make IS_G4X only take dev_priv
2016-10-11 13:21 ` [PATCH 15/19] drm/i915: Make IS_G4X " Tvrtko Ursulin
@ 2016-10-12 11:43 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 11:43 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:48PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 472 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem_stolen.c | 5 +++--
> drivers/gpu/drm/i915/i915_suspend.c | 4 ++--
> drivers/gpu/drm/i915/intel_crt.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 40 ++++++++++++++++++----------------
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/intel_hdmi.c | 4 ++--
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> 8 files changed, 33 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c264e703b686..f54465ea2f44 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2649,7 +2649,7 @@ struct drm_i915_cmd_table {
> #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
> #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
> #define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
> -#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
> +#define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
> #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
> #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
> #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index 3508120b8c90..d1b40bce0249 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -204,7 +204,8 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
> return 0;
>
> /* make sure we don't clobber the GTT if it's within stolen memory */
> - if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) {
> + if (INTEL_GEN(dev_priv) <= 4 && !IS_G33(dev_priv) &&
> + !IS_G4X(dev_priv)) {
> struct {
> u32 start, end;
> } stolen[2] = {
> @@ -437,7 +438,7 @@ int i915_gem_init_stolen(struct drm_device *dev)
> case 3:
> break;
> case 4:
> - if (IS_G4X(dev))
> + if (IS_G4X(dev_priv))
> g4x_get_stolen_reserved(dev_priv, &reserved_base,
> &reserved_size);
> break;
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index a0af170062b1..7870856fccd0 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -38,7 +38,7 @@ static void i915_save_display(struct drm_device *dev)
> dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
>
> /* save FBC interval */
> - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
> + if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
> dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
> }
>
> @@ -54,7 +54,7 @@ static void i915_restore_display(struct drm_device *dev)
> intel_fbc_global_disable(dev_priv);
>
> /* restore FBC interval */
> - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
> + if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
> I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
>
> i915_redisable_vga(dev);
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index d4388c03b4da..d456786f5813 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -771,7 +771,7 @@ static int intel_crt_get_modes(struct drm_connector *connector)
>
> i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
> ret = intel_crt_ddc_get_modes(connector, i2c);
> - if (ret || !IS_G4X(dev))
> + if (ret || !IS_G4X(dev_priv))
> goto out;
>
> /* Try to probe digital port for output in DVI-I -> VGA mode. */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 636e5572b996..bf871b565549 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3071,7 +3071,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
> dspcntr |= DISPPLANE_TILED;
>
> - if (IS_G4X(dev))
> + if (IS_G4X(dev_priv))
> dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>
> intel_add_fb_offsets(&x, &y, plane_state, 0);
> @@ -7226,7 +7226,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> /* Cantiga+ cannot handle modes with a hsync front porch of 0.
> * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
> */
> - if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
> + if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
> adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
> return -EINVAL;
>
> @@ -7540,7 +7540,7 @@ static unsigned int intel_hpll_vco(struct drm_device *dev)
> /* FIXME other chipsets? */
> if (IS_GM45(dev_priv))
> vco_table = ctg_vco;
> - else if (IS_G4X(dev))
> + else if (IS_G4X(dev_priv))
> vco_table = elk_vco;
> else if (IS_CRESTLINE(dev))
> vco_table = cl_vco;
> @@ -8174,7 +8174,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
> dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
> else {
> dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> - if (IS_G4X(dev) && reduced_clock)
> + if (IS_G4X(dev_priv) && reduced_clock)
> dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
> }
> switch (clock->p2) {
> @@ -8416,7 +8416,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
> pipeconf |= PIPECONF_DOUBLE_WIDE;
>
> /* only g4x and later have fancy bpc/dither controls */
> - if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> + IS_CHERRYVIEW(dev_priv)) {
> /* Bspec claims that we can't use dithering for 30bpp pipes. */
> if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
> pipeconf |= PIPECONF_DITHER_EN |
> @@ -8833,7 +8834,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> if (!(tmp & PIPECONF_ENABLE))
> goto out;
>
> - if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> + IS_CHERRYVIEW(dev_priv)) {
> switch (tmp & PIPECONF_BPC_MASK) {
> case PIPECONF_6BPC:
> pipe_config->pipe_bpp = 18;
> @@ -11582,7 +11584,7 @@ static bool __pageflip_finished_cs(struct intel_crtc *crtc,
> * really needed there. But since ctg has the registers,
> * include it in the check anyway.
> */
> - if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
> + if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
> return true;
>
> /*
> @@ -12245,7 +12247,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
>
> atomic_inc(&intel_crtc->unpin_work_count);
>
> - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
> + if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
>
> if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> @@ -12705,15 +12707,16 @@ static int
> compute_baseline_pipe_bpp(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> - struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct drm_atomic_state *state;
> struct drm_connector *connector;
> struct drm_connector_state *connector_state;
> int bpp, i;
>
> - if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
> + if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> + IS_CHERRYVIEW(dev_priv)))
> bpp = 10*3;
> - else if (INTEL_INFO(dev)->gen >= 5)
> + else if (INTEL_GEN(dev_priv) >= 5)
> bpp = 12*3;
> else
> bpp = 8*3;
> @@ -13404,7 +13407,7 @@ intel_pipe_config_compare(struct drm_device *dev,
> PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> PIPE_CONF_CHECK_X(dsi_pll.div);
>
> - if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
> + if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> PIPE_CONF_CHECK_I(pipe_bpp);
>
> PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
> @@ -14966,7 +14969,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
> intel_primary_formats, num_formats,
> DRM_PLANE_TYPE_PRIMARY,
> "plane 1%c", pipe_name(pipe));
> - else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
> + else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> ret = drm_universal_plane_init(dev, &primary->base, 0,
> &intel_plane_funcs,
> intel_primary_formats, num_formats,
> @@ -15527,12 +15530,12 @@ static void intel_setup_outputs(struct drm_device *dev)
> if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
> DRM_DEBUG_KMS("probing SDVOB\n");
> found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
> - if (!found && IS_G4X(dev)) {
> + if (!found && IS_G4X(dev_priv)) {
> DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
> intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
> }
>
> - if (!found && IS_G4X(dev))
> + if (!found && IS_G4X(dev_priv))
> intel_dp_init(dev, DP_B, PORT_B);
> }
>
> @@ -15545,16 +15548,15 @@ static void intel_setup_outputs(struct drm_device *dev)
>
> if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
>
> - if (IS_G4X(dev)) {
> + if (IS_G4X(dev_priv)) {
> DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
> intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
> }
> - if (IS_G4X(dev))
> + if (IS_G4X(dev_priv))
> intel_dp_init(dev, DP_C, PORT_C);
> }
>
> - if (IS_G4X(dev) &&
> - (I915_READ(DP_D) & DP_DETECTED))
> + if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
> intel_dp_init(dev, DP_D, PORT_D);
> } else if (IS_GEN2(dev))
> intel_dvo_init(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index b6c8b25ee1d4..dfc93cc11a13 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1341,7 +1341,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
> const struct dp_link_dpll *divisor = NULL;
> int i, count = 0;
>
> - if (IS_G4X(dev)) {
> + if (IS_G4X(dev_priv)) {
> divisor = gen4_dpll;
> count = ARRAY_SIZE(gen4_dpll);
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index f6562451c47e..c7d9cddf4e3e 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1889,7 +1889,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> intel_hdmi->write_infoframe = vlv_write_infoframe;
> intel_hdmi->set_infoframes = vlv_set_infoframes;
> intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
> - } else if (IS_G4X(dev)) {
> + } else if (IS_G4X(dev_priv)) {
> intel_hdmi->write_infoframe = g4x_write_infoframe;
> intel_hdmi->set_infoframes = g4x_set_infoframes;
> intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
> @@ -1996,7 +1996,7 @@ void intel_hdmi_init(struct drm_device *dev,
> * to work on real hardware. And since g4x can send infoframes to
> * only one port anyway, nothing is lost by allowing it.
> */
> - if (IS_G4X(dev))
> + if (IS_G4X(dev_priv))
> intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
>
> intel_dig_port->port = port;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3ba9502cf2c2..2c5dcd3ba2c2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -326,7 +326,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
> I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> POSTING_READ(FW_BLC_SELF_VLV);
> dev_priv->wm.vlv.cxsr = enable;
> - } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
> + } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
> I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
> POSTING_READ(FW_BLC_SELF);
> } else if (IS_PINEVIEW(dev)) {
> @@ -7776,7 +7776,7 @@ void intel_init_pm(struct drm_device *dev)
> dev_priv->display.update_wm = NULL;
> } else
> dev_priv->display.update_wm = pineview_update_wm;
> - } else if (IS_G4X(dev)) {
> + } else if (IS_G4X(dev_priv)) {
> dev_priv->display.update_wm = g4x_update_wm;
> } else if (IS_GEN4(dev)) {
> dev_priv->display.update_wm = i965_update_wm;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 16/19] drm/i915: Make IS_CHERRYVIEW only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (14 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 15/19] drm/i915: Make IS_G4X " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 12:09 ` David Weinehall
2016-10-11 13:21 ` [PATCH 17/19] drm/i915: Make IS_VALLEYVIEW " Tvrtko Ursulin
` (4 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 864 bytes of .rodata strings and ~100 of .text.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 8 ++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/intel_audio.c | 4 +-
drivers/gpu/drm/i915/intel_color.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 67 +++++++++++++++++----------------
drivers/gpu/drm/i915/intel_dp.c | 55 ++++++++++++++-------------
drivers/gpu/drm/i915/intel_dsi.c | 8 ++--
drivers/gpu/drm/i915/intel_hdmi.c | 10 ++---
drivers/gpu/drm/i915/intel_i2c.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 4 +-
drivers/gpu/drm/i915/intel_psr.c | 4 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 10 +++--
14 files changed, 93 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 18af6d1ccec9..5e7b6a1cb2c8 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -424,7 +424,7 @@ intel_setup_mchbar(struct drm_device *dev)
u32 temp;
bool enabled;
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return;
dev_priv->mchbar_need_disable = false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f54465ea2f44..96846ecfc224 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2660,7 +2660,7 @@ struct drm_i915_cmd_table {
INTEL_DEVID(dev_priv) == 0x0152 || \
INTEL_DEVID(dev_priv) == 0x015a)
#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
-#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
+#define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
#define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
#define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
@@ -3838,11 +3838,11 @@ __raw_write(64, q)
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
-static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
+static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
{
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return VLV_VGACNTRL;
- else if (INTEL_INFO(dev)->gen >= 5)
+ else if (INTEL_GEN(dev_priv) >= 5)
return CPU_VGACNTRL;
else
return VGACNTRL;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e628691fe97e..4211b9a4a918 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2133,7 +2133,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
if (IS_BROADWELL(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
- else if (IS_CHERRYVIEW(dev))
+ else if (IS_CHERRYVIEW(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
else if (IS_SKYLAKE(dev_priv))
I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 13b726916f98..d1275cbd5905 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -428,8 +428,8 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
aud_config = IBX_AUD_CFG(pipe);
aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
- } else if (IS_VALLEYVIEW(connector->dev) ||
- IS_CHERRYVIEW(connector->dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv) ||
+ IS_CHERRYVIEW(dev_priv)) {
hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
aud_config = VLV_AUD_CFG(pipe);
aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index da76a799411a..445108855275 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -534,7 +534,7 @@ void intel_color_init(struct drm_crtc *crtc)
drm_mode_crtc_set_gamma_size(crtc, 256);
- if (IS_CHERRYVIEW(dev)) {
+ if (IS_CHERRYVIEW(dev_priv)) {
dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
dev_priv->display.load_luts = cherryview_load_luts;
} else if (IS_HASWELL(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bf871b565549..d61a12dbbd72 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -849,7 +849,7 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
* For CHV ignore the error and consider only the P value.
* Prefer a bigger P value based on HW requirements.
*/
- if (IS_CHERRYVIEW(dev)) {
+ if (IS_CHERRYVIEW(to_i915(dev))) {
*error_ppm = 0;
return calculated_clock->p > best_clock->p;
@@ -1332,7 +1332,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
"plane %d assertion failure, should be off on pipe %c but is still active\n",
sprite, pipe_name(pipe));
}
- } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
for_each_sprite(dev_priv, pipe, sprite) {
u32 val = I915_READ(SPCNTR(pipe, sprite));
I915_STATE_WARN(val & SP_ENABLE,
@@ -3033,7 +3033,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
((crtc_state->pipe_src_h - 1) << 16) |
(crtc_state->pipe_src_w - 1));
I915_WRITE(DSPPOS(plane), 0);
- } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
+ } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
I915_WRITE(PRIMSIZE(plane),
((crtc_state->pipe_src_h - 1) << 16) |
(crtc_state->pipe_src_w - 1));
@@ -5874,7 +5874,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
dev_priv->max_cdclk_freq = 540000;
else
dev_priv->max_cdclk_freq = 675000;
- } else if (IS_CHERRYVIEW(dev)) {
+ } else if (IS_CHERRYVIEW(dev_priv)) {
dev_priv->max_cdclk_freq = 320000;
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->max_cdclk_freq = 400000;
@@ -6676,7 +6676,7 @@ static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
*/
intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(dev_priv))
cherryview_set_cdclk(dev, req_cdclk);
else
valleyview_set_cdclk(dev, req_cdclk);
@@ -6704,7 +6704,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
intel_set_pipe_timings(intel_crtc);
intel_set_pipe_src_size(intel_crtc);
- if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
+ if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
struct drm_i915_private *dev_priv = to_i915(dev);
I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
@@ -6719,7 +6719,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
- if (IS_CHERRYVIEW(dev)) {
+ if (IS_CHERRYVIEW(dev_priv)) {
chv_prepare_pll(intel_crtc, intel_crtc->config);
chv_enable_pll(intel_crtc, intel_crtc->config);
} else {
@@ -6838,7 +6838,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_post_disable(crtc, old_crtc_state, old_state);
if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(dev_priv))
chv_disable_pll(dev_priv, pipe);
else if (IS_VALLEYVIEW(dev))
vlv_disable_pll(dev_priv, pipe);
@@ -7805,8 +7805,8 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
* for gen < 8) and if DRRS is supported (to make sure the
* registers are not unnecessarily accessed).
*/
- if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
- crtc->config->has_drrs) {
+ if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
+ INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
I915_WRITE(PIPE_DATA_M2(transcoder),
TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
@@ -8108,7 +8108,7 @@ int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
pipe_config->pixel_multiplier = 1;
pipe_config->dpll = *dpll;
- if (IS_CHERRYVIEW(dev)) {
+ if (IS_CHERRYVIEW(to_i915(dev))) {
chv_compute_dpll(crtc, pipe_config);
chv_prepare_pll(crtc, pipe_config);
chv_enable_pll(crtc, pipe_config);
@@ -8133,7 +8133,7 @@ int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
*/
void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
{
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(to_i915(dev)))
chv_disable_pll(to_i915(dev), pipe);
else
vlv_disable_pll(to_i915(dev), pipe);
@@ -8457,7 +8457,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
} else
pipeconf |= PIPECONF_PROGRESSIVE;
- if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_crtc->config->limited_color_range)
pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
@@ -8851,7 +8851,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
}
}
- if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
(tmp & PIPECONF_COLOR_RANGE_SELECT))
pipe_config->limited_color_range = true;
@@ -8865,7 +8865,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
if (INTEL_INFO(dev)->gen >= 4) {
/* No way to read it out on pipes B and C */
- if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
+ if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
tmp = dev_priv->chv_dpll_md[crtc->pipe];
else
tmp = I915_READ(DPLL_MD(crtc->pipe));
@@ -8886,7 +8886,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
pipe_config->pixel_multiplier = 1;
}
pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
- if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
+ if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
/*
* DPLL_DVO_2X_MODE must be enabled for both DPLLs
* on 830. Filter it out here so that we don't
@@ -8904,7 +8904,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
DPLL_PORTB_READY_MASK);
}
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(dev_priv))
chv_crtc_clock_get(crtc, pipe_config);
else if (IS_VALLEYVIEW(dev))
vlv_crtc_clock_get(crtc, pipe_config);
@@ -12250,7 +12250,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
engine = &dev_priv->engine[BCS];
if (fb->modifier[0] != old_fb->modifier[0])
/* vlv: DISPLAY_FLIP fails to change tiling */
@@ -13348,7 +13348,7 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_I(pixel_multiplier);
PIPE_CONF_CHECK_I(has_hdmi_sink);
if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
- IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
PIPE_CONF_CHECK_I(limited_color_range);
PIPE_CONF_CHECK_I(has_infoframe);
@@ -15068,7 +15068,7 @@ intel_check_cursor_plane(struct drm_plane *plane,
* display power well must be turned off and on again.
* Refuse the put the cursor into that compromised position.
*/
- if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
+ if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
state->base.visible && state->base.crtc_x < 0) {
DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
return -EINVAL;
@@ -15338,7 +15338,7 @@ static bool intel_crt_present(struct drm_device *dev)
if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
return false;
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(dev_priv))
return false;
if (HAS_PCH_LPT_H(dev_priv) &&
@@ -15479,7 +15479,7 @@ static void intel_setup_outputs(struct drm_device *dev)
if (I915_READ(PCH_DP_D) & DP_DETECTED)
intel_dp_init(dev, PCH_DP_D, PORT_D);
- } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
bool has_edp, has_port;
/*
@@ -15511,7 +15511,7 @@ static void intel_setup_outputs(struct drm_device *dev)
if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
- if (IS_CHERRYVIEW(dev)) {
+ if (IS_CHERRYVIEW(dev_priv)) {
/*
* eDP not supported on port D,
* so no need to worry about it
@@ -15629,10 +15629,10 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
};
static
-u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
- uint32_t pixel_format)
+u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
+ uint64_t fb_modifier, uint32_t pixel_format)
{
- u32 gen = INTEL_INFO(dev)->gen;
+ u32 gen = INTEL_INFO(dev_priv)->gen;
if (gen >= 9) {
int cpp = drm_format_plane_cpp(pixel_format, 0);
@@ -15641,7 +15641,8 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
* pixels and 32K bytes."
*/
return min(8192 * cpp, 32768);
- } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
+ } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
+ !IS_CHERRYVIEW(dev_priv)) {
return 32*1024;
} else if (gen >= 4) {
if (fb_modifier == I915_FORMAT_MOD_X_TILED)
@@ -15728,7 +15729,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
return -EINVAL;
}
- pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
+ pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
mode_cmd->pixel_format);
if (mode_cmd->pitches[0] > pitch_limit) {
DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
@@ -15766,7 +15767,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
}
break;
case DRM_FORMAT_ABGR8888:
- if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
+ if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
INTEL_INFO(dev)->gen < 9) {
format_name = drm_get_format_name(mode_cmd->pixel_format);
DRM_DEBUG("unsupported pixel format: %s\n", format_name);
@@ -15785,7 +15786,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
}
break;
case DRM_FORMAT_ABGR2101010:
- if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
+ if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
format_name = drm_get_format_name(mode_cmd->pixel_format);
DRM_DEBUG("unsupported pixel format: %s\n", format_name);
kfree(format_name);
@@ -16232,7 +16233,7 @@ static void i915_disable_vga(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
u8 sr1;
- i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
+ i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
@@ -16677,7 +16678,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
void i915_redisable_vga_power_on(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
+ i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
@@ -16915,7 +16916,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
pll->on = false;
}
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_wm_get_hw_state(dev);
else if (IS_GEN9(dev))
skl_wm_get_hw_state(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dfc93cc11a13..1e1ccf092e11 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -344,7 +344,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
DP |= DP_PORT_WIDTH(1);
DP |= DP_LINK_TRAIN_PAT_1;
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(dev_priv))
DP |= DP_PIPE_SELECT_CHV(pipe);
else if (pipe == PIPE_B)
DP |= DP_PIPEB_SELECT;
@@ -356,10 +356,10 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
* So enable temporarily it if it's not already enabled.
*/
if (!pll_enabled) {
- release_cl_override = IS_CHERRYVIEW(dev) &&
+ release_cl_override = IS_CHERRYVIEW(dev_priv) &&
!chv_phy_powergate_ch(dev_priv, phy, ch, true);
- if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
+ if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev_priv) ?
&chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
DRM_ERROR("Failed to force on pll for pipe %c!\n",
pipe_name(pipe));
@@ -570,7 +570,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
struct drm_device *dev = &dev_priv->drm;
struct intel_encoder *encoder;
- if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
+ if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
!IS_BROXTON(dev_priv)))
return;
@@ -664,7 +664,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
pps_lock(intel_dp);
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
i915_reg_t pp_ctrl_reg, pp_div_reg;
u32 pp_div;
@@ -692,7 +692,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
lockdep_assert_held(&dev_priv->pps_mutex);
- if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_dp->pps_pipe == INVALID_PIPE)
return false;
@@ -706,7 +706,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
lockdep_assert_held(&dev_priv->pps_mutex);
- if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_dp->pps_pipe == INVALID_PIPE)
return false;
@@ -1347,7 +1347,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
} else if (HAS_PCH_SPLIT(dev_priv)) {
divisor = pch_dpll;
count = ARRAY_SIZE(pch_dpll);
- } else if (IS_CHERRYVIEW(dev)) {
+ } else if (IS_CHERRYVIEW(dev_priv)) {
divisor = chv_dpll;
count = ARRAY_SIZE(chv_dpll);
} else if (IS_VALLEYVIEW(dev)) {
@@ -1791,7 +1791,8 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
} else {
if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev) &&
- !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
+ !IS_CHERRYVIEW(dev_priv) &&
+ pipe_config->limited_color_range)
intel_dp->DP |= DP_COLOR_RANGE_16_235;
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
@@ -1803,7 +1804,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
intel_dp->DP |= DP_ENHANCED_FRAMING;
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(dev_priv))
intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
else if (crtc->pipe == PIPE_B)
intel_dp->DP |= DP_PIPEB_SELECT;
@@ -2459,7 +2460,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
i915_mmio_reg_offset(intel_dp->output_reg));
- } else if (IS_CHERRYVIEW(dev)) {
+ } else if (IS_CHERRYVIEW(dev_priv)) {
*pipe = DP_PORT_TO_PIPE_CHV(tmp);
} else {
*pipe = PORT_TO_PIPE(tmp);
@@ -2681,7 +2682,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
}
} else {
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(dev_priv))
*DP &= ~DP_LINK_TRAIN_MASK_CHV;
else
*DP &= ~DP_LINK_TRAIN_MASK;
@@ -2697,7 +2698,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
*DP |= DP_LINK_TRAIN_PAT_2;
break;
case DP_TRAINING_PATTERN_3:
- if (IS_CHERRYVIEW(dev)) {
+ if (IS_CHERRYVIEW(dev_priv)) {
*DP |= DP_LINK_TRAIN_PAT_3_CHV;
} else {
DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
@@ -2747,7 +2748,7 @@ static void intel_enable_dp(struct intel_encoder *encoder,
pps_lock(intel_dp);
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_init_panel_power_sequencer(intel_dp);
intel_dp_enable_port(intel_dp, pipe_config);
@@ -2758,10 +2759,10 @@ static void intel_enable_dp(struct intel_encoder *encoder,
pps_unlock(intel_dp);
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
unsigned int lane_mask = 0x0;
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(dev_priv))
lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
@@ -2987,7 +2988,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
- } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
else if (IS_GEN7(dev) && port == PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
@@ -3348,7 +3349,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
signal_levels = 0;
else
mask = DDI_BUF_EMP_MASK;
- } else if (IS_CHERRYVIEW(dev)) {
+ } else if (IS_CHERRYVIEW(dev_priv)) {
signal_levels = chv_signal_levels(intel_dp);
} else if (IS_VALLEYVIEW(dev)) {
signal_levels = vlv_signal_levels(intel_dp);
@@ -3448,7 +3449,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
DP &= ~DP_LINK_TRAIN_MASK_CPT;
DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
} else {
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(dev_priv))
DP &= ~DP_LINK_TRAIN_MASK_CHV;
else
DP &= ~DP_LINK_TRAIN_MASK;
@@ -5085,7 +5086,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
/* Haswell doesn't have any port selection bits for the panel
* power sequencer any more. */
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
port_sel = PANEL_PORT_SELECT_VLV(port);
} else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
if (port == PORT_A)
@@ -5114,7 +5115,9 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
static void intel_dp_pps_init(struct drm_device *dev,
struct intel_dp *intel_dp)
{
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
vlv_initial_power_sequencer_setup(intel_dp);
} else {
intel_dp_init_panel_power_sequencer(dev, intel_dp);
@@ -5584,7 +5587,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
}
mutex_unlock(&dev->mode_config.mutex);
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_dp->edp_notifier.notifier_call = edp_notify_handler;
register_reboot_notifier(&intel_dp->edp_notifier);
@@ -5593,7 +5596,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
* If the current pipe isn't valid, try the PPS pipe, and if that
* fails just assume pipe A.
*/
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(dev_priv))
pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
else
pipe = PORT_TO_PIPE(intel_dp->DP);
@@ -5682,7 +5685,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
intel_encoder->type = INTEL_OUTPUT_EDP;
/* eDP only on port B and/or C on vlv/chv */
- if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+ if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
is_edp(intel_dp) && port != PORT_B && port != PORT_C))
return false;
@@ -5792,7 +5795,7 @@ bool intel_dp_init(struct drm_device *dev,
intel_encoder->get_hw_state = intel_dp_get_hw_state;
intel_encoder->get_config = intel_dp_get_config;
intel_encoder->suspend = intel_dp_encoder_suspend;
- if (IS_CHERRYVIEW(dev)) {
+ if (IS_CHERRYVIEW(dev_priv)) {
intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
intel_encoder->pre_enable = chv_pre_enable_dp;
intel_encoder->enable = vlv_enable_dp;
@@ -5815,7 +5818,7 @@ bool intel_dp_init(struct drm_device *dev,
intel_dig_port->max_lanes = 4;
intel_encoder->type = INTEL_OUTPUT_DP;
- if (IS_CHERRYVIEW(dev)) {
+ if (IS_CHERRYVIEW(dev_priv)) {
if (port == PORT_D)
intel_encoder->crtc_mask = 1 << 2;
else
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 48e8dd108f4f..4e0d025490a3 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -740,7 +740,6 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
- struct drm_device *dev = encoder->base.dev;
enum intel_display_power_domain power_domain;
enum port port;
bool active = false;
@@ -770,7 +769,8 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
* bit in port C control register does not get set. As a
* workaround, check pipe B conf instead.
*/
- if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && port == PORT_C)
+ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
+ port == PORT_C)
enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
/* Try command mode if video mode not enabled */
@@ -1137,7 +1137,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
}
for_each_dsi_port(port, intel_dsi->ports) {
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
/*
* escape clock divider, 20MHz, shared for A and C.
* device ready must be off when doing this! txclkesc?
@@ -1449,7 +1449,7 @@ void intel_dsi_init(struct drm_device *dev)
if (!intel_bios_is_dsi_present(dev_priv, &port))
return;
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
} else if (IS_BROXTON(dev_priv)) {
dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index c7d9cddf4e3e..c8243dc4d2b9 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -881,7 +881,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
if (HAS_PCH_CPT(dev_priv))
hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
- else if (IS_CHERRYVIEW(dev))
+ else if (IS_CHERRYVIEW(dev_priv))
hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
else
hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
@@ -913,7 +913,7 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
if (HAS_PCH_CPT(dev_priv))
*pipe = PORT_TO_PIPE_CPT(tmp);
- else if (IS_CHERRYVIEW(dev))
+ else if (IS_CHERRYVIEW(dev_priv))
*pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
else
*pipe = PORT_TO_PIPE(tmp);
@@ -1885,7 +1885,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
BUG();
}
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_hdmi->write_infoframe = vlv_write_infoframe;
intel_hdmi->set_infoframes = vlv_set_infoframes;
intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
@@ -1959,7 +1959,7 @@ void intel_hdmi_init(struct drm_device *dev,
}
intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
intel_encoder->get_config = intel_hdmi_get_config;
- if (IS_CHERRYVIEW(dev)) {
+ if (IS_CHERRYVIEW(dev_priv)) {
intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
intel_encoder->pre_enable = chv_hdmi_pre_enable;
intel_encoder->enable = vlv_enable_hdmi;
@@ -1982,7 +1982,7 @@ void intel_hdmi_init(struct drm_device *dev,
intel_encoder->type = INTEL_OUTPUT_HDMI;
intel_encoder->port = port;
- if (IS_CHERRYVIEW(dev)) {
+ if (IS_CHERRYVIEW(dev_priv)) {
if (port == PORT_D)
intel_encoder->crtc_mask = 1 << 2;
else
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index afb2652919d0..d04185e1edd6 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -635,7 +635,7 @@ int intel_setup_gmbus(struct drm_device *dev)
if (HAS_PCH_NOP(dev_priv))
return 0;
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
else if (!HAS_GMCH_DISPLAY(dev_priv))
dev_priv->gpio_mmio_base =
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2c5dcd3ba2c2..2107434a42e4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -322,7 +322,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
struct drm_device *dev = &dev_priv->drm;
u32 val;
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
POSTING_READ(FW_BLC_SELF_VLV);
dev_priv->wm.vlv.cxsr = enable;
@@ -7755,7 +7755,7 @@ void intel_init_pm(struct drm_device *dev)
DRM_DEBUG_KMS("Failed to read display plane latency. "
"Disable CxSR\n");
}
- } else if (IS_CHERRYVIEW(dev)) {
+ } else if (IS_CHERRYVIEW(dev_priv)) {
vlv_setup_wm_latency(dev);
dev_priv->display.update_wm = vlv_update_wm;
} else if (IS_VALLEYVIEW(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4a973b34348a..271a3e29ff23 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -354,7 +354,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
return false;
}
- if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
!dev_priv->psr.link_standby) {
DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
return false;
@@ -837,7 +837,7 @@ void intel_psr_init(struct drm_device *dev)
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
/* HSW and BDW require workarounds that we don't implement. */
dev_priv->psr.link_standby = false;
- else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
+ else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
/* On VLV and CHV only standby mode is supported. */
dev_priv->psr.link_standby = true;
else
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index e4bb85c9c6e1..3a6e1a93aed9 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2598,7 +2598,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
skl_display_core_init(dev_priv, resume);
} else if (IS_BROXTON(dev_priv)) {
bxt_display_core_init(dev_priv, resume);
- } else if (IS_CHERRYVIEW(dev)) {
+ } else if (IS_CHERRYVIEW(dev_priv)) {
mutex_lock(&power_domains->lock);
chv_phy_control_init(dev_priv);
mutex_unlock(&power_domains->lock);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index fefd3034aead..f760d5fcbe48 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -450,7 +450,7 @@ vlv_update_plane(struct drm_plane *dplane,
if (key->flags & I915_SET_COLORKEY_SOURCE)
sprctl |= SP_SOURCE_KEY;
- if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
+ if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
chv_update_csc(intel_plane, fb->pixel_format);
I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
@@ -944,6 +944,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_intel_sprite_colorkey *set = data;
struct drm_plane *plane;
struct drm_plane_state *plane_state;
@@ -955,7 +956,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
return -EINVAL;
- if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
+ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
set->flags & I915_SET_COLORKEY_DESTINATION)
return -EINVAL;
@@ -1042,6 +1043,7 @@ static uint32_t skl_plane_formats[] = {
int
intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_plane *intel_plane = NULL;
struct intel_plane_state *state = NULL;
unsigned long possible_crtcs;
@@ -1084,7 +1086,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
case 7:
case 8:
- if (IS_IVYBRIDGE(to_i915(dev))) {
+ if (IS_IVYBRIDGE(dev_priv)) {
intel_plane->can_scale = true;
intel_plane->max_downscale = 2;
} else {
@@ -1092,7 +1094,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
intel_plane->max_downscale = 1;
}
- if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_plane->update_plane = vlv_update_plane;
intel_plane->disable_plane = vlv_disable_plane;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 16/19] drm/i915: Make IS_CHERRYVIEW only take dev_priv
2016-10-11 13:21 ` [PATCH 16/19] drm/i915: Make IS_CHERRYVIEW " Tvrtko Ursulin
@ 2016-10-12 12:09 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 12:09 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:49PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 864 bytes of .rodata strings and ~100 of .text.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 8 ++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> drivers/gpu/drm/i915/intel_audio.c | 4 +-
> drivers/gpu/drm/i915/intel_color.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 67 +++++++++++++++++----------------
> drivers/gpu/drm/i915/intel_dp.c | 55 ++++++++++++++-------------
> drivers/gpu/drm/i915/intel_dsi.c | 8 ++--
> drivers/gpu/drm/i915/intel_hdmi.c | 10 ++---
> drivers/gpu/drm/i915/intel_i2c.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 4 +-
> drivers/gpu/drm/i915/intel_psr.c | 4 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> drivers/gpu/drm/i915/intel_sprite.c | 10 +++--
> 14 files changed, 93 insertions(+), 87 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 18af6d1ccec9..5e7b6a1cb2c8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -424,7 +424,7 @@ intel_setup_mchbar(struct drm_device *dev)
> u32 temp;
> bool enabled;
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return;
>
> dev_priv->mchbar_need_disable = false;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f54465ea2f44..96846ecfc224 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2660,7 +2660,7 @@ struct drm_i915_cmd_table {
> INTEL_DEVID(dev_priv) == 0x0152 || \
> INTEL_DEVID(dev_priv) == 0x015a)
> #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
> -#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
> +#define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
> #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
> #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
> @@ -3838,11 +3838,11 @@ __raw_write(64, q)
> #define INTEL_BROADCAST_RGB_FULL 1
> #define INTEL_BROADCAST_RGB_LIMITED 2
>
> -static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
> +static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
> {
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return VLV_VGACNTRL;
> - else if (INTEL_INFO(dev)->gen >= 5)
> + else if (INTEL_GEN(dev_priv) >= 5)
> return CPU_VGACNTRL;
> else
> return VGACNTRL;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index e628691fe97e..4211b9a4a918 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2133,7 +2133,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
> /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
> if (IS_BROADWELL(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
> - else if (IS_CHERRYVIEW(dev))
> + else if (IS_CHERRYVIEW(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> else if (IS_SKYLAKE(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 13b726916f98..d1275cbd5905 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -428,8 +428,8 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
> aud_config = IBX_AUD_CFG(pipe);
> aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
> aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
> - } else if (IS_VALLEYVIEW(connector->dev) ||
> - IS_CHERRYVIEW(connector->dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) ||
> + IS_CHERRYVIEW(dev_priv)) {
> hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
> aud_config = VLV_AUD_CFG(pipe);
> aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index da76a799411a..445108855275 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -534,7 +534,7 @@ void intel_color_init(struct drm_crtc *crtc)
>
> drm_mode_crtc_set_gamma_size(crtc, 256);
>
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
> dev_priv->display.load_luts = cherryview_load_luts;
> } else if (IS_HASWELL(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bf871b565549..d61a12dbbd72 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -849,7 +849,7 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
> * For CHV ignore the error and consider only the P value.
> * Prefer a bigger P value based on HW requirements.
> */
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(to_i915(dev))) {
> *error_ppm = 0;
>
> return calculated_clock->p > best_clock->p;
> @@ -1332,7 +1332,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
> "plane %d assertion failure, should be off on pipe %c but is still active\n",
> sprite, pipe_name(pipe));
> }
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> for_each_sprite(dev_priv, pipe, sprite) {
> u32 val = I915_READ(SPCNTR(pipe, sprite));
> I915_STATE_WARN(val & SP_ENABLE,
> @@ -3033,7 +3033,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> ((crtc_state->pipe_src_h - 1) << 16) |
> (crtc_state->pipe_src_w - 1));
> I915_WRITE(DSPPOS(plane), 0);
> - } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> + } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
> I915_WRITE(PRIMSIZE(plane),
> ((crtc_state->pipe_src_h - 1) << 16) |
> (crtc_state->pipe_src_w - 1));
> @@ -5874,7 +5874,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> dev_priv->max_cdclk_freq = 540000;
> else
> dev_priv->max_cdclk_freq = 675000;
> - } else if (IS_CHERRYVIEW(dev)) {
> + } else if (IS_CHERRYVIEW(dev_priv)) {
> dev_priv->max_cdclk_freq = 320000;
> } else if (IS_VALLEYVIEW(dev)) {
> dev_priv->max_cdclk_freq = 400000;
> @@ -6676,7 +6676,7 @@ static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> */
> intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> cherryview_set_cdclk(dev, req_cdclk);
> else
> valleyview_set_cdclk(dev, req_cdclk);
> @@ -6704,7 +6704,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_set_pipe_timings(intel_crtc);
> intel_set_pipe_src_size(intel_crtc);
>
> - if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
> + if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
> @@ -6719,7 +6719,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
>
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> chv_prepare_pll(intel_crtc, intel_crtc->config);
> chv_enable_pll(intel_crtc, intel_crtc->config);
> } else {
> @@ -6838,7 +6838,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> intel_encoders_post_disable(crtc, old_crtc_state, old_state);
>
> if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> chv_disable_pll(dev_priv, pipe);
> else if (IS_VALLEYVIEW(dev))
> vlv_disable_pll(dev_priv, pipe);
> @@ -7805,8 +7805,8 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> * for gen < 8) and if DRRS is supported (to make sure the
> * registers are not unnecessarily accessed).
> */
> - if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
> - crtc->config->has_drrs) {
> + if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
> + INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
> I915_WRITE(PIPE_DATA_M2(transcoder),
> TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
> I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
> @@ -8108,7 +8108,7 @@ int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
> pipe_config->pixel_multiplier = 1;
> pipe_config->dpll = *dpll;
>
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(to_i915(dev))) {
> chv_compute_dpll(crtc, pipe_config);
> chv_prepare_pll(crtc, pipe_config);
> chv_enable_pll(crtc, pipe_config);
> @@ -8133,7 +8133,7 @@ int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
> */
> void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
> {
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(to_i915(dev)))
> chv_disable_pll(to_i915(dev), pipe);
> else
> vlv_disable_pll(to_i915(dev), pipe);
> @@ -8457,7 +8457,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
> } else
> pipeconf |= PIPECONF_PROGRESSIVE;
>
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> intel_crtc->config->limited_color_range)
> pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
>
> @@ -8851,7 +8851,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> }
> }
>
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> (tmp & PIPECONF_COLOR_RANGE_SELECT))
> pipe_config->limited_color_range = true;
>
> @@ -8865,7 +8865,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>
> if (INTEL_INFO(dev)->gen >= 4) {
> /* No way to read it out on pipes B and C */
> - if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
> + if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
> tmp = dev_priv->chv_dpll_md[crtc->pipe];
> else
> tmp = I915_READ(DPLL_MD(crtc->pipe));
> @@ -8886,7 +8886,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> pipe_config->pixel_multiplier = 1;
> }
> pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
> - if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
> + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
> /*
> * DPLL_DVO_2X_MODE must be enabled for both DPLLs
> * on 830. Filter it out here so that we don't
> @@ -8904,7 +8904,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> DPLL_PORTB_READY_MASK);
> }
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> chv_crtc_clock_get(crtc, pipe_config);
> else if (IS_VALLEYVIEW(dev))
> vlv_crtc_clock_get(crtc, pipe_config);
> @@ -12250,7 +12250,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
> if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> engine = &dev_priv->engine[BCS];
> if (fb->modifier[0] != old_fb->modifier[0])
> /* vlv: DISPLAY_FLIP fails to change tiling */
> @@ -13348,7 +13348,7 @@ intel_pipe_config_compare(struct drm_device *dev,
> PIPE_CONF_CHECK_I(pixel_multiplier);
> PIPE_CONF_CHECK_I(has_hdmi_sink);
> if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
> - IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> PIPE_CONF_CHECK_I(limited_color_range);
> PIPE_CONF_CHECK_I(has_infoframe);
>
> @@ -15068,7 +15068,7 @@ intel_check_cursor_plane(struct drm_plane *plane,
> * display power well must be turned off and on again.
> * Refuse the put the cursor into that compromised position.
> */
> - if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
> + if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
> state->base.visible && state->base.crtc_x < 0) {
> DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
> return -EINVAL;
> @@ -15338,7 +15338,7 @@ static bool intel_crt_present(struct drm_device *dev)
> if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
> return false;
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> return false;
>
> if (HAS_PCH_LPT_H(dev_priv) &&
> @@ -15479,7 +15479,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>
> if (I915_READ(PCH_DP_D) & DP_DETECTED)
> intel_dp_init(dev, PCH_DP_D, PORT_D);
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> bool has_edp, has_port;
>
> /*
> @@ -15511,7 +15511,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
> intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
>
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> /*
> * eDP not supported on port D,
> * so no need to worry about it
> @@ -15629,10 +15629,10 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
> };
>
> static
> -u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
> - uint32_t pixel_format)
> +u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
> + uint64_t fb_modifier, uint32_t pixel_format)
> {
> - u32 gen = INTEL_INFO(dev)->gen;
> + u32 gen = INTEL_INFO(dev_priv)->gen;
>
> if (gen >= 9) {
> int cpp = drm_format_plane_cpp(pixel_format, 0);
> @@ -15641,7 +15641,8 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
> * pixels and 32K bytes."
> */
> return min(8192 * cpp, 32768);
> - } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
> + } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
> + !IS_CHERRYVIEW(dev_priv)) {
> return 32*1024;
> } else if (gen >= 4) {
> if (fb_modifier == I915_FORMAT_MOD_X_TILED)
> @@ -15728,7 +15729,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
> return -EINVAL;
> }
>
> - pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
> + pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
> mode_cmd->pixel_format);
> if (mode_cmd->pitches[0] > pitch_limit) {
> DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
> @@ -15766,7 +15767,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
> }
> break;
> case DRM_FORMAT_ABGR8888:
> - if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> INTEL_INFO(dev)->gen < 9) {
> format_name = drm_get_format_name(mode_cmd->pixel_format);
> DRM_DEBUG("unsupported pixel format: %s\n", format_name);
> @@ -15785,7 +15786,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
> }
> break;
> case DRM_FORMAT_ABGR2101010:
> - if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
> + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
> format_name = drm_get_format_name(mode_cmd->pixel_format);
> DRM_DEBUG("unsupported pixel format: %s\n", format_name);
> kfree(format_name);
> @@ -16232,7 +16233,7 @@ static void i915_disable_vga(struct drm_device *dev)
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct pci_dev *pdev = dev_priv->drm.pdev;
> u8 sr1;
> - i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
> + i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
>
> /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
> vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
> @@ -16677,7 +16678,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
> void i915_redisable_vga_power_on(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
> + i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
>
> if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
> DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
> @@ -16915,7 +16916,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
> pll->on = false;
> }
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_wm_get_hw_state(dev);
> else if (IS_GEN9(dev))
> skl_wm_get_hw_state(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dfc93cc11a13..1e1ccf092e11 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -344,7 +344,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
> DP |= DP_PORT_WIDTH(1);
> DP |= DP_LINK_TRAIN_PAT_1;
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> DP |= DP_PIPE_SELECT_CHV(pipe);
> else if (pipe == PIPE_B)
> DP |= DP_PIPEB_SELECT;
> @@ -356,10 +356,10 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
> * So enable temporarily it if it's not already enabled.
> */
> if (!pll_enabled) {
> - release_cl_override = IS_CHERRYVIEW(dev) &&
> + release_cl_override = IS_CHERRYVIEW(dev_priv) &&
> !chv_phy_powergate_ch(dev_priv, phy, ch, true);
>
> - if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
> + if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev_priv) ?
> &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
> DRM_ERROR("Failed to force on pll for pipe %c!\n",
> pipe_name(pipe));
> @@ -570,7 +570,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> struct drm_device *dev = &dev_priv->drm;
> struct intel_encoder *encoder;
>
> - if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> + if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> !IS_BROXTON(dev_priv)))
> return;
>
> @@ -664,7 +664,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
>
> pps_lock(intel_dp);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
> i915_reg_t pp_ctrl_reg, pp_div_reg;
> u32 pp_div;
> @@ -692,7 +692,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
>
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> intel_dp->pps_pipe == INVALID_PIPE)
> return false;
>
> @@ -706,7 +706,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> intel_dp->pps_pipe == INVALID_PIPE)
> return false;
>
> @@ -1347,7 +1347,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> divisor = pch_dpll;
> count = ARRAY_SIZE(pch_dpll);
> - } else if (IS_CHERRYVIEW(dev)) {
> + } else if (IS_CHERRYVIEW(dev_priv)) {
> divisor = chv_dpll;
> count = ARRAY_SIZE(chv_dpll);
> } else if (IS_VALLEYVIEW(dev)) {
> @@ -1791,7 +1791,8 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
> I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
> } else {
> if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev) &&
> - !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
> + !IS_CHERRYVIEW(dev_priv) &&
> + pipe_config->limited_color_range)
> intel_dp->DP |= DP_COLOR_RANGE_16_235;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> @@ -1803,7 +1804,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
> if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> intel_dp->DP |= DP_ENHANCED_FRAMING;
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
> else if (crtc->pipe == PIPE_B)
> intel_dp->DP |= DP_PIPEB_SELECT;
> @@ -2459,7 +2460,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
>
> DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
> i915_mmio_reg_offset(intel_dp->output_reg));
> - } else if (IS_CHERRYVIEW(dev)) {
> + } else if (IS_CHERRYVIEW(dev_priv)) {
> *pipe = DP_PORT_TO_PIPE_CHV(tmp);
> } else {
> *pipe = PORT_TO_PIPE(tmp);
> @@ -2681,7 +2682,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> }
>
> } else {
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> *DP &= ~DP_LINK_TRAIN_MASK_CHV;
> else
> *DP &= ~DP_LINK_TRAIN_MASK;
> @@ -2697,7 +2698,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> *DP |= DP_LINK_TRAIN_PAT_2;
> break;
> case DP_TRAINING_PATTERN_3:
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> *DP |= DP_LINK_TRAIN_PAT_3_CHV;
> } else {
> DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
> @@ -2747,7 +2748,7 @@ static void intel_enable_dp(struct intel_encoder *encoder,
>
> pps_lock(intel_dp);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_init_panel_power_sequencer(intel_dp);
>
> intel_dp_enable_port(intel_dp, pipe_config);
> @@ -2758,10 +2759,10 @@ static void intel_enable_dp(struct intel_encoder *encoder,
>
> pps_unlock(intel_dp);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> unsigned int lane_mask = 0x0;
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
>
> vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
> @@ -2987,7 +2988,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (IS_GEN7(dev) && port == PORT_A)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> @@ -3348,7 +3349,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> signal_levels = 0;
> else
> mask = DDI_BUF_EMP_MASK;
> - } else if (IS_CHERRYVIEW(dev)) {
> + } else if (IS_CHERRYVIEW(dev_priv)) {
> signal_levels = chv_signal_levels(intel_dp);
> } else if (IS_VALLEYVIEW(dev)) {
> signal_levels = vlv_signal_levels(intel_dp);
> @@ -3448,7 +3449,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
> DP &= ~DP_LINK_TRAIN_MASK_CPT;
> DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
> } else {
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> DP &= ~DP_LINK_TRAIN_MASK_CHV;
> else
> DP &= ~DP_LINK_TRAIN_MASK;
> @@ -5085,7 +5086,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>
> /* Haswell doesn't have any port selection bits for the panel
> * power sequencer any more. */
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> port_sel = PANEL_PORT_SELECT_VLV(port);
> } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
> if (port == PORT_A)
> @@ -5114,7 +5115,9 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> static void intel_dp_pps_init(struct drm_device *dev,
> struct intel_dp *intel_dp)
> {
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> vlv_initial_power_sequencer_setup(intel_dp);
> } else {
> intel_dp_init_panel_power_sequencer(dev, intel_dp);
> @@ -5584,7 +5587,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> }
> mutex_unlock(&dev->mode_config.mutex);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> intel_dp->edp_notifier.notifier_call = edp_notify_handler;
> register_reboot_notifier(&intel_dp->edp_notifier);
>
> @@ -5593,7 +5596,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> * If the current pipe isn't valid, try the PPS pipe, and if that
> * fails just assume pipe A.
> */
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
> else
> pipe = PORT_TO_PIPE(intel_dp->DP);
> @@ -5682,7 +5685,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> intel_encoder->type = INTEL_OUTPUT_EDP;
>
> /* eDP only on port B and/or C on vlv/chv */
> - if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> is_edp(intel_dp) && port != PORT_B && port != PORT_C))
> return false;
>
> @@ -5792,7 +5795,7 @@ bool intel_dp_init(struct drm_device *dev,
> intel_encoder->get_hw_state = intel_dp_get_hw_state;
> intel_encoder->get_config = intel_dp_get_config;
> intel_encoder->suspend = intel_dp_encoder_suspend;
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
> intel_encoder->pre_enable = chv_pre_enable_dp;
> intel_encoder->enable = vlv_enable_dp;
> @@ -5815,7 +5818,7 @@ bool intel_dp_init(struct drm_device *dev,
> intel_dig_port->max_lanes = 4;
>
> intel_encoder->type = INTEL_OUTPUT_DP;
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> if (port == PORT_D)
> intel_encoder->crtc_mask = 1 << 2;
> else
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 48e8dd108f4f..4e0d025490a3 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -740,7 +740,6 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> - struct drm_device *dev = encoder->base.dev;
> enum intel_display_power_domain power_domain;
> enum port port;
> bool active = false;
> @@ -770,7 +769,8 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> * bit in port C control register does not get set. As a
> * workaround, check pipe B conf instead.
> */
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && port == PORT_C)
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> + port == PORT_C)
> enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
>
> /* Try command mode if video mode not enabled */
> @@ -1137,7 +1137,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> /*
> * escape clock divider, 20MHz, shared for A and C.
> * device ready must be off when doing this! txclkesc?
> @@ -1449,7 +1449,7 @@ void intel_dsi_init(struct drm_device *dev)
> if (!intel_bios_is_dsi_present(dev_priv, &port))
> return;
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> } else if (IS_BROXTON(dev_priv)) {
> dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index c7d9cddf4e3e..c8243dc4d2b9 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -881,7 +881,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
>
> if (HAS_PCH_CPT(dev_priv))
> hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
> - else if (IS_CHERRYVIEW(dev))
> + else if (IS_CHERRYVIEW(dev_priv))
> hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
> else
> hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
> @@ -913,7 +913,7 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
>
> if (HAS_PCH_CPT(dev_priv))
> *pipe = PORT_TO_PIPE_CPT(tmp);
> - else if (IS_CHERRYVIEW(dev))
> + else if (IS_CHERRYVIEW(dev_priv))
> *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
> else
> *pipe = PORT_TO_PIPE(tmp);
> @@ -1885,7 +1885,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> BUG();
> }
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> intel_hdmi->write_infoframe = vlv_write_infoframe;
> intel_hdmi->set_infoframes = vlv_set_infoframes;
> intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
> @@ -1959,7 +1959,7 @@ void intel_hdmi_init(struct drm_device *dev,
> }
> intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
> intel_encoder->get_config = intel_hdmi_get_config;
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
> intel_encoder->pre_enable = chv_hdmi_pre_enable;
> intel_encoder->enable = vlv_enable_hdmi;
> @@ -1982,7 +1982,7 @@ void intel_hdmi_init(struct drm_device *dev,
>
> intel_encoder->type = INTEL_OUTPUT_HDMI;
> intel_encoder->port = port;
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> if (port == PORT_D)
> intel_encoder->crtc_mask = 1 << 2;
> else
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index afb2652919d0..d04185e1edd6 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -635,7 +635,7 @@ int intel_setup_gmbus(struct drm_device *dev)
> if (HAS_PCH_NOP(dev_priv))
> return 0;
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
> else if (!HAS_GMCH_DISPLAY(dev_priv))
> dev_priv->gpio_mmio_base =
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2c5dcd3ba2c2..2107434a42e4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -322,7 +322,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
> struct drm_device *dev = &dev_priv->drm;
> u32 val;
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> POSTING_READ(FW_BLC_SELF_VLV);
> dev_priv->wm.vlv.cxsr = enable;
> @@ -7755,7 +7755,7 @@ void intel_init_pm(struct drm_device *dev)
> DRM_DEBUG_KMS("Failed to read display plane latency. "
> "Disable CxSR\n");
> }
> - } else if (IS_CHERRYVIEW(dev)) {
> + } else if (IS_CHERRYVIEW(dev_priv)) {
> vlv_setup_wm_latency(dev);
> dev_priv->display.update_wm = vlv_update_wm;
> } else if (IS_VALLEYVIEW(dev)) {
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 4a973b34348a..271a3e29ff23 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -354,7 +354,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> return false;
> }
>
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> !dev_priv->psr.link_standby) {
> DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
> return false;
> @@ -837,7 +837,7 @@ void intel_psr_init(struct drm_device *dev)
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> /* HSW and BDW require workarounds that we don't implement. */
> dev_priv->psr.link_standby = false;
> - else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> /* On VLV and CHV only standby mode is supported. */
> dev_priv->psr.link_standby = true;
> else
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index e4bb85c9c6e1..3a6e1a93aed9 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2598,7 +2598,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
> skl_display_core_init(dev_priv, resume);
> } else if (IS_BROXTON(dev_priv)) {
> bxt_display_core_init(dev_priv, resume);
> - } else if (IS_CHERRYVIEW(dev)) {
> + } else if (IS_CHERRYVIEW(dev_priv)) {
> mutex_lock(&power_domains->lock);
> chv_phy_control_init(dev_priv);
> mutex_unlock(&power_domains->lock);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index fefd3034aead..f760d5fcbe48 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -450,7 +450,7 @@ vlv_update_plane(struct drm_plane *dplane,
> if (key->flags & I915_SET_COLORKEY_SOURCE)
> sprctl |= SP_SOURCE_KEY;
>
> - if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
> + if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
> chv_update_csc(intel_plane, fb->pixel_format);
>
> I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
> @@ -944,6 +944,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
> int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
> struct drm_file *file_priv)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_intel_sprite_colorkey *set = data;
> struct drm_plane *plane;
> struct drm_plane_state *plane_state;
> @@ -955,7 +956,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
> if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
> return -EINVAL;
>
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> set->flags & I915_SET_COLORKEY_DESTINATION)
> return -EINVAL;
>
> @@ -1042,6 +1043,7 @@ static uint32_t skl_plane_formats[] = {
> int
> intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_plane *intel_plane = NULL;
> struct intel_plane_state *state = NULL;
> unsigned long possible_crtcs;
> @@ -1084,7 +1086,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
>
> case 7:
> case 8:
> - if (IS_IVYBRIDGE(to_i915(dev))) {
> + if (IS_IVYBRIDGE(dev_priv)) {
> intel_plane->can_scale = true;
> intel_plane->max_downscale = 2;
> } else {
> @@ -1092,7 +1094,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
> intel_plane->max_downscale = 1;
> }
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> intel_plane->update_plane = vlv_update_plane;
> intel_plane->disable_plane = vlv_disable_plane;
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 17/19] drm/i915: Make IS_VALLEYVIEW only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (15 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 16/19] drm/i915: Make IS_CHERRYVIEW " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 11:50 ` David Weinehall
2016-10-11 13:21 ` [PATCH 18/19] drm/i915: Make INTEL_GEN " Tvrtko Ursulin
` (3 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 944 bytes of .rodata strings and 128 bytes of .text.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_fence.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++--
drivers/gpu/drm/i915/intel_crt.c | 6 +++---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
drivers/gpu/drm/i915/intel_dp.c | 8 ++++----
drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
9 files changed, 17 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 96846ecfc224..f9f9a218d5fe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2659,7 +2659,7 @@ struct drm_i915_cmd_table {
#define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
INTEL_DEVID(dev_priv) == 0x0152 || \
INTEL_DEVID(dev_priv) == 0x015a)
-#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
+#define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.is_valleyview)
#define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
#define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index 8df1fa7234e8..d26768567252 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -448,7 +448,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
- if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
+ if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
/*
* On BDW+, swizzling is not used. We leave the CPU memory
* controller in charge of optimizing memory accesses without
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index d41517e11978..6eb11fd326fd 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1349,7 +1349,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
*/
/* 1: Registers specific to a single generation */
- if (IS_VALLEYVIEW(dev)) {
+ if (IS_VALLEYVIEW(dev_priv)) {
error->gtier[0] = I915_READ(GTIER);
error->ier = I915_READ(VLV_IER);
error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
@@ -1398,7 +1398,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
error->gtier[0] = I915_READ(GTIER);
} else if (IS_GEN2(dev)) {
error->ier = I915_READ16(IER);
- } else if (!IS_VALLEYVIEW(dev)) {
+ } else if (!IS_VALLEYVIEW(dev_priv)) {
error->ier = I915_READ(IER);
}
error->eir = I915_READ(EIR);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index d456786f5813..d92c3edf10ff 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -253,7 +253,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
if (HAS_PCH_LPT(dev_priv))
max_clock = 180000;
- else if (IS_VALLEYVIEW(dev))
+ else if (IS_VALLEYVIEW(dev_priv))
/*
* 270 MHz due to current DPLL limits,
* DAC limit supposedly 355 MHz.
@@ -423,7 +423,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
if (HAS_PCH_SPLIT(dev_priv))
return intel_ironlake_crt_detect_hotplug(connector);
- if (IS_VALLEYVIEW(dev))
+ if (IS_VALLEYVIEW(dev_priv))
return valleyview_crt_detect_hotplug(connector);
/*
@@ -850,7 +850,7 @@ void intel_crt_init(struct drm_device *dev)
if (HAS_PCH_SPLIT(dev_priv))
adpa_reg = PCH_ADPA;
- else if (IS_VALLEYVIEW(dev))
+ else if (IS_VALLEYVIEW(dev_priv))
adpa_reg = VLV_ADPA;
else
adpa_reg = ADPA;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d61a12dbbd72..c3fb9f700c7a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5876,7 +5876,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
dev_priv->max_cdclk_freq = 675000;
} else if (IS_CHERRYVIEW(dev_priv)) {
dev_priv->max_cdclk_freq = 320000;
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv)) {
dev_priv->max_cdclk_freq = 400000;
} else {
/* otherwise assume cdclk is fixed */
@@ -6840,7 +6840,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
if (IS_CHERRYVIEW(dev_priv))
chv_disable_pll(dev_priv, pipe);
- else if (IS_VALLEYVIEW(dev))
+ else if (IS_VALLEYVIEW(dev_priv))
vlv_disable_pll(dev_priv, pipe);
else
i9xx_disable_pll(intel_crtc);
@@ -8906,7 +8906,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
if (IS_CHERRYVIEW(dev_priv))
chv_crtc_clock_get(crtc, pipe_config);
- else if (IS_VALLEYVIEW(dev))
+ else if (IS_VALLEYVIEW(dev_priv))
vlv_crtc_clock_get(crtc, pipe_config);
else
i9xx_crtc_clock_get(crtc, pipe_config);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1e1ccf092e11..a2c4d5a0b704 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1350,7 +1350,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
} else if (IS_CHERRYVIEW(dev_priv)) {
divisor = chv_dpll;
count = ARRAY_SIZE(chv_dpll);
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv)) {
divisor = vlv_dpll;
count = ARRAY_SIZE(vlv_dpll);
}
@@ -1790,7 +1790,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
trans_dp &= ~TRANS_DP_ENH_FRAMING;
I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
} else {
- if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev) &&
+ if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
!IS_CHERRYVIEW(dev_priv) &&
pipe_config->limited_color_range)
intel_dp->DP |= DP_COLOR_RANGE_16_235;
@@ -3351,7 +3351,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
mask = DDI_BUF_EMP_MASK;
} else if (IS_CHERRYVIEW(dev_priv)) {
signal_levels = chv_signal_levels(intel_dp);
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv)) {
signal_levels = vlv_signal_levels(intel_dp);
} else if (IS_GEN7(dev) && port == PORT_A) {
signal_levels = gen7_edp_signal_levels(train_set);
@@ -5801,7 +5801,7 @@ bool intel_dp_init(struct drm_device *dev,
intel_encoder->enable = vlv_enable_dp;
intel_encoder->post_disable = chv_post_disable_dp;
intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv)) {
intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
intel_encoder->pre_enable = vlv_pre_enable_dp;
intel_encoder->enable = vlv_enable_dp;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index c8243dc4d2b9..501334242d38 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1965,7 +1965,7 @@ void intel_hdmi_init(struct drm_device *dev,
intel_encoder->enable = vlv_enable_hdmi;
intel_encoder->post_disable = chv_hdmi_post_disable;
intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv)) {
intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
intel_encoder->pre_enable = vlv_hdmi_pre_enable;
intel_encoder->enable = vlv_enable_hdmi;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2107434a42e4..9baffae4f9f8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7758,7 +7758,7 @@ void intel_init_pm(struct drm_device *dev)
} else if (IS_CHERRYVIEW(dev_priv)) {
vlv_setup_wm_latency(dev);
dev_priv->display.update_wm = vlv_update_wm;
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv)) {
vlv_setup_wm_latency(dev);
dev_priv->display.update_wm = vlv_update_wm;
} else if (IS_PINEVIEW(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 3a6e1a93aed9..ee56a8756c07 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2589,7 +2589,6 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
*/
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
{
- struct drm_device *dev = &dev_priv->drm;
struct i915_power_domains *power_domains = &dev_priv->power_domains;
power_domains->initializing = true;
@@ -2602,7 +2601,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
mutex_lock(&power_domains->lock);
chv_phy_control_init(dev_priv);
mutex_unlock(&power_domains->lock);
- } else if (IS_VALLEYVIEW(dev)) {
+ } else if (IS_VALLEYVIEW(dev_priv)) {
mutex_lock(&power_domains->lock);
vlv_cmnlane_wa(dev_priv);
mutex_unlock(&power_domains->lock);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 17/19] drm/i915: Make IS_VALLEYVIEW only take dev_priv
2016-10-11 13:21 ` [PATCH 17/19] drm/i915: Make IS_VALLEYVIEW " Tvrtko Ursulin
@ 2016-10-12 11:50 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 11:50 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:50PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 944 bytes of .rodata strings and 128 bytes of .text.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem_fence.c | 2 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++--
> drivers/gpu/drm/i915/intel_crt.c | 6 +++---
> drivers/gpu/drm/i915/intel_display.c | 6 +++---
> drivers/gpu/drm/i915/intel_dp.c | 8 ++++----
> drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
> 9 files changed, 17 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 96846ecfc224..f9f9a218d5fe 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2659,7 +2659,7 @@ struct drm_i915_cmd_table {
> #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
> INTEL_DEVID(dev_priv) == 0x0152 || \
> INTEL_DEVID(dev_priv) == 0x015a)
> -#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
> +#define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.is_valleyview)
> #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
> #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
> #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
> index 8df1fa7234e8..d26768567252 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence.c
> @@ -448,7 +448,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
> uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>
> - if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
> + if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
> /*
> * On BDW+, swizzling is not used. We leave the CPU memory
> * controller in charge of optimizing memory accesses without
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index d41517e11978..6eb11fd326fd 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1349,7 +1349,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> */
>
> /* 1: Registers specific to a single generation */
> - if (IS_VALLEYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv)) {
> error->gtier[0] = I915_READ(GTIER);
> error->ier = I915_READ(VLV_IER);
> error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
> @@ -1398,7 +1398,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> error->gtier[0] = I915_READ(GTIER);
> } else if (IS_GEN2(dev)) {
> error->ier = I915_READ16(IER);
> - } else if (!IS_VALLEYVIEW(dev)) {
> + } else if (!IS_VALLEYVIEW(dev_priv)) {
> error->ier = I915_READ(IER);
> }
> error->eir = I915_READ(EIR);
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index d456786f5813..d92c3edf10ff 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -253,7 +253,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
>
> if (HAS_PCH_LPT(dev_priv))
> max_clock = 180000;
> - else if (IS_VALLEYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv))
> /*
> * 270 MHz due to current DPLL limits,
> * DAC limit supposedly 355 MHz.
> @@ -423,7 +423,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
> if (HAS_PCH_SPLIT(dev_priv))
> return intel_ironlake_crt_detect_hotplug(connector);
>
> - if (IS_VALLEYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv))
> return valleyview_crt_detect_hotplug(connector);
>
> /*
> @@ -850,7 +850,7 @@ void intel_crt_init(struct drm_device *dev)
>
> if (HAS_PCH_SPLIT(dev_priv))
> adpa_reg = PCH_ADPA;
> - else if (IS_VALLEYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv))
> adpa_reg = VLV_ADPA;
> else
> adpa_reg = ADPA;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d61a12dbbd72..c3fb9f700c7a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5876,7 +5876,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> dev_priv->max_cdclk_freq = 675000;
> } else if (IS_CHERRYVIEW(dev_priv)) {
> dev_priv->max_cdclk_freq = 320000;
> - } else if (IS_VALLEYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv)) {
> dev_priv->max_cdclk_freq = 400000;
> } else {
> /* otherwise assume cdclk is fixed */
> @@ -6840,7 +6840,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
> if (IS_CHERRYVIEW(dev_priv))
> chv_disable_pll(dev_priv, pipe);
> - else if (IS_VALLEYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv))
> vlv_disable_pll(dev_priv, pipe);
> else
> i9xx_disable_pll(intel_crtc);
> @@ -8906,7 +8906,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>
> if (IS_CHERRYVIEW(dev_priv))
> chv_crtc_clock_get(crtc, pipe_config);
> - else if (IS_VALLEYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv))
> vlv_crtc_clock_get(crtc, pipe_config);
> else
> i9xx_crtc_clock_get(crtc, pipe_config);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1e1ccf092e11..a2c4d5a0b704 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1350,7 +1350,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
> } else if (IS_CHERRYVIEW(dev_priv)) {
> divisor = chv_dpll;
> count = ARRAY_SIZE(chv_dpll);
> - } else if (IS_VALLEYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv)) {
> divisor = vlv_dpll;
> count = ARRAY_SIZE(vlv_dpll);
> }
> @@ -1790,7 +1790,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
> trans_dp &= ~TRANS_DP_ENH_FRAMING;
> I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
> } else {
> - if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev) &&
> + if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> !IS_CHERRYVIEW(dev_priv) &&
> pipe_config->limited_color_range)
> intel_dp->DP |= DP_COLOR_RANGE_16_235;
> @@ -3351,7 +3351,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> mask = DDI_BUF_EMP_MASK;
> } else if (IS_CHERRYVIEW(dev_priv)) {
> signal_levels = chv_signal_levels(intel_dp);
> - } else if (IS_VALLEYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv)) {
> signal_levels = vlv_signal_levels(intel_dp);
> } else if (IS_GEN7(dev) && port == PORT_A) {
> signal_levels = gen7_edp_signal_levels(train_set);
> @@ -5801,7 +5801,7 @@ bool intel_dp_init(struct drm_device *dev,
> intel_encoder->enable = vlv_enable_dp;
> intel_encoder->post_disable = chv_post_disable_dp;
> intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
> - } else if (IS_VALLEYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv)) {
> intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
> intel_encoder->pre_enable = vlv_pre_enable_dp;
> intel_encoder->enable = vlv_enable_dp;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index c8243dc4d2b9..501334242d38 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1965,7 +1965,7 @@ void intel_hdmi_init(struct drm_device *dev,
> intel_encoder->enable = vlv_enable_hdmi;
> intel_encoder->post_disable = chv_hdmi_post_disable;
> intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
> - } else if (IS_VALLEYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv)) {
> intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
> intel_encoder->pre_enable = vlv_hdmi_pre_enable;
> intel_encoder->enable = vlv_enable_hdmi;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2107434a42e4..9baffae4f9f8 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7758,7 +7758,7 @@ void intel_init_pm(struct drm_device *dev)
> } else if (IS_CHERRYVIEW(dev_priv)) {
> vlv_setup_wm_latency(dev);
> dev_priv->display.update_wm = vlv_update_wm;
> - } else if (IS_VALLEYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv)) {
> vlv_setup_wm_latency(dev);
> dev_priv->display.update_wm = vlv_update_wm;
> } else if (IS_PINEVIEW(dev)) {
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 3a6e1a93aed9..ee56a8756c07 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2589,7 +2589,6 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
> */
> void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
> {
> - struct drm_device *dev = &dev_priv->drm;
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
>
> power_domains->initializing = true;
> @@ -2602,7 +2601,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
> mutex_lock(&power_domains->lock);
> chv_phy_control_init(dev_priv);
> mutex_unlock(&power_domains->lock);
> - } else if (IS_VALLEYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv)) {
> mutex_lock(&power_domains->lock);
> vlv_cmnlane_wa(dev_priv);
> mutex_unlock(&power_domains->lock);
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 18/19] drm/i915: Make INTEL_GEN only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (16 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 17/19] drm/i915: Make IS_VALLEYVIEW " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 11:44 ` David Weinehall
2016-10-11 13:21 ` [PATCH 19/19] drm/i915: Make IS_GEN macros " Tvrtko Ursulin
` (2 subsequent siblings)
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 968 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_render_state.c | 6 +++---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 8 ++++----
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f9f9a218d5fe..3f38b9755763 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2604,8 +2604,8 @@ struct drm_i915_cmd_table {
__p; \
})
#define INTEL_INFO(p) (&__I915__(p)->info)
-#define INTEL_GEN(p) (INTEL_INFO(p)->gen)
+#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
#define REVID_FOREVER 0xff
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 95b7e9afd5f8..a98c0f42badd 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -72,9 +72,9 @@ render_state_get_rodata(const struct drm_i915_gem_request *req)
static int render_state_setup(struct render_state *so)
{
- struct drm_device *dev = so->vma->vm->dev;
+ struct drm_i915_private *dev_priv = to_i915(so->vma->vm->dev);
const struct intel_renderstate_rodata *rodata = so->rodata;
- const bool has_64bit_reloc = INTEL_GEN(dev) >= 8;
+ const bool has_64bit_reloc = INTEL_GEN(dev_priv) >= 8;
unsigned int i = 0, reloc_index = 0;
struct page *page;
u32 *d;
@@ -115,7 +115,7 @@ static int render_state_setup(struct render_state *so)
so->aux_batch_offset = i * sizeof(u32);
- if (HAS_POOLED_EU(dev)) {
+ if (HAS_POOLED_EU(dev_priv)) {
/*
* We always program 3x6 pool config but depending upon which
* subslice is disabled HW drops down to appropriate config
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c3fb9f700c7a..eda38e53f68a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12452,7 +12452,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
struct drm_framebuffer *fb = plane_state->fb;
int ret;
- if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
+ if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
ret = skl_update_scaler_plane(
to_intel_crtc_state(crtc_state),
to_intel_plane_state(plane_state));
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index f760d5fcbe48..8b4748839c07 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -753,7 +753,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
struct intel_crtc_state *crtc_state,
struct intel_plane_state *state)
{
- struct drm_device *dev = plane->dev;
+ struct drm_i915_private *dev_priv = to_i915(plane->dev);
struct drm_crtc *crtc = state->base.crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_plane *intel_plane = to_intel_plane(plane);
@@ -797,7 +797,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
}
/* setup can_scale, min_scale, max_scale */
- if (INTEL_INFO(dev)->gen >= 9) {
+ if (INTEL_GEN(dev_priv) >= 9) {
/* use scaler when colorkey is not required */
if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
can_scale = 1;
@@ -913,7 +913,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
- if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
+ if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
width_bytes > 4096 || fb->pitches[0] > 4096)) {
DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
return -EINVAL;
@@ -932,7 +932,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
dst->y1 = crtc_y;
dst->y2 = crtc_y + crtc_h;
- if (INTEL_GEN(dev) >= 9) {
+ if (INTEL_GEN(dev_priv) >= 9) {
ret = skl_check_plane_surface(state);
if (ret)
return ret;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 18/19] drm/i915: Make INTEL_GEN only take dev_priv
2016-10-11 13:21 ` [PATCH 18/19] drm/i915: Make INTEL_GEN " Tvrtko Ursulin
@ 2016-10-12 11:44 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 11:44 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:51PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 968 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem_render_state.c | 6 +++---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_sprite.c | 8 ++++----
> 4 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f9f9a218d5fe..3f38b9755763 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2604,8 +2604,8 @@ struct drm_i915_cmd_table {
> __p; \
> })
> #define INTEL_INFO(p) (&__I915__(p)->info)
> -#define INTEL_GEN(p) (INTEL_INFO(p)->gen)
>
> +#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
> #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
>
> #define REVID_FOREVER 0xff
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
> index 95b7e9afd5f8..a98c0f42badd 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
> @@ -72,9 +72,9 @@ render_state_get_rodata(const struct drm_i915_gem_request *req)
>
> static int render_state_setup(struct render_state *so)
> {
> - struct drm_device *dev = so->vma->vm->dev;
> + struct drm_i915_private *dev_priv = to_i915(so->vma->vm->dev);
> const struct intel_renderstate_rodata *rodata = so->rodata;
> - const bool has_64bit_reloc = INTEL_GEN(dev) >= 8;
> + const bool has_64bit_reloc = INTEL_GEN(dev_priv) >= 8;
> unsigned int i = 0, reloc_index = 0;
> struct page *page;
> u32 *d;
> @@ -115,7 +115,7 @@ static int render_state_setup(struct render_state *so)
>
> so->aux_batch_offset = i * sizeof(u32);
>
> - if (HAS_POOLED_EU(dev)) {
> + if (HAS_POOLED_EU(dev_priv)) {
> /*
> * We always program 3x6 pool config but depending upon which
> * subslice is disabled HW drops down to appropriate config
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c3fb9f700c7a..eda38e53f68a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12452,7 +12452,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
> struct drm_framebuffer *fb = plane_state->fb;
> int ret;
>
> - if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
> + if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
> ret = skl_update_scaler_plane(
> to_intel_crtc_state(crtc_state),
> to_intel_plane_state(plane_state));
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index f760d5fcbe48..8b4748839c07 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -753,7 +753,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
> struct intel_crtc_state *crtc_state,
> struct intel_plane_state *state)
> {
> - struct drm_device *dev = plane->dev;
> + struct drm_i915_private *dev_priv = to_i915(plane->dev);
> struct drm_crtc *crtc = state->base.crtc;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_plane *intel_plane = to_intel_plane(plane);
> @@ -797,7 +797,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
> }
>
> /* setup can_scale, min_scale, max_scale */
> - if (INTEL_INFO(dev)->gen >= 9) {
> + if (INTEL_GEN(dev_priv) >= 9) {
> /* use scaler when colorkey is not required */
> if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
> can_scale = 1;
> @@ -913,7 +913,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
>
> width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
>
> - if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
> + if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
> width_bytes > 4096 || fb->pitches[0] > 4096)) {
> DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
> return -EINVAL;
> @@ -932,7 +932,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
> dst->y1 = crtc_y;
> dst->y2 = crtc_y + crtc_h;
>
> - if (INTEL_GEN(dev) >= 9) {
> + if (INTEL_GEN(dev_priv) >= 9) {
> ret = skl_check_plane_surface(state);
> if (ret)
> return ret;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 19/19] drm/i915: Make IS_GEN macros only take dev_priv
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (17 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 18/19] drm/i915: Make INTEL_GEN " Tvrtko Ursulin
@ 2016-10-11 13:21 ` Tvrtko Ursulin
2016-10-12 11:50 ` David Weinehall
2016-10-11 13:49 ` ✗ Fi.CI.BAT: warning for .rodata.str diet Patchwork
2016-10-13 10:50 ` ✓ Fi.CI.BAT: success for .rodata.str diet (rev2) Patchwork
20 siblings, 1 reply; 46+ messages in thread
From: Tvrtko Ursulin @ 2016-10-11 13:21 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Saves 1416 bytes of .rodata strings.
v2: Add parantheses around dev_priv. (Ville Syrjala)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 6 +--
drivers/gpu/drm/i915/i915_drv.h | 16 +++---
drivers/gpu/drm/i915/i915_gem.c | 8 +--
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +-
drivers/gpu/drm/i915/i915_gem_fence.c | 9 ++--
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++--
drivers/gpu/drm/i915/i915_gem_stolen.c | 4 +-
drivers/gpu/drm/i915/i915_gem_tiling.c | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++--
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_suspend.c | 4 +-
drivers/gpu/drm/i915/intel_crt.c | 6 +--
drivers/gpu/drm/i915/intel_display.c | 41 ++++++++-------
drivers/gpu/drm/i915/intel_dp.c | 20 +++----
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_fifo_underrun.c | 6 +--
drivers/gpu/drm/i915/intel_guc_loader.c | 3 +-
drivers/gpu/drm/i915/intel_lvds.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 83 +++++++++++++++---------------
drivers/gpu/drm/i915/intel_sprite.c | 4 +-
21 files changed, 126 insertions(+), 124 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 20689f1cd719..3a42df3a29e5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4552,7 +4552,7 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
else if (IS_VALLEYVIEW(dev_priv))
num_levels = 1;
else
- num_levels = ilk_wm_max_level(dev) + 1;
+ num_levels = ilk_wm_max_level(dev_priv) + 1;
drm_modeset_lock_all(dev);
@@ -4668,7 +4668,7 @@ static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
else if (IS_VALLEYVIEW(dev_priv))
num_levels = 1;
else
- num_levels = ilk_wm_max_level(dev) + 1;
+ num_levels = ilk_wm_max_level(dev_priv) + 1;
if (len >= sizeof(tmp))
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5e7b6a1cb2c8..c1956855feb6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -174,7 +174,7 @@ static void intel_detect_pch(struct drm_device *dev)
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_IBX;
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
- WARN_ON(!IS_GEN5(dev));
+ WARN_ON(!IS_GEN5(dev_priv));
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
@@ -884,7 +884,7 @@ static int i915_mmio_setup(struct drm_device *dev)
int mmio_bar;
int mmio_size;
- mmio_bar = IS_GEN2(dev) ? 1 : 0;
+ mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
/*
* Before gen4, the registers and the GTT are behind different BARs.
* However, from gen4 onwards, the registers and the GTT are shared
@@ -1037,7 +1037,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
pci_set_master(pdev);
/* overlay on gen2 is broken and can't address above 1G */
- if (IS_GEN2(dev)) {
+ if (IS_GEN2(dev_priv)) {
ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
if (ret) {
DRM_ERROR("failed to set DMA mask\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3f38b9755763..a05665af31be 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2742,14 +2742,14 @@ struct drm_i915_cmd_table {
* have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
* chips, etc.).
*/
-#define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
-#define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
-#define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
-#define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
-#define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
-#define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
-#define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
-#define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
+#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
+#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
+#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
+#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
+#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
+#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
+#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
+#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
#define ENGINE_MASK(id) BIT(id)
#define RENDER_RING ENGINE_MASK(RCS)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8c362899674a..b79392605256 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4308,15 +4308,15 @@ void i915_gem_init_swizzling(struct drm_device *dev)
I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
DISP_TILE_SURFACE_SWIZZLING);
- if (IS_GEN5(dev))
+ if (IS_GEN5(dev_priv))
return;
I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev_priv))
I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
- else if (IS_GEN7(dev))
+ else if (IS_GEN7(dev_priv))
I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
- else if (IS_GEN8(dev))
+ else if (IS_GEN8(dev_priv))
I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
else
BUG();
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 72c7c1855e70..11bb3ae94e00 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -572,7 +572,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
struct drm_i915_gem_relocation_entry *reloc,
struct reloc_cache *cache)
{
- struct drm_device *dev = obj->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
struct drm_gem_object *target_obj;
struct drm_i915_gem_object *target_i915_obj;
struct i915_vma *target_vma;
@@ -591,7 +591,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
* pipe_control writes because the gpu doesn't properly redirect them
* through the ppgtt for non_secure batchbuffers. */
- if (unlikely(IS_GEN6(dev) &&
+ if (unlikely(IS_GEN6(dev_priv) &&
reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
PIN_GLOBAL);
diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index d26768567252..bedf2278df16 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -487,19 +487,20 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
}
}
- } else if (IS_GEN5(dev)) {
+ } else if (IS_GEN5(dev_priv)) {
/* On Ironlake whatever DRAM config, GPU always do
* same swizzling setup.
*/
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9;
- } else if (IS_GEN2(dev)) {
+ } else if (IS_GEN2(dev_priv)) {
/* As far as we know, the 865 doesn't have these bit 6
* swizzling issues.
*/
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
- } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
+ } else if (IS_MOBILE(dev_priv) || (IS_GEN3(dev_priv) &&
+ !IS_G33(dev_priv))) {
uint32_t dcc;
/* On 9xx chipsets, channel interleave by the CPU is
@@ -537,7 +538,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
}
/* check for L-shaped memory aka modified enhanced addressing */
- if (IS_GEN4(dev) &&
+ if (IS_GEN4(dev_priv) &&
!(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4211b9a4a918..c35ba67d1a5d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2058,11 +2058,11 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
int ret;
ppgtt->base.pte_encode = ggtt->base.pte_encode;
- if (intel_vgpu_active(dev_priv) || IS_GEN6(dev))
+ if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv))
ppgtt->switch_mm = gen6_mm_switch;
else if (IS_HASWELL(dev_priv))
ppgtt->switch_mm = hsw_mm_switch;
- else if (IS_GEN7(dev))
+ else if (IS_GEN7(dev_priv))
ppgtt->switch_mm = gen7_mm_switch;
else
BUG();
@@ -2159,6 +2159,8 @@ static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
int i915_ppgtt_init_hw(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
gtt_write_workarounds(dev);
/* In the case of execlists, PPGTT is enabled by the context descriptor
@@ -2170,9 +2172,9 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
if (!USES_PPGTT(dev))
return 0;
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev_priv))
gen6_ppgtt_enable(dev);
- else if (IS_GEN7(dev))
+ else if (IS_GEN7(dev_priv))
gen7_ppgtt_enable(dev);
else if (INTEL_INFO(dev)->gen >= 8)
gen8_ppgtt_enable(dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index d1b40bce0249..f4f6d3a48b05 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -215,7 +215,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
u64 ggtt_start, ggtt_end;
ggtt_start = I915_READ(PGTBL_CTL);
- if (IS_GEN4(dev))
+ if (IS_GEN4(dev_priv))
ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) |
(ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
else
@@ -271,7 +271,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
* GEN3 firmware likes to smash pci bridges into the stolen
* range. Apparently this works.
*/
- if (r == NULL && !IS_GEN3(dev)) {
+ if (r == NULL && !IS_GEN3(dev_priv)) {
DRM_ERROR("conflict detected with stolen region: [0x%08x - 0x%08x]\n",
base, base + (uint32_t)ggtt->stolen_size);
base = 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 89d1d234a1b4..c21bc0068d20 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -72,7 +72,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
if (tiling_mode > I915_TILING_LAST)
return false;
- if (IS_GEN2(dev) ||
+ if (IS_GEN2(dev_priv) ||
(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
tile_width = 128;
else
@@ -91,7 +91,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
if (stride > 8192)
return false;
- if (IS_GEN3(dev)) {
+ if (IS_GEN3(dev_priv)) {
if (size > I830_FENCE_MAX_SIZE_VAL << 20)
return false;
} else {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 6eb11fd326fd..629ac567dcbb 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -442,7 +442,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
}
- if (IS_GEN7(dev))
+ if (IS_GEN7(dev_priv))
err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
@@ -1355,7 +1355,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
}
- if (IS_GEN7(dev))
+ if (IS_GEN7(dev_priv))
error->err_int = I915_READ(GEN7_ERR_INT);
if (INTEL_INFO(dev)->gen >= 8) {
@@ -1363,7 +1363,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
}
- if (IS_GEN6(dev)) {
+ if (IS_GEN6(dev_priv)) {
error->forcewake = I915_READ_FW(FORCEWAKE);
error->gab_ctl = I915_READ(GAB_CTL);
error->gfx_mode = I915_READ(GFX_MODE);
@@ -1380,7 +1380,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
}
/* 3: Feature specific registers */
- if (IS_GEN6(dev) || IS_GEN7(dev)) {
+ if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
error->gam_ecochk = I915_READ(GAM_ECOCHK);
error->gac_eco = I915_READ(GAC_ECO_BITS);
}
@@ -1396,7 +1396,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
} else if (HAS_PCH_SPLIT(dev_priv)) {
error->ier = I915_READ(DEIER);
error->gtier[0] = I915_READ(GTIER);
- } else if (IS_GEN2(dev)) {
+ } else if (IS_GEN2(dev_priv)) {
error->ier = I915_READ16(IER);
} else if (!IS_VALLEYVIEW(dev_priv)) {
error->ier = I915_READ(IER);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 079ba7cfc971..d610df92ad1f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3333,7 +3333,7 @@ static void ironlake_irq_reset(struct drm_device *dev)
I915_WRITE(HWSTAM, 0xffffffff);
GEN5_IRQ_RESET(DE);
- if (IS_GEN7(dev))
+ if (IS_GEN7(dev_priv))
I915_WRITE(GEN7_ERR_INT, 0xffffffff);
gen5_gt_irq_reset(dev);
@@ -3599,7 +3599,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
}
gt_irqs |= GT_RENDER_USER_INTERRUPT;
- if (IS_GEN5(dev)) {
+ if (IS_GEN5(dev_priv)) {
gt_irqs |= ILK_BSD_USER_INTERRUPT;
} else {
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 7870856fccd0..344cbf39cfa9 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -70,7 +70,7 @@ int i915_save_state(struct drm_device *dev)
i915_save_display(dev);
- if (IS_GEN4(dev))
+ if (IS_GEN4(dev_priv))
pci_read_config_word(pdev, GCDGMBUS,
&dev_priv->regfile.saveGCDGMBUS);
@@ -116,7 +116,7 @@ int i915_restore_state(struct drm_device *dev)
i915_gem_restore_fences(dev);
- if (IS_GEN4(dev))
+ if (IS_GEN4(dev_priv))
pci_write_config_word(pdev, GCDGMBUS,
dev_priv->regfile.saveGCDGMBUS);
i915_restore_display(dev);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index d92c3edf10ff..a97151fcb9f4 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -259,7 +259,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
* DAC limit supposedly 355 MHz.
*/
max_clock = 270000;
- else if (IS_GEN3(dev) || IS_GEN4(dev))
+ else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
max_clock = 400000;
else
max_clock = 350000;
@@ -567,7 +567,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
/* Set the border color to purple. */
I915_WRITE(bclrpat_reg, 0x500050);
- if (!IS_GEN2(dev)) {
+ if (!IS_GEN2(dev_priv)) {
uint32_t pipeconf = I915_READ(pipeconf_reg);
I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
POSTING_READ(pipeconf_reg);
@@ -899,7 +899,7 @@ void intel_crt_init(struct drm_device *dev)
else
crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
connector->interlace_allowed = 0;
else
connector->interlace_allowed = 1;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index eda38e53f68a..f3931c66116f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1045,7 +1045,7 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
u32 line1, line2;
u32 line_mask;
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
line_mask = DSL_LINEMASK_GEN2;
else
line_mask = DSL_LINEMASK_GEN3;
@@ -3947,7 +3947,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
temp = I915_READ(reg);
temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_PATTERN_2;
- if (IS_GEN6(dev)) {
+ if (IS_GEN6(dev_priv)) {
temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
/* SNB-B */
temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
@@ -4985,7 +4985,7 @@ intel_post_enable_primary(struct drm_crtc *crtc)
* FIXME: Need to fix the logic to work when we turn off all planes
* but leave the pipe running.
*/
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
/* Underruns don't always raise interrupts, so check manually. */
@@ -5008,7 +5008,7 @@ intel_pre_disable_primary(struct drm_crtc *crtc)
* FIXME: Need to fix the logic to work when we turn off all planes
* but leave the pipe running.
*/
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
/*
@@ -6775,7 +6775,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc->active = true;
- if (!IS_GEN2(dev))
+ if (!IS_GEN2(dev_priv))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
intel_encoders_pre_enable(crtc, pipe_config, old_state);
@@ -6823,7 +6823,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
* On gen2 planes are double buffered but the pipe isn't, so we must
* wait for planes to fully turn off before disabling the pipe.
*/
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
intel_wait_for_vblank(dev, pipe);
intel_encoders_disable(crtc, old_crtc_state, old_state);
@@ -6848,7 +6848,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
- if (!IS_GEN2(dev))
+ if (!IS_GEN2(dev_priv))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
}
@@ -9846,7 +9846,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
/* We currently do not free assignements of panel fitters on
* ivb/hsw (since we don't use the higher upscaling modes which
* differentiates them) so just WARN about this case for now. */
- if (IS_GEN7(dev)) {
+ if (IS_GEN7(dev_priv)) {
WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
PF_PIPE_SEL_IVB(crtc->pipe));
}
@@ -11322,7 +11322,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
return dev_priv->vbt.lvds_ssc_freq;
else if (HAS_PCH_SPLIT(dev_priv))
return 120000;
- else if (!IS_GEN2(dev))
+ else if (!IS_GEN2(dev_priv))
return 96000;
else
return 48000;
@@ -11355,7 +11355,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
}
- if (!IS_GEN2(dev)) {
+ if (!IS_GEN2(dev_priv)) {
if (IS_PINEVIEW(dev))
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
@@ -11854,6 +11854,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_ring *ring = req->ring;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t plane_bit = 0;
@@ -11882,7 +11883,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
* 48bits addresses, and we need a NOOP for the batch size to
* stay even.
*/
- if (IS_GEN8(dev))
+ if (IS_GEN8(dev_priv))
len += 2;
}
@@ -11919,7 +11920,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
DERRMR_PIPEB_PRI_FLIP_DONE |
DERRMR_PIPEC_PRI_FLIP_DONE));
- if (IS_GEN8(dev))
+ if (IS_GEN8(dev_priv))
intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
MI_SRM_LRM_GLOBAL_GTT);
else
@@ -11928,7 +11929,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
intel_ring_emit_reg(ring, DERRMR);
intel_ring_emit(ring,
i915_ggtt_offset(req->engine->scratch) + 256);
- if (IS_GEN8(dev)) {
+ if (IS_GEN8(dev_priv)) {
intel_ring_emit(ring, 0);
intel_ring_emit(ring, MI_NOOP);
}
@@ -15322,7 +15323,7 @@ static bool has_edp_a(struct drm_device *dev)
if ((I915_READ(DP_A) & DP_DETECTED) == 0)
return false;
- if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
+ if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
return false;
return true;
@@ -15524,7 +15525,7 @@ static void intel_setup_outputs(struct drm_device *dev)
}
intel_dsi_init(dev);
- } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
+ } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
bool found = false;
if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
@@ -15558,7 +15559,7 @@ static void intel_setup_outputs(struct drm_device *dev)
if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
intel_dp_init(dev, DP_D, PORT_D);
- } else if (IS_GEN2(dev))
+ } else if (IS_GEN2(dev_priv))
intel_dvo_init(dev);
if (SUPPORTS_TV(dev))
@@ -16383,10 +16384,10 @@ void intel_modeset_init(struct drm_device *dev)
}
}
- if (IS_GEN2(dev)) {
+ if (IS_GEN2(dev_priv)) {
dev->mode_config.max_width = 2048;
dev->mode_config.max_height = 2048;
- } else if (IS_GEN3(dev)) {
+ } else if (IS_GEN3(dev_priv)) {
dev->mode_config.max_width = 4096;
dev->mode_config.max_height = 4096;
} else {
@@ -16397,7 +16398,7 @@ void intel_modeset_init(struct drm_device *dev)
if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
dev->mode_config.cursor_height = 1023;
- } else if (IS_GEN2(dev)) {
+ } else if (IS_GEN2(dev_priv)) {
dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
} else {
@@ -16918,7 +16919,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_wm_get_hw_state(dev);
- else if (IS_GEN9(dev))
+ else if (IS_GEN9(dev_priv))
skl_wm_get_hw_state(dev);
else if (HAS_PCH_SPLIT(dev_priv))
ilk_wm_get_hw_state(dev);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a2c4d5a0b704..ba3ac2661625 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1767,7 +1767,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
/* Split out the IBX/CPU vs CPT settings */
- if (IS_GEN7(dev) && port == PORT_A) {
+ if (IS_GEN7(dev_priv) && port == PORT_A) {
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
intel_dp->DP |= DP_SYNC_HS_HIGH;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -2113,7 +2113,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
pp = ironlake_get_pp_control(intel_dp);
- if (IS_GEN5(dev)) {
+ if (IS_GEN5(dev_priv)) {
/* ILK workaround: disable reset around power sequence */
pp &= ~PANEL_POWER_RESET;
I915_WRITE(pp_ctrl_reg, pp);
@@ -2121,7 +2121,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
}
pp |= PANEL_POWER_ON;
- if (!IS_GEN5(dev))
+ if (!IS_GEN5(dev_priv))
pp |= PANEL_POWER_RESET;
I915_WRITE(pp_ctrl_reg, pp);
@@ -2130,7 +2130,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
wait_panel_on(intel_dp);
intel_dp->last_power_on = jiffies;
- if (IS_GEN5(dev)) {
+ if (IS_GEN5(dev_priv)) {
pp |= PANEL_POWER_RESET; /* restore panel reset bit */
I915_WRITE(pp_ctrl_reg, pp);
POSTING_READ(pp_ctrl_reg);
@@ -2443,7 +2443,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
if (!(tmp & DP_PORT_EN))
goto out;
- if (IS_GEN7(dev) && port == PORT_A) {
+ if (IS_GEN7(dev_priv) && port == PORT_A) {
*pipe = PORT_TO_PIPE_CPT(tmp);
} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
enum pipe p;
@@ -2661,7 +2661,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
}
I915_WRITE(DP_TP_CTL(port), temp);
- } else if ((IS_GEN7(dev) && port == PORT_A) ||
+ } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
*DP &= ~DP_LINK_TRAIN_MASK_CPT;
@@ -2990,7 +2990,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
- else if (IS_GEN7(dev) && port == PORT_A)
+ else if (IS_GEN7(dev_priv) && port == PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
@@ -3353,10 +3353,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
signal_levels = chv_signal_levels(intel_dp);
} else if (IS_VALLEYVIEW(dev_priv)) {
signal_levels = vlv_signal_levels(intel_dp);
- } else if (IS_GEN7(dev) && port == PORT_A) {
+ } else if (IS_GEN7(dev_priv) && port == PORT_A) {
signal_levels = gen7_edp_signal_levels(train_set);
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
- } else if (IS_GEN6(dev) && port == PORT_A) {
+ } else if (IS_GEN6(dev_priv) && port == PORT_A) {
signal_levels = gen6_edp_signal_levels(train_set);
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
} else {
@@ -3444,7 +3444,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("\n");
- if ((IS_GEN7(dev) && port == PORT_A) ||
+ if ((IS_GEN7(dev_priv) && port == PORT_A) ||
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
DP &= ~DP_LINK_TRAIN_MASK_CPT;
DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f48e79ae2ac6..9f571770c1db 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1722,7 +1722,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
/* intel_pm.c */
void intel_init_clock_gating(struct drm_device *dev);
void intel_suspend_hw(struct drm_device *dev);
-int ilk_wm_max_level(const struct drm_device *dev);
+int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
void intel_update_watermarks(struct drm_crtc *crtc);
void intel_init_pm(struct drm_device *dev);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index 076893cc3890..3018f4f589c8 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -256,11 +256,11 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
if (HAS_GMCH_DISPLAY(dev_priv))
i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
- else if (IS_GEN5(dev) || IS_GEN6(dev))
+ else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
- else if (IS_GEN7(dev))
+ else if (IS_GEN7(dev_priv))
ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
- else if (IS_GEN8(dev) || IS_GEN9(dev))
+ else if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
return old;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 5d5d609ed5e9..cc7df0c57982 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -347,7 +347,6 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
{
struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
- struct drm_device *dev = &dev_priv->drm;
struct i915_vma *vma;
int ret;
@@ -390,7 +389,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
else
I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
- if (IS_GEN9(dev)) {
+ if (IS_GEN9(dev_priv)) {
/* DOP Clock Gating Enable for GuC clocks */
I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
I915_READ(GEN7_MISCCPCTL)));
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 1c47f99917e6..199b90c7907a 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -1071,7 +1071,7 @@ void intel_lvds_init(struct drm_device *dev)
intel_encoder->cloneable = 0;
if (HAS_PCH_SPLIT(dev_priv))
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
- else if (IS_GEN4(dev))
+ else if (IS_GEN4(dev_priv))
intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
else
intel_encoder->crtc_mask = (1 << 1);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9baffae4f9f8..d9eb10f2bb78 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1530,7 +1530,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
if (IS_I945GM(dev))
wm_info = &i945_wm_info;
- else if (!IS_GEN2(dev))
+ else if (!IS_GEN2(dev_priv))
wm_info = &i915_wm_info;
else
wm_info = &i830_a_wm_info;
@@ -1540,7 +1540,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode;
int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
cpp = 4;
adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
@@ -1554,7 +1554,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
planea_wm = wm_info->max_wm;
}
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
wm_info = &i830_bc_wm_info;
fifo_size = dev_priv->display.get_fifo_size(dev, 1);
@@ -1562,7 +1562,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *adjusted_mode;
int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
- if (IS_GEN2(dev))
+ if (IS_GEN2(dev_priv))
cpp = 4;
adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
@@ -2082,10 +2082,10 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
{
struct drm_i915_private *dev_priv = to_i915(dev);
- if (IS_GEN9(dev)) {
+ if (IS_GEN9(dev_priv)) {
uint32_t val;
int ret, i;
- int level, max_level = ilk_wm_max_level(dev);
+ int level, max_level = ilk_wm_max_level(dev_priv);
/* read the first set of memory latencies[0:3] */
val = 0; /* data0 to be programmed to 0 for first set */
@@ -2184,10 +2184,11 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
}
}
-static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
+static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
+ uint16_t wm[5])
{
/* ILK sprite LP0 latency is 1300 ns */
- if (IS_GEN5(dev))
+ if (IS_GEN5(dev_priv))
wm[0] = 13;
}
@@ -2203,10 +2204,8 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
wm[3] *= 2;
}
-int ilk_wm_max_level(const struct drm_device *dev)
+int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
-
/* how many WM levels are we expecting */
if (INTEL_GEN(dev_priv) >= 9)
return 7;
@@ -2218,11 +2217,11 @@ int ilk_wm_max_level(const struct drm_device *dev)
return 2;
}
-static void intel_print_wm_latency(struct drm_device *dev,
+static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
const char *name,
const uint16_t wm[8])
{
- int level, max_level = ilk_wm_max_level(dev);
+ int level, max_level = ilk_wm_max_level(dev_priv);
for (level = 0; level <= max_level; level++) {
unsigned int latency = wm[level];
@@ -2237,7 +2236,7 @@ static void intel_print_wm_latency(struct drm_device *dev,
* - latencies are in us on gen9.
* - before then, WM1+ latency values are in 0.5us units
*/
- if (IS_GEN9(dev))
+ if (IS_GEN9(dev_priv))
latency *= 10;
else if (level > 0)
latency *= 5;
@@ -2251,7 +2250,7 @@ static void intel_print_wm_latency(struct drm_device *dev,
static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
uint16_t wm[5], uint16_t min)
{
- int level, max_level = ilk_wm_max_level(&dev_priv->drm);
+ int level, max_level = ilk_wm_max_level(dev_priv);
if (wm[0] >= min)
return false;
@@ -2280,9 +2279,9 @@ static void snb_wm_latency_quirk(struct drm_device *dev)
return;
DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
- intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
- intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
- intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
+ intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
+ intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
+ intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
}
static void ilk_setup_wm_latency(struct drm_device *dev)
@@ -2296,14 +2295,14 @@ static void ilk_setup_wm_latency(struct drm_device *dev)
memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
sizeof(dev_priv->wm.pri_latency));
- intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
+ intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
- intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
- intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
- intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
+ intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
+ intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
+ intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev_priv))
snb_wm_latency_quirk(dev);
}
@@ -2312,7 +2311,7 @@ static void skl_setup_wm_latency(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev);
intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
- intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
+ intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
}
static bool ilk_validate_pipe_wm(struct drm_device *dev,
@@ -2350,7 +2349,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
struct intel_plane_state *pristate = NULL;
struct intel_plane_state *sprstate = NULL;
struct intel_plane_state *curstate = NULL;
- int level, max_level = ilk_wm_max_level(dev), usable_level;
+ int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
struct ilk_wm_maximums max;
pipe_wm = &cstate->wm.ilk.optimal;
@@ -2437,7 +2436,7 @@ static int ilk_compute_intermediate_wm(struct drm_device *dev,
{
struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
- int level, max_level = ilk_wm_max_level(dev);
+ int level, max_level = ilk_wm_max_level(to_i915(dev));
/*
* Start with the final, target watermarks, then combine with the
@@ -2521,7 +2520,7 @@ static void ilk_wm_merge(struct drm_device *dev,
struct intel_pipe_wm *merged)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- int level, max_level = ilk_wm_max_level(dev);
+ int level, max_level = ilk_wm_max_level(dev_priv);
int last_enabled_level = max_level;
/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
@@ -2561,7 +2560,7 @@ static void ilk_wm_merge(struct drm_device *dev,
* What we should check here is whether FBC can be
* enabled sometime later.
*/
- if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
+ if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
intel_fbc_is_active(dev_priv)) {
for (level = 2; level <= max_level; level++) {
struct intel_wm_level *wm = &merged->wm[level];
@@ -2661,7 +2660,7 @@ static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
struct intel_pipe_wm *r1,
struct intel_pipe_wm *r2)
{
- int level, max_level = ilk_wm_max_level(dev);
+ int level, max_level = ilk_wm_max_level(to_i915(dev));
int level1 = 0, level2 = 0;
for (level = 1; level <= max_level; level++) {
@@ -3035,7 +3034,7 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
continue;
/* Find the highest enabled wm level for this plane */
- for (level = ilk_wm_max_level(dev);
+ for (level = ilk_wm_max_level(dev_priv);
intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
{ }
@@ -3776,7 +3775,7 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
{
struct drm_device *dev = cstate->base.crtc->dev;
const struct drm_i915_private *dev_priv = to_i915(dev);
- int level, max_level = ilk_wm_max_level(dev);
+ int level, max_level = ilk_wm_max_level(dev_priv);
int ret;
for (level = 0; level <= max_level; level++) {
@@ -3797,7 +3796,7 @@ static void skl_compute_wm_results(struct drm_device *dev,
struct skl_wm_values *r,
struct intel_crtc *intel_crtc)
{
- int level, max_level = ilk_wm_max_level(dev);
+ int level, max_level = ilk_wm_max_level(to_i915(dev));
enum pipe pipe = intel_crtc->pipe;
uint32_t temp;
int i;
@@ -3866,7 +3865,7 @@ void skl_write_plane_wm(struct intel_crtc *intel_crtc,
struct drm_crtc *crtc = &intel_crtc->base;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- int level, max_level = ilk_wm_max_level(dev);
+ int level, max_level = ilk_wm_max_level(dev_priv);
enum pipe pipe = intel_crtc->pipe;
for (level = 0; level <= max_level; level++) {
@@ -3887,7 +3886,7 @@ void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
struct drm_crtc *crtc = &intel_crtc->base;
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- int level, max_level = ilk_wm_max_level(dev);
+ int level, max_level = ilk_wm_max_level(dev_priv);
enum pipe pipe = intel_crtc->pipe;
for (level = 0; level <= max_level; level++) {
@@ -4331,7 +4330,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
int level, i, max_level;
uint32_t temp;
- max_level = ilk_wm_max_level(dev);
+ max_level = ilk_wm_max_level(dev_priv);
hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
@@ -4431,7 +4430,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
active->linetime = hw->wm_linetime[pipe];
} else {
- int level, max_level = ilk_wm_max_level(dev);
+ int level, max_level = ilk_wm_max_level(dev_priv);
/*
* For inactive pipes, all watermark levels
@@ -7729,7 +7728,7 @@ void intel_init_pm(struct drm_device *dev)
/* For cxsr */
if (IS_PINEVIEW(dev))
i915_pineview_get_mem_freq(dev);
- else if (IS_GEN5(dev))
+ else if (IS_GEN5(dev_priv))
i915_ironlake_get_mem_freq(dev);
/* For FIFO watermark updates */
@@ -7740,9 +7739,9 @@ void intel_init_pm(struct drm_device *dev)
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev);
- if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
+ if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
- (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
+ (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
dev_priv->display.compute_intermediate_wm =
@@ -7778,12 +7777,12 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.update_wm = pineview_update_wm;
} else if (IS_G4X(dev_priv)) {
dev_priv->display.update_wm = g4x_update_wm;
- } else if (IS_GEN4(dev)) {
+ } else if (IS_GEN4(dev_priv)) {
dev_priv->display.update_wm = i965_update_wm;
- } else if (IS_GEN3(dev)) {
+ } else if (IS_GEN3(dev_priv)) {
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
- } else if (IS_GEN2(dev)) {
+ } else if (IS_GEN2(dev_priv)) {
if (INTEL_INFO(dev)->num_pipes == 1) {
dev_priv->display.update_wm = i845_update_wm;
dev_priv->display.get_fifo_size = i845_get_fifo_size;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 8b4748839c07..c7d9a20e370d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -680,7 +680,7 @@ ilk_update_plane(struct drm_plane *plane,
if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
dvscntr |= DVS_TILED;
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev_priv))
dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
/* Sizes are 0 based */
@@ -1075,7 +1075,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
intel_plane->update_plane = ilk_update_plane;
intel_plane->disable_plane = ilk_disable_plane;
- if (IS_GEN6(dev)) {
+ if (IS_GEN6(dev_priv)) {
plane_formats = snb_plane_formats;
num_plane_formats = ARRAY_SIZE(snb_plane_formats);
} else {
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH 19/19] drm/i915: Make IS_GEN macros only take dev_priv
2016-10-11 13:21 ` [PATCH 19/19] drm/i915: Make IS_GEN macros " Tvrtko Ursulin
@ 2016-10-12 11:50 ` David Weinehall
0 siblings, 0 replies; 46+ messages in thread
From: David Weinehall @ 2016-10-12 11:50 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Intel-gfx
On Tue, Oct 11, 2016 at 02:21:52PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Saves 1416 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Do note though, that this is a *very* large patch, and I suspect that
you'll have trouble getting it merged...
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.c | 6 +--
> drivers/gpu/drm/i915/i915_drv.h | 16 +++---
> drivers/gpu/drm/i915/i915_gem.c | 8 +--
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +-
> drivers/gpu/drm/i915/i915_gem_fence.c | 9 ++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++--
> drivers/gpu/drm/i915/i915_gem_stolen.c | 4 +-
> drivers/gpu/drm/i915/i915_gem_tiling.c | 4 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++--
> drivers/gpu/drm/i915/i915_irq.c | 4 +-
> drivers/gpu/drm/i915/i915_suspend.c | 4 +-
> drivers/gpu/drm/i915/intel_crt.c | 6 +--
> drivers/gpu/drm/i915/intel_display.c | 41 ++++++++-------
> drivers/gpu/drm/i915/intel_dp.c | 20 +++----
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_fifo_underrun.c | 6 +--
> drivers/gpu/drm/i915/intel_guc_loader.c | 3 +-
> drivers/gpu/drm/i915/intel_lvds.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 83 +++++++++++++++---------------
> drivers/gpu/drm/i915/intel_sprite.c | 4 +-
> 21 files changed, 126 insertions(+), 124 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 20689f1cd719..3a42df3a29e5 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4552,7 +4552,7 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
> else if (IS_VALLEYVIEW(dev_priv))
> num_levels = 1;
> else
> - num_levels = ilk_wm_max_level(dev) + 1;
> + num_levels = ilk_wm_max_level(dev_priv) + 1;
>
> drm_modeset_lock_all(dev);
>
> @@ -4668,7 +4668,7 @@ static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
> else if (IS_VALLEYVIEW(dev_priv))
> num_levels = 1;
> else
> - num_levels = ilk_wm_max_level(dev) + 1;
> + num_levels = ilk_wm_max_level(dev_priv) + 1;
>
> if (len >= sizeof(tmp))
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5e7b6a1cb2c8..c1956855feb6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -174,7 +174,7 @@ static void intel_detect_pch(struct drm_device *dev)
> if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_IBX;
> DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
> - WARN_ON(!IS_GEN5(dev));
> + WARN_ON(!IS_GEN5(dev_priv));
> } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_CPT;
> DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> @@ -884,7 +884,7 @@ static int i915_mmio_setup(struct drm_device *dev)
> int mmio_bar;
> int mmio_size;
>
> - mmio_bar = IS_GEN2(dev) ? 1 : 0;
> + mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
> /*
> * Before gen4, the registers and the GTT are behind different BARs.
> * However, from gen4 onwards, the registers and the GTT are shared
> @@ -1037,7 +1037,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
> pci_set_master(pdev);
>
> /* overlay on gen2 is broken and can't address above 1G */
> - if (IS_GEN2(dev)) {
> + if (IS_GEN2(dev_priv)) {
> ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
> if (ret) {
> DRM_ERROR("failed to set DMA mask\n");
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3f38b9755763..a05665af31be 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2742,14 +2742,14 @@ struct drm_i915_cmd_table {
> * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
> * chips, etc.).
> */
> -#define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
> -#define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
> -#define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
> -#define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
> -#define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
> -#define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
> -#define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
> -#define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
> +#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
> +#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
> +#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
> +#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
> +#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
> +#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
> +#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
> +#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
>
> #define ENGINE_MASK(id) BIT(id)
> #define RENDER_RING ENGINE_MASK(RCS)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 8c362899674a..b79392605256 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4308,15 +4308,15 @@ void i915_gem_init_swizzling(struct drm_device *dev)
> I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> DISP_TILE_SURFACE_SWIZZLING);
>
> - if (IS_GEN5(dev))
> + if (IS_GEN5(dev_priv))
> return;
>
> I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
> - else if (IS_GEN7(dev))
> + else if (IS_GEN7(dev_priv))
> I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> - else if (IS_GEN8(dev))
> + else if (IS_GEN8(dev_priv))
> I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
> else
> BUG();
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 72c7c1855e70..11bb3ae94e00 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -572,7 +572,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
> struct drm_i915_gem_relocation_entry *reloc,
> struct reloc_cache *cache)
> {
> - struct drm_device *dev = obj->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
> struct drm_gem_object *target_obj;
> struct drm_i915_gem_object *target_i915_obj;
> struct i915_vma *target_vma;
> @@ -591,7 +591,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
> /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
> * pipe_control writes because the gpu doesn't properly redirect them
> * through the ppgtt for non_secure batchbuffers. */
> - if (unlikely(IS_GEN6(dev) &&
> + if (unlikely(IS_GEN6(dev_priv) &&
> reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
> ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
> PIN_GLOBAL);
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
> index d26768567252..bedf2278df16 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence.c
> @@ -487,19 +487,20 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> }
> }
> - } else if (IS_GEN5(dev)) {
> + } else if (IS_GEN5(dev_priv)) {
> /* On Ironlake whatever DRAM config, GPU always do
> * same swizzling setup.
> */
> swizzle_x = I915_BIT_6_SWIZZLE_9_10;
> swizzle_y = I915_BIT_6_SWIZZLE_9;
> - } else if (IS_GEN2(dev)) {
> + } else if (IS_GEN2(dev_priv)) {
> /* As far as we know, the 865 doesn't have these bit 6
> * swizzling issues.
> */
> swizzle_x = I915_BIT_6_SWIZZLE_NONE;
> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> - } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
> + } else if (IS_MOBILE(dev_priv) || (IS_GEN3(dev_priv) &&
> + !IS_G33(dev_priv))) {
> uint32_t dcc;
>
> /* On 9xx chipsets, channel interleave by the CPU is
> @@ -537,7 +538,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
> }
>
> /* check for L-shaped memory aka modified enhanced addressing */
> - if (IS_GEN4(dev) &&
> + if (IS_GEN4(dev_priv) &&
> !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
> swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 4211b9a4a918..c35ba67d1a5d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2058,11 +2058,11 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
> int ret;
>
> ppgtt->base.pte_encode = ggtt->base.pte_encode;
> - if (intel_vgpu_active(dev_priv) || IS_GEN6(dev))
> + if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv))
> ppgtt->switch_mm = gen6_mm_switch;
> else if (IS_HASWELL(dev_priv))
> ppgtt->switch_mm = hsw_mm_switch;
> - else if (IS_GEN7(dev))
> + else if (IS_GEN7(dev_priv))
> ppgtt->switch_mm = gen7_mm_switch;
> else
> BUG();
> @@ -2159,6 +2159,8 @@ static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
>
> int i915_ppgtt_init_hw(struct drm_device *dev)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> gtt_write_workarounds(dev);
>
> /* In the case of execlists, PPGTT is enabled by the context descriptor
> @@ -2170,9 +2172,9 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
> if (!USES_PPGTT(dev))
> return 0;
>
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> gen6_ppgtt_enable(dev);
> - else if (IS_GEN7(dev))
> + else if (IS_GEN7(dev_priv))
> gen7_ppgtt_enable(dev);
> else if (INTEL_INFO(dev)->gen >= 8)
> gen8_ppgtt_enable(dev);
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index d1b40bce0249..f4f6d3a48b05 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -215,7 +215,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
> u64 ggtt_start, ggtt_end;
>
> ggtt_start = I915_READ(PGTBL_CTL);
> - if (IS_GEN4(dev))
> + if (IS_GEN4(dev_priv))
> ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) |
> (ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
> else
> @@ -271,7 +271,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
> * GEN3 firmware likes to smash pci bridges into the stolen
> * range. Apparently this works.
> */
> - if (r == NULL && !IS_GEN3(dev)) {
> + if (r == NULL && !IS_GEN3(dev_priv)) {
> DRM_ERROR("conflict detected with stolen region: [0x%08x - 0x%08x]\n",
> base, base + (uint32_t)ggtt->stolen_size);
> base = 0;
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index 89d1d234a1b4..c21bc0068d20 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -72,7 +72,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> if (tiling_mode > I915_TILING_LAST)
> return false;
>
> - if (IS_GEN2(dev) ||
> + if (IS_GEN2(dev_priv) ||
> (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
> tile_width = 128;
> else
> @@ -91,7 +91,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> if (stride > 8192)
> return false;
>
> - if (IS_GEN3(dev)) {
> + if (IS_GEN3(dev_priv)) {
> if (size > I830_FENCE_MAX_SIZE_VAL << 20)
> return false;
> } else {
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 6eb11fd326fd..629ac567dcbb 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -442,7 +442,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
> }
>
> - if (IS_GEN7(dev))
> + if (IS_GEN7(dev_priv))
> err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
>
> for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
> @@ -1355,7 +1355,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
> }
>
> - if (IS_GEN7(dev))
> + if (IS_GEN7(dev_priv))
> error->err_int = I915_READ(GEN7_ERR_INT);
>
> if (INTEL_INFO(dev)->gen >= 8) {
> @@ -1363,7 +1363,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
> }
>
> - if (IS_GEN6(dev)) {
> + if (IS_GEN6(dev_priv)) {
> error->forcewake = I915_READ_FW(FORCEWAKE);
> error->gab_ctl = I915_READ(GAB_CTL);
> error->gfx_mode = I915_READ(GFX_MODE);
> @@ -1380,7 +1380,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> }
>
> /* 3: Feature specific registers */
> - if (IS_GEN6(dev) || IS_GEN7(dev)) {
> + if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
> error->gam_ecochk = I915_READ(GAM_ECOCHK);
> error->gac_eco = I915_READ(GAC_ECO_BITS);
> }
> @@ -1396,7 +1396,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> error->ier = I915_READ(DEIER);
> error->gtier[0] = I915_READ(GTIER);
> - } else if (IS_GEN2(dev)) {
> + } else if (IS_GEN2(dev_priv)) {
> error->ier = I915_READ16(IER);
> } else if (!IS_VALLEYVIEW(dev_priv)) {
> error->ier = I915_READ(IER);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 079ba7cfc971..d610df92ad1f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3333,7 +3333,7 @@ static void ironlake_irq_reset(struct drm_device *dev)
> I915_WRITE(HWSTAM, 0xffffffff);
>
> GEN5_IRQ_RESET(DE);
> - if (IS_GEN7(dev))
> + if (IS_GEN7(dev_priv))
> I915_WRITE(GEN7_ERR_INT, 0xffffffff);
>
> gen5_gt_irq_reset(dev);
> @@ -3599,7 +3599,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
> }
>
> gt_irqs |= GT_RENDER_USER_INTERRUPT;
> - if (IS_GEN5(dev)) {
> + if (IS_GEN5(dev_priv)) {
> gt_irqs |= ILK_BSD_USER_INTERRUPT;
> } else {
> gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 7870856fccd0..344cbf39cfa9 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -70,7 +70,7 @@ int i915_save_state(struct drm_device *dev)
>
> i915_save_display(dev);
>
> - if (IS_GEN4(dev))
> + if (IS_GEN4(dev_priv))
> pci_read_config_word(pdev, GCDGMBUS,
> &dev_priv->regfile.saveGCDGMBUS);
>
> @@ -116,7 +116,7 @@ int i915_restore_state(struct drm_device *dev)
>
> i915_gem_restore_fences(dev);
>
> - if (IS_GEN4(dev))
> + if (IS_GEN4(dev_priv))
> pci_write_config_word(pdev, GCDGMBUS,
> dev_priv->regfile.saveGCDGMBUS);
> i915_restore_display(dev);
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index d92c3edf10ff..a97151fcb9f4 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -259,7 +259,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
> * DAC limit supposedly 355 MHz.
> */
> max_clock = 270000;
> - else if (IS_GEN3(dev) || IS_GEN4(dev))
> + else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
> max_clock = 400000;
> else
> max_clock = 350000;
> @@ -567,7 +567,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
> /* Set the border color to purple. */
> I915_WRITE(bclrpat_reg, 0x500050);
>
> - if (!IS_GEN2(dev)) {
> + if (!IS_GEN2(dev_priv)) {
> uint32_t pipeconf = I915_READ(pipeconf_reg);
> I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
> POSTING_READ(pipeconf_reg);
> @@ -899,7 +899,7 @@ void intel_crt_init(struct drm_device *dev)
> else
> crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> connector->interlace_allowed = 0;
> else
> connector->interlace_allowed = 1;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index eda38e53f68a..f3931c66116f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1045,7 +1045,7 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
> u32 line1, line2;
> u32 line_mask;
>
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> line_mask = DSL_LINEMASK_GEN2;
> else
> line_mask = DSL_LINEMASK_GEN3;
> @@ -3947,7 +3947,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
> temp = I915_READ(reg);
> temp &= ~FDI_LINK_TRAIN_NONE;
> temp |= FDI_LINK_TRAIN_PATTERN_2;
> - if (IS_GEN6(dev)) {
> + if (IS_GEN6(dev_priv)) {
> temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> /* SNB-B */
> temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
> @@ -4985,7 +4985,7 @@ intel_post_enable_primary(struct drm_crtc *crtc)
> * FIXME: Need to fix the logic to work when we turn off all planes
> * but leave the pipe running.
> */
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>
> /* Underruns don't always raise interrupts, so check manually. */
> @@ -5008,7 +5008,7 @@ intel_pre_disable_primary(struct drm_crtc *crtc)
> * FIXME: Need to fix the logic to work when we turn off all planes
> * but leave the pipe running.
> */
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>
> /*
> @@ -6775,7 +6775,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_crtc->active = true;
>
> - if (!IS_GEN2(dev))
> + if (!IS_GEN2(dev_priv))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>
> intel_encoders_pre_enable(crtc, pipe_config, old_state);
> @@ -6823,7 +6823,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> * On gen2 planes are double buffered but the pipe isn't, so we must
> * wait for planes to fully turn off before disabling the pipe.
> */
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> intel_wait_for_vblank(dev, pipe);
>
> intel_encoders_disable(crtc, old_crtc_state, old_state);
> @@ -6848,7 +6848,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
>
> intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
>
> - if (!IS_GEN2(dev))
> + if (!IS_GEN2(dev_priv))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> }
>
> @@ -9846,7 +9846,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
> /* We currently do not free assignements of panel fitters on
> * ivb/hsw (since we don't use the higher upscaling modes which
> * differentiates them) so just WARN about this case for now. */
> - if (IS_GEN7(dev)) {
> + if (IS_GEN7(dev_priv)) {
> WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
> PF_PIPE_SEL_IVB(crtc->pipe));
> }
> @@ -11322,7 +11322,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
> return dev_priv->vbt.lvds_ssc_freq;
> else if (HAS_PCH_SPLIT(dev_priv))
> return 120000;
> - else if (!IS_GEN2(dev))
> + else if (!IS_GEN2(dev_priv))
> return 96000;
> else
> return 48000;
> @@ -11355,7 +11355,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
> }
>
> - if (!IS_GEN2(dev)) {
> + if (!IS_GEN2(dev_priv)) {
> if (IS_PINEVIEW(dev))
> clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
> DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
> @@ -11854,6 +11854,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> struct drm_i915_gem_request *req,
> uint32_t flags)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_ring *ring = req->ring;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> uint32_t plane_bit = 0;
> @@ -11882,7 +11883,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> * 48bits addresses, and we need a NOOP for the batch size to
> * stay even.
> */
> - if (IS_GEN8(dev))
> + if (IS_GEN8(dev_priv))
> len += 2;
> }
>
> @@ -11919,7 +11920,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
> DERRMR_PIPEB_PRI_FLIP_DONE |
> DERRMR_PIPEC_PRI_FLIP_DONE));
> - if (IS_GEN8(dev))
> + if (IS_GEN8(dev_priv))
> intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
> MI_SRM_LRM_GLOBAL_GTT);
> else
> @@ -11928,7 +11929,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> intel_ring_emit_reg(ring, DERRMR);
> intel_ring_emit(ring,
> i915_ggtt_offset(req->engine->scratch) + 256);
> - if (IS_GEN8(dev)) {
> + if (IS_GEN8(dev_priv)) {
> intel_ring_emit(ring, 0);
> intel_ring_emit(ring, MI_NOOP);
> }
> @@ -15322,7 +15323,7 @@ static bool has_edp_a(struct drm_device *dev)
> if ((I915_READ(DP_A) & DP_DETECTED) == 0)
> return false;
>
> - if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
> + if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
> return false;
>
> return true;
> @@ -15524,7 +15525,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> }
>
> intel_dsi_init(dev);
> - } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
> + } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
> bool found = false;
>
> if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
> @@ -15558,7 +15559,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>
> if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
> intel_dp_init(dev, DP_D, PORT_D);
> - } else if (IS_GEN2(dev))
> + } else if (IS_GEN2(dev_priv))
> intel_dvo_init(dev);
>
> if (SUPPORTS_TV(dev))
> @@ -16383,10 +16384,10 @@ void intel_modeset_init(struct drm_device *dev)
> }
> }
>
> - if (IS_GEN2(dev)) {
> + if (IS_GEN2(dev_priv)) {
> dev->mode_config.max_width = 2048;
> dev->mode_config.max_height = 2048;
> - } else if (IS_GEN3(dev)) {
> + } else if (IS_GEN3(dev_priv)) {
> dev->mode_config.max_width = 4096;
> dev->mode_config.max_height = 4096;
> } else {
> @@ -16397,7 +16398,7 @@ void intel_modeset_init(struct drm_device *dev)
> if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
> dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
> dev->mode_config.cursor_height = 1023;
> - } else if (IS_GEN2(dev)) {
> + } else if (IS_GEN2(dev_priv)) {
> dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
> dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
> } else {
> @@ -16918,7 +16919,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_wm_get_hw_state(dev);
> - else if (IS_GEN9(dev))
> + else if (IS_GEN9(dev_priv))
> skl_wm_get_hw_state(dev);
> else if (HAS_PCH_SPLIT(dev_priv))
> ilk_wm_get_hw_state(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a2c4d5a0b704..ba3ac2661625 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1767,7 +1767,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
>
> /* Split out the IBX/CPU vs CPT settings */
>
> - if (IS_GEN7(dev) && port == PORT_A) {
> + if (IS_GEN7(dev_priv) && port == PORT_A) {
> if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> intel_dp->DP |= DP_SYNC_HS_HIGH;
> if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> @@ -2113,7 +2113,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
>
> pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> pp = ironlake_get_pp_control(intel_dp);
> - if (IS_GEN5(dev)) {
> + if (IS_GEN5(dev_priv)) {
> /* ILK workaround: disable reset around power sequence */
> pp &= ~PANEL_POWER_RESET;
> I915_WRITE(pp_ctrl_reg, pp);
> @@ -2121,7 +2121,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
> }
>
> pp |= PANEL_POWER_ON;
> - if (!IS_GEN5(dev))
> + if (!IS_GEN5(dev_priv))
> pp |= PANEL_POWER_RESET;
>
> I915_WRITE(pp_ctrl_reg, pp);
> @@ -2130,7 +2130,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
> wait_panel_on(intel_dp);
> intel_dp->last_power_on = jiffies;
>
> - if (IS_GEN5(dev)) {
> + if (IS_GEN5(dev_priv)) {
> pp |= PANEL_POWER_RESET; /* restore panel reset bit */
> I915_WRITE(pp_ctrl_reg, pp);
> POSTING_READ(pp_ctrl_reg);
> @@ -2443,7 +2443,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
> if (!(tmp & DP_PORT_EN))
> goto out;
>
> - if (IS_GEN7(dev) && port == PORT_A) {
> + if (IS_GEN7(dev_priv) && port == PORT_A) {
> *pipe = PORT_TO_PIPE_CPT(tmp);
> } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
> enum pipe p;
> @@ -2661,7 +2661,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> }
> I915_WRITE(DP_TP_CTL(port), temp);
>
> - } else if ((IS_GEN7(dev) && port == PORT_A) ||
> + } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
> (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> *DP &= ~DP_LINK_TRAIN_MASK_CPT;
>
> @@ -2990,7 +2990,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> - else if (IS_GEN7(dev) && port == PORT_A)
> + else if (IS_GEN7(dev_priv) && port == PORT_A)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> @@ -3353,10 +3353,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> signal_levels = chv_signal_levels(intel_dp);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> signal_levels = vlv_signal_levels(intel_dp);
> - } else if (IS_GEN7(dev) && port == PORT_A) {
> + } else if (IS_GEN7(dev_priv) && port == PORT_A) {
> signal_levels = gen7_edp_signal_levels(train_set);
> mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
> - } else if (IS_GEN6(dev) && port == PORT_A) {
> + } else if (IS_GEN6(dev_priv) && port == PORT_A) {
> signal_levels = gen6_edp_signal_levels(train_set);
> mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
> } else {
> @@ -3444,7 +3444,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
>
> DRM_DEBUG_KMS("\n");
>
> - if ((IS_GEN7(dev) && port == PORT_A) ||
> + if ((IS_GEN7(dev_priv) && port == PORT_A) ||
> (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> DP &= ~DP_LINK_TRAIN_MASK_CPT;
> DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index f48e79ae2ac6..9f571770c1db 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1722,7 +1722,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> /* intel_pm.c */
> void intel_init_clock_gating(struct drm_device *dev);
> void intel_suspend_hw(struct drm_device *dev);
> -int ilk_wm_max_level(const struct drm_device *dev);
> +int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
> void intel_update_watermarks(struct drm_crtc *crtc);
> void intel_init_pm(struct drm_device *dev);
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> index 076893cc3890..3018f4f589c8 100644
> --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> @@ -256,11 +256,11 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
>
> if (HAS_GMCH_DISPLAY(dev_priv))
> i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
> - else if (IS_GEN5(dev) || IS_GEN6(dev))
> + else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
> ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
> - else if (IS_GEN7(dev))
> + else if (IS_GEN7(dev_priv))
> ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
> - else if (IS_GEN8(dev) || IS_GEN9(dev))
> + else if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
> broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
>
> return old;
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 5d5d609ed5e9..cc7df0c57982 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -347,7 +347,6 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> {
> struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> - struct drm_device *dev = &dev_priv->drm;
> struct i915_vma *vma;
> int ret;
>
> @@ -390,7 +389,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> else
> I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>
> - if (IS_GEN9(dev)) {
> + if (IS_GEN9(dev_priv)) {
> /* DOP Clock Gating Enable for GuC clocks */
> I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
> I915_READ(GEN7_MISCCPCTL)));
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 1c47f99917e6..199b90c7907a 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -1071,7 +1071,7 @@ void intel_lvds_init(struct drm_device *dev)
> intel_encoder->cloneable = 0;
> if (HAS_PCH_SPLIT(dev_priv))
> intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
> - else if (IS_GEN4(dev))
> + else if (IS_GEN4(dev_priv))
> intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
> else
> intel_encoder->crtc_mask = (1 << 1);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9baffae4f9f8..d9eb10f2bb78 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1530,7 +1530,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
>
> if (IS_I945GM(dev))
> wm_info = &i945_wm_info;
> - else if (!IS_GEN2(dev))
> + else if (!IS_GEN2(dev_priv))
> wm_info = &i915_wm_info;
> else
> wm_info = &i830_a_wm_info;
> @@ -1540,7 +1540,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *adjusted_mode;
> int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> cpp = 4;
>
> adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
> @@ -1554,7 +1554,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> planea_wm = wm_info->max_wm;
> }
>
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> wm_info = &i830_bc_wm_info;
>
> fifo_size = dev_priv->display.get_fifo_size(dev, 1);
> @@ -1562,7 +1562,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *adjusted_mode;
> int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> cpp = 4;
>
> adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
> @@ -2082,10 +2082,10 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (IS_GEN9(dev)) {
> + if (IS_GEN9(dev_priv)) {
> uint32_t val;
> int ret, i;
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
>
> /* read the first set of memory latencies[0:3] */
> val = 0; /* data0 to be programmed to 0 for first set */
> @@ -2184,10 +2184,11 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
> }
> }
>
> -static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
> +static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
> + uint16_t wm[5])
> {
> /* ILK sprite LP0 latency is 1300 ns */
> - if (IS_GEN5(dev))
> + if (IS_GEN5(dev_priv))
> wm[0] = 13;
> }
>
> @@ -2203,10 +2204,8 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
> wm[3] *= 2;
> }
>
> -int ilk_wm_max_level(const struct drm_device *dev)
> +int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> -
> /* how many WM levels are we expecting */
> if (INTEL_GEN(dev_priv) >= 9)
> return 7;
> @@ -2218,11 +2217,11 @@ int ilk_wm_max_level(const struct drm_device *dev)
> return 2;
> }
>
> -static void intel_print_wm_latency(struct drm_device *dev,
> +static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
> const char *name,
> const uint16_t wm[8])
> {
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
>
> for (level = 0; level <= max_level; level++) {
> unsigned int latency = wm[level];
> @@ -2237,7 +2236,7 @@ static void intel_print_wm_latency(struct drm_device *dev,
> * - latencies are in us on gen9.
> * - before then, WM1+ latency values are in 0.5us units
> */
> - if (IS_GEN9(dev))
> + if (IS_GEN9(dev_priv))
> latency *= 10;
> else if (level > 0)
> latency *= 5;
> @@ -2251,7 +2250,7 @@ static void intel_print_wm_latency(struct drm_device *dev,
> static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
> uint16_t wm[5], uint16_t min)
> {
> - int level, max_level = ilk_wm_max_level(&dev_priv->drm);
> + int level, max_level = ilk_wm_max_level(dev_priv);
>
> if (wm[0] >= min)
> return false;
> @@ -2280,9 +2279,9 @@ static void snb_wm_latency_quirk(struct drm_device *dev)
> return;
>
> DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
> - intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
> - intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
> - intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
> + intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
> + intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
> + intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
> }
>
> static void ilk_setup_wm_latency(struct drm_device *dev)
> @@ -2296,14 +2295,14 @@ static void ilk_setup_wm_latency(struct drm_device *dev)
> memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
> sizeof(dev_priv->wm.pri_latency));
>
> - intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
> + intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
> intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
>
> - intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
> - intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
> - intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
> + intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
> + intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
> + intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
>
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> snb_wm_latency_quirk(dev);
> }
>
> @@ -2312,7 +2311,7 @@ static void skl_setup_wm_latency(struct drm_device *dev)
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
> - intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
> + intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
> }
>
> static bool ilk_validate_pipe_wm(struct drm_device *dev,
> @@ -2350,7 +2349,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
> struct intel_plane_state *pristate = NULL;
> struct intel_plane_state *sprstate = NULL;
> struct intel_plane_state *curstate = NULL;
> - int level, max_level = ilk_wm_max_level(dev), usable_level;
> + int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
> struct ilk_wm_maximums max;
>
> pipe_wm = &cstate->wm.ilk.optimal;
> @@ -2437,7 +2436,7 @@ static int ilk_compute_intermediate_wm(struct drm_device *dev,
> {
> struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
> struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(to_i915(dev));
>
> /*
> * Start with the final, target watermarks, then combine with the
> @@ -2521,7 +2520,7 @@ static void ilk_wm_merge(struct drm_device *dev,
> struct intel_pipe_wm *merged)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
> int last_enabled_level = max_level;
>
> /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
> @@ -2561,7 +2560,7 @@ static void ilk_wm_merge(struct drm_device *dev,
> * What we should check here is whether FBC can be
> * enabled sometime later.
> */
> - if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
> + if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
> intel_fbc_is_active(dev_priv)) {
> for (level = 2; level <= max_level; level++) {
> struct intel_wm_level *wm = &merged->wm[level];
> @@ -2661,7 +2660,7 @@ static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
> struct intel_pipe_wm *r1,
> struct intel_pipe_wm *r2)
> {
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(to_i915(dev));
> int level1 = 0, level2 = 0;
>
> for (level = 1; level <= max_level; level++) {
> @@ -3035,7 +3034,7 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
> continue;
>
> /* Find the highest enabled wm level for this plane */
> - for (level = ilk_wm_max_level(dev);
> + for (level = ilk_wm_max_level(dev_priv);
> intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
> { }
>
> @@ -3776,7 +3775,7 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
> {
> struct drm_device *dev = cstate->base.crtc->dev;
> const struct drm_i915_private *dev_priv = to_i915(dev);
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
> int ret;
>
> for (level = 0; level <= max_level; level++) {
> @@ -3797,7 +3796,7 @@ static void skl_compute_wm_results(struct drm_device *dev,
> struct skl_wm_values *r,
> struct intel_crtc *intel_crtc)
> {
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(to_i915(dev));
> enum pipe pipe = intel_crtc->pipe;
> uint32_t temp;
> int i;
> @@ -3866,7 +3865,7 @@ void skl_write_plane_wm(struct intel_crtc *intel_crtc,
> struct drm_crtc *crtc = &intel_crtc->base;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
> enum pipe pipe = intel_crtc->pipe;
>
> for (level = 0; level <= max_level; level++) {
> @@ -3887,7 +3886,7 @@ void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
> struct drm_crtc *crtc = &intel_crtc->base;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
> enum pipe pipe = intel_crtc->pipe;
>
> for (level = 0; level <= max_level; level++) {
> @@ -4331,7 +4330,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
> int level, i, max_level;
> uint32_t temp;
>
> - max_level = ilk_wm_max_level(dev);
> + max_level = ilk_wm_max_level(dev_priv);
>
> hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
>
> @@ -4431,7 +4430,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
> active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
> active->linetime = hw->wm_linetime[pipe];
> } else {
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
>
> /*
> * For inactive pipes, all watermark levels
> @@ -7729,7 +7728,7 @@ void intel_init_pm(struct drm_device *dev)
> /* For cxsr */
> if (IS_PINEVIEW(dev))
> i915_pineview_get_mem_freq(dev);
> - else if (IS_GEN5(dev))
> + else if (IS_GEN5(dev_priv))
> i915_ironlake_get_mem_freq(dev);
>
> /* For FIFO watermark updates */
> @@ -7740,9 +7739,9 @@ void intel_init_pm(struct drm_device *dev)
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> ilk_setup_wm_latency(dev);
>
> - if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
> + if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
> dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
> - (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
> + (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
> dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
> dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
> dev_priv->display.compute_intermediate_wm =
> @@ -7778,12 +7777,12 @@ void intel_init_pm(struct drm_device *dev)
> dev_priv->display.update_wm = pineview_update_wm;
> } else if (IS_G4X(dev_priv)) {
> dev_priv->display.update_wm = g4x_update_wm;
> - } else if (IS_GEN4(dev)) {
> + } else if (IS_GEN4(dev_priv)) {
> dev_priv->display.update_wm = i965_update_wm;
> - } else if (IS_GEN3(dev)) {
> + } else if (IS_GEN3(dev_priv)) {
> dev_priv->display.update_wm = i9xx_update_wm;
> dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
> - } else if (IS_GEN2(dev)) {
> + } else if (IS_GEN2(dev_priv)) {
> if (INTEL_INFO(dev)->num_pipes == 1) {
> dev_priv->display.update_wm = i845_update_wm;
> dev_priv->display.get_fifo_size = i845_get_fifo_size;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 8b4748839c07..c7d9a20e370d 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -680,7 +680,7 @@ ilk_update_plane(struct drm_plane *plane,
> if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
> dvscntr |= DVS_TILED;
>
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
>
> /* Sizes are 0 based */
> @@ -1075,7 +1075,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
> intel_plane->update_plane = ilk_update_plane;
> intel_plane->disable_plane = ilk_disable_plane;
>
> - if (IS_GEN6(dev)) {
> + if (IS_GEN6(dev_priv)) {
> plane_formats = snb_plane_formats;
> num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> } else {
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread
* ✗ Fi.CI.BAT: warning for .rodata.str diet
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (18 preceding siblings ...)
2016-10-11 13:21 ` [PATCH 19/19] drm/i915: Make IS_GEN macros " Tvrtko Ursulin
@ 2016-10-11 13:49 ` Patchwork
2016-10-13 10:50 ` ✓ Fi.CI.BAT: success for .rodata.str diet (rev2) Patchwork
20 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2016-10-11 13:49 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: .rodata.str diet
URL : https://patchwork.freedesktop.org/series/13583/
State : warning
== Summary ==
Series 13583v1 .rodata.str diet
https://patchwork.freedesktop.org/api/1.0/series/13583/revisions/1/mbox/
Test kms_cursor_legacy:
Subgroup basic-flip-after-cursor-varying-size:
dmesg-warn -> PASS (fi-skl-6700k)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a:
dmesg-warn -> PASS (fi-ivb-3770)
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (fi-byt-j1900)
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass -> DMESG-WARN (fi-skl-6700hq)
Test vgem_basic:
Subgroup unload:
pass -> SKIP (fi-hsw-4770)
pass -> SKIP (fi-skl-6700k)
skip -> PASS (fi-ilk-650)
fi-bdw-5557u total:248 pass:231 dwarn:0 dfail:0 fail:0 skip:17
fi-bsw-n3050 total:248 pass:204 dwarn:0 dfail:0 fail:0 skip:44
fi-bxt-t5700 total:248 pass:217 dwarn:0 dfail:0 fail:0 skip:31
fi-byt-j1900 total:248 pass:213 dwarn:2 dfail:0 fail:1 skip:32
fi-hsw-4770 total:248 pass:224 dwarn:0 dfail:0 fail:0 skip:24
fi-hsw-4770r total:248 pass:224 dwarn:0 dfail:0 fail:0 skip:24
fi-ilk-650 total:248 pass:185 dwarn:0 dfail:0 fail:2 skip:61
fi-ivb-3520m total:248 pass:221 dwarn:0 dfail:0 fail:0 skip:27
fi-ivb-3770 total:248 pass:221 dwarn:0 dfail:0 fail:0 skip:27
fi-kbl-7200u total:248 pass:222 dwarn:0 dfail:0 fail:0 skip:26
fi-skl-6260u total:248 pass:232 dwarn:0 dfail:0 fail:0 skip:16
fi-skl-6700hq total:248 pass:223 dwarn:1 dfail:0 fail:0 skip:24
fi-skl-6700k total:248 pass:221 dwarn:1 dfail:0 fail:0 skip:26
fi-skl-6770hq total:248 pass:231 dwarn:1 dfail:0 fail:1 skip:15
fi-snb-2520m total:248 pass:211 dwarn:0 dfail:0 fail:0 skip:37
fi-snb-2600 total:248 pass:209 dwarn:0 dfail:0 fail:0 skip:39
Results at /archive/results/CI_IGT_test/Patchwork_2672/
660541d3c3f78795aa8bb7aa65747b0aa93cb463 drm-intel-nightly: 2016y-10m-11d-11h-21m-29s UTC integration manifest
ad0d4d6 drm/i915: Make IS_GEN macros only take dev_priv
3213fb2 drm/i915: Make INTEL_GEN only take dev_priv
c7388ca drm/i915: Make IS_VALLEYVIEW only take dev_priv
88fa29c drm/i915: Make IS_CHERRYVIEW only take dev_priv
0854f48 drm/i915: Make IS_G4X only take dev_priv
ca1ea2a drm/i915: Make HAS_L3_DPF only take dev_priv
04c5f83 drm/i915: Make IS_BROXTON only take dev_priv
d0c32be drm/i915: Make IS_SKYLAKE only take dev_priv
d8b0b94 drm/i915: Make IS_KABYLAKE only take dev_priv
444c507 drm/i915: Make IS_HASWELL only take dev_priv
b3d3b09 drm/i915: Make IS_BROADWELL only take dev_priv
6eaf5ac drm/i915: Make IS_IVYBRIDGE only take dev_priv
7f5c6d5 drm/i915: Make INTEL_DEVID only take dev_priv
e3b1e00 drm/i915: Make IS_GEN-range macro only take dev_priv
3fd6060 drm/i915: Do not use INTEL_INFO(dev_priv)->ring_mask inside WARNs
980e918 drm/i915: Make HAS_RUNTIME_PM only take dev_priv
f7b32d6 drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv
f7e3e43 drm/i915: Make INTEL_PCH_TYPE & co only take dev_priv
c18b0d8 drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread* ✓ Fi.CI.BAT: success for .rodata.str diet (rev2)
2016-10-11 13:21 [PATCH v2 00/19] .rodata.str diet Tvrtko Ursulin
` (19 preceding siblings ...)
2016-10-11 13:49 ` ✗ Fi.CI.BAT: warning for .rodata.str diet Patchwork
@ 2016-10-13 10:50 ` Patchwork
20 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2016-10-13 10:50 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: .rodata.str diet (rev2)
URL : https://patchwork.freedesktop.org/series/13583/
State : success
== Summary ==
Series 13583v2 .rodata.str diet
https://patchwork.freedesktop.org/api/1.0/series/13583/revisions/2/mbox/
Test kms_pipe_crc_basic:
Subgroup bad-source:
dmesg-warn -> PASS (fi-ilk-650)
Subgroup read-crc-pipe-a-frame-sequence:
dmesg-warn -> PASS (fi-ilk-650)
fi-bdw-5557u total:246 pass:231 dwarn:0 dfail:0 fail:0 skip:15
fi-bsw-n3050 total:246 pass:204 dwarn:0 dfail:0 fail:0 skip:42
fi-bxt-t5700 total:246 pass:216 dwarn:0 dfail:0 fail:0 skip:30
fi-byt-j1900 total:246 pass:212 dwarn:2 dfail:0 fail:1 skip:31
fi-byt-n2820 total:246 pass:210 dwarn:0 dfail:0 fail:1 skip:35
fi-hsw-4770 total:246 pass:223 dwarn:0 dfail:0 fail:0 skip:23
fi-hsw-4770r total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22
fi-ilk-650 total:246 pass:184 dwarn:0 dfail:0 fail:2 skip:60
fi-ivb-3520m total:246 pass:221 dwarn:0 dfail:0 fail:0 skip:25
fi-ivb-3770 total:246 pass:221 dwarn:0 dfail:0 fail:0 skip:25
fi-skl-6260u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14
fi-skl-6700hq total:246 pass:223 dwarn:0 dfail:0 fail:0 skip:23
fi-skl-6700k total:246 pass:221 dwarn:1 dfail:0 fail:0 skip:24
fi-skl-6770hq total:246 pass:230 dwarn:1 dfail:0 fail:1 skip:14
fi-snb-2520m total:246 pass:210 dwarn:0 dfail:0 fail:0 skip:36
fi-snb-2600 total:246 pass:209 dwarn:0 dfail:0 fail:0 skip:37
Results at /archive/results/CI_IGT_test/Patchwork_2699/
75d9d28f7f5d0147ba35e956268c3a3c079dc754 drm-intel-nightly: 2016y-10m-13d-09h-14m-05s UTC integration manifest
dbbd702 drm/i915: Make IS_GEN macros only take dev_priv
13bc123 drm/i915: Make INTEL_GEN only take dev_priv
900c851 drm/i915: Make IS_VALLEYVIEW only take dev_priv
37a0949 drm/i915: Make IS_CHERRYVIEW only take dev_priv
0769dc1 drm/i915: Make IS_G4X only take dev_priv
c51b0bf drm/i915: Make HAS_L3_DPF only take dev_priv
8a2da25 drm/i915: Make IS_BROXTON only take dev_priv
ab535b0 drm/i915: Make IS_SKYLAKE only take dev_priv
132b10d drm/i915: Make IS_KABYLAKE only take dev_priv
525bdad drm/i915: Make IS_HASWELL only take dev_priv
abe7804 drm/i915: Make IS_BROADWELL only take dev_priv
42c297b drm/i915: Make IS_IVYBRIDGE only take dev_priv
82fa58b drm/i915: Make INTEL_DEVID only take dev_priv
e9c70b6 drm/i915: Make IS_GEN-range macro only take dev_priv
d0c233f drm/i915: Do not use INTEL_INFO(dev_priv)->ring_mask inside WARNs
89d8348 drm/i915: Make HAS_RUNTIME_PM only take dev_priv
83b6ab1 drm/i915: Make HAS_GMCH_DISPLAY only take dev_priv
1a81c50 drm/i915: Make INTEL_PCH_TYPE & co only take dev_priv
bf86786 drm/i915: Make HAS_DDI and HAS_PCH_LPT_LP only take dev_priv
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 46+ messages in thread