From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org,
Jani Nikula <jani.nikula@linux.intel.com>,
"# v4 . 0+" <stable@vger.kernel.org>
Subject: Re: [PATCH] drm/i915: Mark CPU cache as dirty when used for rendering
Date: Mon, 7 Nov 2016 18:35:57 +0200 [thread overview]
Message-ID: <20161107163557.GZ4617@intel.com> (raw)
In-Reply-To: <20161107154628.32474-1-chris@chris-wilson.co.uk>
On Mon, Nov 07, 2016 at 03:46:28PM +0000, Chris Wilson wrote:
> On LLC, or even snooped, machines rendering via the GPU ends up in the CPU
> cache. This cacheline dirt also needs to be flushed to main memory when
> moving to an incoherent domain, such as the display's scanout engine.
> Mostly, this happens because either the object is marked as dirty from
> its first use or is avoided by setting the object into the display
> domain from the start.
>
> Fixes: 0f71979ab7fb ("drm/i915: Performed deferred clflush inside set-cache-level")
> References: https://bugs.freedesktop.org/show_bug.cgi?id=95414
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: <stable@vger.kernel.org> # v4.0+
> ---
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 30f6eb516ca3..30b684fecf09 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1282,6 +1282,7 @@ void i915_vma_move_to_active(struct i915_vma *vma,
>
> /* update for the implicit flush after a batch */
> obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
> + obj->cache_dirty |= obj->cache_level != I915_CACHE_NONE;
I915_CACHE_WT shouldn't dirty the cache either, so could be excluded
as well.
Everything else makes sense
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> }
>
> if (flags & EXEC_OBJECT_NEEDS_FENCE)
> --
> 2.10.2
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2016-11-07 16:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-07 15:46 [PATCH] drm/i915: Mark CPU cache as dirty when used for rendering Chris Wilson
2016-11-07 16:16 ` ✓ Fi.CI.BAT: success for " Patchwork
2016-11-07 16:35 ` Ville Syrjälä [this message]
2016-11-07 16:52 ` [PATCH v2] " Chris Wilson
2016-11-07 17:15 ` ✓ Fi.CI.BAT: success for drm/i915: Mark CPU cache as dirty when used for rendering (rev2) Patchwork
2016-11-07 20:59 ` Chris Wilson
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