[PATCH v3] drm/i915: fix the dequeue logic for single_port_submission context

[PATCH v3] drm/i915: fix the dequeue logic for single_port_submission context

[Min He]

For a singl_port_submission context, it can only be submitted to port 0,
and there shouldn't be any other context in port 1 at the same time. This
is required by GVT-g context to have an opportunity to save/restore some
non-hw context render registers.
This patch is to implement the correct logic in execlists_dequeue.

v2: optimized code by following Chris's advice, and added more comments to
explain the patch.
v3: followed the coding style.

Signed-off-by: Min He <min.he@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f50feaa..b2c0d50 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -499,7 +499,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 			 * context (even though a different request) to
 			 * the second port.
 			 */
-			if (ctx_single_port_submission(cursor->ctx))
+			if (ctx_single_port_submission(last->ctx) ||
+			    ctx_single_port_submission(cursor->ctx))
 				break;
 
 			GEM_BUG_ON(last->ctx == cursor->ctx);
-- 
1.9.1

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✓ Fi.CI.BAT: success for drm/i915: fix the dequeue logic for single_port_submission context (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: fix the dequeue logic for single_port_submission context (rev3)
URL   : https://patchwork.freedesktop.org/series/15391/
State : success

== Summary ==

Series 15391v3 drm/i915: fix the dequeue logic for single_port_submission context
https://patchwork.freedesktop.org/api/1.0/series/15391/revisions/3/mbox/


fi-bdw-5557u     total:244  pass:229  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050     total:244  pass:204  dwarn:0   dfail:0   fail:0   skip:40 
fi-byt-j1900     total:244  pass:216  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770      total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r     total:244  pass:224  dwarn:0   dfail:0   fail:0   skip:20 
fi-ilk-650       total:244  pass:191  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-ivb-3770      total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-kbl-7200u     total:244  pass:222  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6260u     total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hq    total:244  pass:223  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6700k     total:244  pass:222  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:244  pass:230  dwarn:0   dfail:0   fail:0   skip:14 
fi-snb-2520m     total:244  pass:212  dwarn:0   dfail:0   fail:0   skip:32 
fi-snb-2600      total:244  pass:211  dwarn:0   dfail:0   fail:0   skip:33 

6294f67611ebe69006c0e85c372efadcac8e9d66 drm-intel-nightly: 2016y-11m-16d-09h-57m-25s UTC integration manifest
d8671cd drm/i915: fix the dequeue logic for single_port_submission context

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3022/
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Re: [PATCH v3] drm/i915: fix the dequeue logic for single_port_submission context

[Zhenyu Wang]

[-- Attachment #1.1: Type: text/plain, Size: 1566 bytes --]

On 2016.11.16 22:05:04 +0800, Min He wrote:
> For a singl_port_submission context, it can only be submitted to port 0,
> and there shouldn't be any other context in port 1 at the same time. This
> is required by GVT-g context to have an opportunity to save/restore some
> non-hw context render registers.
> This patch is to implement the correct logic in execlists_dequeue.
> 
> v2: optimized code by following Chris's advice, and added more comments to
> explain the patch.
> v3: followed the coding style.
> 
> Signed-off-by: Min He <min.he@intel.com>
> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
> ---

Hi, Min, like Daniel said not need to add my s-o-b.

>  drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index f50feaa..b2c0d50 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -499,7 +499,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>  			 * context (even though a different request) to
>  			 * the second port.
>  			 */
> -			if (ctx_single_port_submission(cursor->ctx))
> +			if (ctx_single_port_submission(last->ctx) ||
> +			    ctx_single_port_submission(cursor->ctx))
>  				break;
>  
>  			GEM_BUG_ON(last->ctx == cursor->ctx);
> -- 
> 1.9.1
>

Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>

-- 
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827

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Re: [PATCH v3] drm/i915: fix the dequeue logic for single_port_submission context

[Chris Wilson]

On Wed, Nov 16, 2016 at 10:05:04PM +0800, Min He wrote:
> For a singl_port_submission context, it can only be submitted to port 0,
> and there shouldn't be any other context in port 1 at the same time. This
> is required by GVT-g context to have an opportunity to save/restore some
> non-hw context render registers.

This statement is not true. It has the opportunity to modify the GVT
context if a non-GVT context was in port 0 or port 1.

> This patch is to implement the correct logic in execlists_dequeue.

I object. This is not the correct logic here, but to workaround a
failure in GVT.

Any way pushed until GVT is fixed.
-Chris

-- 
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Re: [PATCH v3] drm/i915: fix the dequeue logic for single_port_submission context

[He, Min]

> -----Original Message-----
> From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
> Sent: Thursday, November 17, 2016 4:01 PM
> To: He, Min <min.he@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v3] drm/i915: fix the dequeue logic for
> single_port_submission context
> 
> On Wed, Nov 16, 2016 at 10:05:04PM +0800, Min He wrote:
> > For a singl_port_submission context, it can only be submitted to port 0,
> > and there shouldn't be any other context in port 1 at the same time. This
> > is required by GVT-g context to have an opportunity to save/restore some
> > non-hw context render registers.
> 
> This statement is not true. It has the opportunity to modify the GVT
> context if a non-GVT context was in port 0 or port 1.
If a non-GVT context is in port 0, and a GVT context in port 1, after non-GVT
context completes, GPU will switch to GVT context directly, and we will lose
the opportunity to save the non-GVT context registers and restore GVT context
registers. So non-GVT context's register will impact GVT context. 
And vice versa. 

> 
> > This patch is to implement the correct logic in execlists_dequeue.
> 
> I object. This is not the correct logic here, but to workaround a
> failure in GVT.
> 
> Any way pushed until GVT is fixed.
> -Chris
> 
> --
> Chris Wilson, Intel Open Source Technology Centre
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