From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 2/2] drm/i915/skl: Increase PCODE CDCLK change notify timeout
Date: Fri, 25 Nov 2016 13:30:38 +0200 [thread overview]
Message-ID: <20161125113038.GW31595@intel.com> (raw)
In-Reply-To: <1480071421-14559-1-git-send-email-imre.deak@intel.com>
On Fri, Nov 25, 2016 at 12:57:01PM +0200, Imre Deak wrote:
> commit 848496e5902833600f7992f4faa82dc1546051ba
> Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Date: Wed Jul 13 16:32:03 2016 +0300
>
> drm/i915: Wait up to 3ms for the pcu to ack the cdclk change request on SKL
>
> increased the timeout to match the spec, but we still see a timeout on
> at least one SKL. A CDCLK change request following the failed one will
> succeed nevertheless, so let's try to increase the timeout to 10ms.
>
> v2:
> - Use 1ms poll period instead of 10us. (Chris)
I'm not sure that's what we want. IIRC the spec says no delay between
attempts, so I'm not sure this isn't just going to make it more likely
to fail.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Reference: https://bugs.freedesktop.org/show_bug.cgi?id=97929
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5d11002..f07b611 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6261,7 +6261,7 @@ static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
>
> static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
> {
> - return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
> + return wait_for(skl_cdclk_pcu_ready(dev_priv), 10) == 0;
> }
>
> static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
> --
> 2.5.0
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2016-11-25 11:30 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-24 15:32 [PATCH 1/2] drm/i915/gen6+: Clear upper data byte during PCODE write Imre Deak
2016-11-24 15:32 ` [PATCH 2/2] drm/i915/skl: Increase PCODE CDCLK change notify timeout Imre Deak
2016-11-25 9:23 ` Chris Wilson
2016-11-25 9:32 ` Chris Wilson
2016-11-25 10:57 ` [PATCH v2 " Imre Deak
2016-11-25 11:00 ` Chris Wilson
2016-11-25 11:30 ` Ville Syrjälä [this message]
2016-11-25 11:44 ` Chris Wilson
2016-11-28 11:12 ` Imre Deak
2016-11-24 15:38 ` [PATCH 1/2] drm/i915/gen6+: Clear upper data byte during PCODE write Chris Wilson
2016-11-24 15:47 ` Ville Syrjälä
2016-11-24 17:15 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2016-11-25 11:15 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/gen6+: Clear upper data byte during PCODE write (rev2) Patchwork
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