From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 2/2] drm/i915/dp: Validate mode against max. link data rate for DP MST
Date: Mon, 5 Dec 2016 16:34:47 +0200 [thread overview]
Message-ID: <20161205143447.GG31595@intel.com> (raw)
In-Reply-To: <20161129202416.GY31595@intel.com>
On Tue, Nov 29, 2016 at 10:24:16PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 15, 2016 at 12:59:06PM -0800, Dhinakaran Pandiyan wrote:
> > Not validating the mode rate against max. link rate results in not pruning
> > invalid modes. For e.g, a HBR2 5.4 Gbps 2-lane configuration does not
> > support 4k@60Hz. But, we do not reject this mode.
> >
> > So, make use of the helpers in intel_dp to validate mode data rate against
> > max. link data rate of a configuration.
> >
> > v3: Renamed local variables again for consistency (Manasi)
> > v2: Renamed mode data rate local variable to be more explanatory.
> >
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
...and both patches pushed to dinq.
>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 4 ++--
> > drivers/gpu/drm/i915/intel_dp_mst.c | 12 +++++++++++-
> > drivers/gpu/drm/i915/intel_drv.h | 2 ++
> > 3 files changed, 15 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index bdef314..8a0c909 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -161,14 +161,14 @@ static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
> > return min(source_max, sink_max);
> > }
> >
> > -static int
> > +int
> > intel_dp_link_required(int pixel_clock, int bpp)
> > {
> > /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
> > return DIV_ROUND_UP(pixel_clock * bpp, 8);
> > }
> >
> > -static int
> > +int
> > intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> > {
> > /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
> > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> > index 3ffbd69..e21cf08 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > @@ -335,7 +335,17 @@ static enum drm_mode_status
> > intel_dp_mst_mode_valid(struct drm_connector *connector,
> > struct drm_display_mode *mode)
> > {
> > + struct intel_connector *intel_connector = to_intel_connector(connector);
> > + struct intel_dp *intel_dp = intel_connector->mst_port;
> > int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
> > + int bpp = 24; /* MST uses fixed bpp */
> > + int max_rate, mode_rate, max_lanes, max_link_clock;
> > +
> > + max_link_clock = intel_dp_max_link_rate(intel_dp);
> > + max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
> > +
> > + max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
> > + mode_rate = intel_dp_link_required(mode->clock, bpp);
> >
> > /* TODO - validate mode against available PBN for link */
> > if (mode->clock < 10000)
> > @@ -344,7 +354,7 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
> > if (mode->flags & DRM_MODE_FLAG_DBLCLK)
> > return MODE_H_ILLEGAL;
> >
> > - if (mode->clock > max_dotclk)
> > + if (mode_rate > max_rate || mode->clock > max_dotclk)
> > return MODE_CLOCK_HIGH;
> >
> > return MODE_OK;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index c2f3863..313419d 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1471,6 +1471,8 @@ bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
> > bool __intel_dp_read_desc(struct intel_dp *intel_dp,
> > struct intel_dp_desc *desc);
> > bool intel_dp_read_desc(struct intel_dp *intel_dp);
> > +int intel_dp_link_required(int pixel_clock, int bpp);
> > +int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
> >
> > /* intel_dp_aux_backlight.c */
> > int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
> > --
> > 2.7.4
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2016-12-05 14:34 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-14 21:42 [PATCH v2 1/2] drm/dp/i915: Fix DP link rate math Dhinakaran Pandiyan
2016-11-14 21:42 ` [PATCH v2 2/2] drm/i915/dp: Validate mode against max. link data rate for DP MST Dhinakaran Pandiyan
2016-11-15 20:59 ` [PATCH v3 " Dhinakaran Pandiyan
2016-11-29 20:24 ` Ville Syrjälä
2016-12-05 14:34 ` Ville Syrjälä [this message]
2016-11-14 21:50 ` [PATCH v2 1/2] drm/dp/i915: Fix DP link rate math Dhinakaran Pandiyan
2016-11-15 9:30 ` Jani Nikula
2016-11-15 18:46 ` Pandiyan, Dhinakaran
2016-11-29 20:22 ` Ville Syrjälä
2016-11-14 22:15 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/dp/i915: Fix DP link rate math (rev2) Patchwork
2016-11-15 5:07 ` [PATCH v2 1/2] drm/dp/i915: Fix DP link rate math kbuild test robot
2016-11-15 21:16 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/dp/i915: Fix DP link rate math (rev3) Patchwork
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