From: Manasi Navare <manasi.d.navare@intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dhinakaran.pandiyan@intel.com
Subject: Re: [PATCH v2 00/13] drm/i915/dp: link rate and lane count refactoring
Date: Tue, 7 Feb 2017 12:15:18 -0800 [thread overview]
Message-ID: <20170207201518.GA26663@intel.com> (raw)
In-Reply-To: <cover.1486131408.git.jani.nikula@intel.com>
Hi Jani,
Thanks for this patch series. This definitely makes use
of lane count and link rate cleaner while handling the link failures.
I have tested these patches with compliance device along with my pending
DRM link-status patches and it does the fallback as expected.
It does not solve the problem of max link rate/lane count getting reset
through ->detect callback from fill_modes(), but that will be fixed in a
separate patch.
As far as these patches, the fallback and compliance works properly:
Tested-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
On Fri, Feb 03, 2017 at 04:19:23PM +0200, Jani Nikula wrote:
> v2 of [1], rebased and review addressed.
>
> BR,
> Jani.
>
>
> [1] http://mid.mail-archive.com/cover.1485459621.git.jani.nikula@intel.com
>
>
> Jani Nikula (13):
> drm/i915/dp: use known correct array size in rate_to_index
> drm/i915/dp: return errors from rate_to_index()
> drm/i915/dp: rename rate_to_index() to intel_dp_rate_index() and reuse
> drm/i915/dp: cache source rates at init
> drm/i915/dp: generate and cache sink rate array for all DP, not just
> eDP 1.4
> drm/i915/dp: use the sink rates array for max sink rates
> drm/i915/dp: cache common rates with sink rates
> drm/i915/dp: do not limit rate seek when not needed
> drm/i915/dp: don't call the link parameters sink parameters
> drm/i915/dp: add functions for max common link rate and lane count
> drm/i915/mst: use max link not sink lane count
> drm/i915/dp: localize link rate index variable more
> drm/i915/dp: use readb and writeb calls for single byte DPCD access
>
> drivers/gpu/drm/i915/intel_dp.c | 284 ++++++++++++++------------
> drivers/gpu/drm/i915/intel_dp_link_training.c | 3 +-
> drivers/gpu/drm/i915/intel_dp_mst.c | 4 +-
> drivers/gpu/drm/i915/intel_drv.h | 20 +-
> 4 files changed, 173 insertions(+), 138 deletions(-)
>
> --
> 2.1.4
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
prev parent reply other threads:[~2017-02-07 20:16 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-03 14:19 [PATCH v2 00/13] drm/i915/dp: link rate and lane count refactoring Jani Nikula
2017-02-03 14:19 ` [PATCH v2 01/13] drm/i915/dp: use known correct array size in rate_to_index Jani Nikula
2017-02-03 14:19 ` [PATCH v2 02/13] drm/i915/dp: return errors from rate_to_index() Jani Nikula
2017-02-03 14:19 ` [PATCH v2 03/13] drm/i915/dp: rename rate_to_index() to intel_dp_rate_index() and reuse Jani Nikula
2017-02-03 14:19 ` [PATCH v2 04/13] drm/i915/dp: cache source rates at init Jani Nikula
2017-02-03 14:19 ` [PATCH v2 05/13] drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4 Jani Nikula
2017-02-03 17:16 ` Ville Syrjälä
2017-02-04 9:10 ` Jani Nikula
2017-02-03 14:19 ` [PATCH v2 06/13] drm/i915/dp: use the sink rates array for max sink rates Jani Nikula
2017-02-03 14:19 ` [PATCH v2 07/13] drm/i915/dp: cache common rates with " Jani Nikula
2017-02-03 14:19 ` [PATCH v2 08/13] drm/i915/dp: do not limit rate seek when not needed Jani Nikula
2017-02-03 14:19 ` [PATCH v2 09/13] drm/i915/dp: don't call the link parameters sink parameters Jani Nikula
2017-02-03 14:19 ` [PATCH v2 10/13] drm/i915/dp: add functions for max common link rate and lane count Jani Nikula
2017-02-03 14:19 ` [PATCH v2 11/13] drm/i915/mst: use max link not sink " Jani Nikula
2017-02-03 14:19 ` [PATCH v2 12/13] drm/i915/dp: localize link rate index variable more Jani Nikula
2017-02-07 20:17 ` Manasi Navare
2017-02-03 14:19 ` [PATCH v2 13/13] drm/i915/dp: use readb and writeb calls for single byte DPCD access Jani Nikula
2017-02-03 17:25 ` Ville Syrjälä
2017-02-03 16:56 ` ✗ Fi.CI.BAT: failure for drm/i915/dp: link rate and lane count refactoring (rev2) Patchwork
2017-02-07 20:15 ` Manasi Navare [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170207201518.GA26663@intel.com \
--to=manasi.d.navare@intel.com \
--cc=dhinakaran.pandiyan@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).