From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Navare, Manasi D" <manasi.d.navare@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: Power management test in DP compliance suite
Date: Thu, 8 Jun 2017 16:26:52 +0300 [thread overview]
Message-ID: <20170608132652.GO12629@intel.com> (raw)
In-Reply-To: <87E1A67218970041879FDD2045F7145D06F2D740@ORSMSX106.amr.corp.intel.com>
On Thu, Jun 08, 2017 at 12:59:23AM +0000, Navare, Manasi D wrote:
> Hi,
>
> I am executing the DP compliance test suite and the only test currently failing with the drm-tip + my patch (https://patchwork.freedesktop.org/series/25191/)
> Is the power management test (4.4.3) where it expects the source DUT to go into Power state D3 by setting DPCD register 0x600 to 2 as requested by the test GUI and then exit to normal operation by writing 1 to that DPCD register.
>
> I see that in the code intel_dp_sink_dpms() with DPMS_OFF will set that register to 2 and then with DPMS on it sets it to 1, but since that happens only during encoder disable and enable, I am not sure how it will happen through this test.
>
> Any thoughts? Please refer to the section 4.4.3 in the CTS spec.
There doesn't seem to support for automated test request for this stuff,
so it has to be done manually. What we should do in the test application
is ConnectorSetProperty(DPMS, OFF) + ConnectorSetProperty(DPMS, ON).
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2017-06-08 13:26 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-08 0:59 Power management test in DP compliance suite Navare, Manasi D
2017-06-08 13:26 ` Ville Syrjälä [this message]
2017-06-08 16:36 ` Navare, Manasi D
2017-06-08 17:19 ` Ville Syrjälä
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